31#ifndef _A2FXXXM3_ETH_DRIVER_H
32#define _A2FXXXM3_ETH_DRIVER_H
38#ifndef A2FXXXM3_ETH_TX_BUFFER_COUNT
39 #define A2FXXXM3_ETH_TX_BUFFER_COUNT 2
40#elif (A2FXXXM3_ETH_TX_BUFFER_COUNT < 1)
41 #error A2FXXXM3_ETH_TX_BUFFER_COUNT parameter is not valid
45#ifndef A2FXXXM3_ETH_TX_BUFFER_SIZE
46 #define A2FXXXM3_ETH_TX_BUFFER_SIZE 1536
47#elif (A2FXXXM3_ETH_TX_BUFFER_SIZE != 1536)
48 #error A2FXXXM3_ETH_TX_BUFFER_SIZE parameter is not valid
52#ifndef A2FXXXM3_ETH_RX_BUFFER_COUNT
53 #define A2FXXXM3_ETH_RX_BUFFER_COUNT 4
54#elif (A2FXXXM3_ETH_RX_BUFFER_COUNT < 1)
55 #error A2FXXXM3_ETH_RX_BUFFER_COUNT parameter is not valid
59#ifndef A2FXXXM3_ETH_RX_BUFFER_SIZE
60 #define A2FXXXM3_ETH_RX_BUFFER_SIZE 1536
61#elif (A2FXXXM3_ETH_RX_BUFFER_SIZE != 1536)
62 #error A2FXXXM3_ETH_RX_BUFFER_SIZE parameter is not valid
66#ifndef A2FXXXM3_ETH_IRQ_PRIORITY_GROUPING
67 #define A2FXXXM3_ETH_IRQ_PRIORITY_GROUPING 2
68#elif (A2FXXXM3_ETH_IRQ_PRIORITY_GROUPING < 0)
69 #error A2FXXXM3_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
73#ifndef A2FXXXM3_ETH_IRQ_GROUP_PRIORITY
74 #define A2FXXXM3_ETH_IRQ_GROUP_PRIORITY 24
75#elif (A2FXXXM3_ETH_IRQ_GROUP_PRIORITY < 0)
76 #error A2FXXXM3_ETH_IRQ_GROUP_PRIORITY parameter is not valid
80#ifndef A2FXXXM3_ETH_IRQ_SUB_PRIORITY
81 #define A2FXXXM3_ETH_IRQ_SUB_PRIORITY 0
82#elif (A2FXXXM3_ETH_IRQ_SUB_PRIORITY < 0)
83 #error A2FXXXM3_ETH_IRQ_SUB_PRIORITY parameter is not valid
88 #define CSR9_MDEN_MASK CSR9_MII_MASK
129 uint32_t hashFilter[32];
130 uint32_t reserved1[7];
131 uint32_t physicalAddr[3];
132 uint32_t reserved2[6];
140error_t a2fxxxm3EthInit(NetInterface *interface);
141void a2fxxxm3EthInitDmaDesc(NetInterface *interface);
143void a2fxxxm3EthTick(NetInterface *interface);
145void a2fxxxm3EthEnableIrq(NetInterface *interface);
146void a2fxxxm3EthDisableIrq(NetInterface *interface);
147void a2fxxxm3EthEventHandler(NetInterface *interface);
149error_t a2fxxxm3EthSendSetup(NetInterface *interface);
151error_t a2fxxxm3EthSendPacket(NetInterface *interface,
152 const NetBuffer *buffer,
size_t offset, NetTxAncillary *ancillary);
154error_t a2fxxxm3EthReceivePacket(NetInterface *interface);
156error_t a2fxxxm3EthUpdateMacAddrFilter(NetInterface *interface);
157error_t a2fxxxm3EthUpdateMacConfig(NetInterface *interface);
159void a2fxxxm3EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
160 uint8_t regAddr, uint16_t data);
162uint16_t a2fxxxm3EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
165void a2fxxxm3EthWriteSmi(uint32_t data, uint_t length);
166uint32_t a2fxxxm3EthReadSmi(uint_t length);
168uint32_t a2fxxxm3EthCalcCrc(
const void *data,
size_t length);
error_t
Error codes.
Definition error.h:43
Network interface controller abstraction layer.
Hash table setup frame.
Definition a2fxxxm3_eth_driver.h:128
Receive DMA descriptor.
Definition a2fxxxm3_eth_driver.h:115
Transmit DMA descriptor.
Definition a2fxxxm3_eth_driver.h:102
Structure describing a buffer that spans multiple chunks.
Definition net_mem.h:89
NIC driver.
Definition nic.h:283