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accel10 2.0.0.0
|
| #define ACCEL10_BDU_CONTINUOUS_UPDATE 0x00 |
| #define ACCEL10_BDU_NOT_UPDATE_MSB_LSB 0x08 |
| #define ACCEL10_BOOT_DISABLE 0x00 |
| #define ACCEL10_BOOT_ENABLE 0x80 |
| #define ACCEL10_BW_FILT_ODR10 0x80 |
| #define ACCEL10_BW_FILT_ODR2 0x00 |
| #define ACCEL10_BW_FILT_ODR20 0xC0 |
| #define ACCEL10_BW_FILT_ODR4 0x40 |
| #define ACCEL10_CS_PU_DISC_CONNECT 0x00 |
| #define ACCEL10_CS_PU_DISC_DISCONNECT 0x10 |
| #define ACCEL10_FS_16G 0x30 |
| #define ACCEL10_FS_2G 0x00 |
| #define ACCEL10_FS_4G 0x10 |
| #define ACCEL10_FS_8G 0x20 |
| #define ACCEL10_FSD_HIGH_PASS 0x08 |
| #define ACCEL10_FSD_LOW_PASS 0x00 |
| #define ACCEL10_H_LACTIVE_HIGH 0x00 |
| #define ACCEL10_H_LACTIVE_LOW 0x08 |
| #define ACCEL10_I2C_ENABLE_I2C_AND_SPI 0x00 |
| #define ACCEL10_I2C_ENABLE_SPI_ONLY 0x02 |
| #define ACCEL10_IF_ADD_INC_DISABLE 0x00 |
| #define ACCEL10_IF_ADD_INC_ENABLE 0x04 |
| #define ACCEL10_INT1_6D_DISABLE 0x00 |
| #define ACCEL10_INT1_6D_ENABLE 0x80 |
| #define ACCEL10_INT1_DIFF5_DISABLE 0x00 |
| #define ACCEL10_INT1_DIFF5_ENABLE 0x04 |
| #define ACCEL10_INT1_DRDY_DISABLE 0x00 |
| #define ACCEL10_INT1_DRDY_ENABLE 0x01 |
| #define ACCEL10_INT1_FF_DISABLE 0x00 |
| #define ACCEL10_INT1_FF_ENABLE 0x10 |
| #define ACCEL10_INT1_FTH_DISABLE 0x00 |
| #define ACCEL10_INT1_FTH_ENABLE 0x02 |
| #define ACCEL10_INT1_SINGLE_TAP_DISABLE 0x00 |
| #define ACCEL10_INT1_SINGLE_TAP_ENABLE 0x40 |
| #define ACCEL10_INT1_TAP_DISABLE 0x00 |
| #define ACCEL10_INT1_TAP_ENABLE 0x08 |
| #define ACCEL10_INT1_WU_DISABLE 0x00 |
| #define ACCEL10_INT1_WU_ENABLE 0x20 |
| #define ACCEL10_INT2_BOOT_DISABLE 0x00 |
| #define ACCEL10_INT2_BOOT_ENABLE 0x20 |
| #define ACCEL10_INT2_DIFF5_DISABLE 0x00 |
| #define ACCEL10_INT2_DIFF5_ENABLE 0x04 |
| #define ACCEL10_INT2_DRDY_DISABLE 0x00 |
| #define ACCEL10_INT2_DRDY_ENABLE 0x01 |
| #define ACCEL10_INT2_DRDY_T_DISABLE 0x00 |
| #define ACCEL10_INT2_DRDY_T_ENABLE 0x10 |
| #define ACCEL10_INT2_FTH_DISABLE 0x00 |
| #define ACCEL10_INT2_FTH_ENABLE 0x02 |
| #define ACCEL10_INT2_OVR_DISABLE 0x00 |
| #define ACCEL10_INT2_OVR_ENABLE 0x08 |
| #define ACCEL10_INT2_SLEEP_CHG_DISABLE 0x00 |
| #define ACCEL10_INT2_SLEEP_CHG_ENABLE 0x40 |
| #define ACCEL10_INT2_SLEEP_STATE_DISABLE 0x00 |
| #define ACCEL10_INT2_SLEEP_STATE_ENABLE 0x80 |
| #define ACCEL10_LIR_LATCHED 0x10 |
| #define ACCEL10_LIR_NOT_LATCHED 0x00 |
| #define ACCEL10_LOW_NOISE_DISABLE 0x00 |
| #define ACCEL10_LOW_NOISE_ENABLE 0x04 |
| #define ACCEL10_LP_MODE_1 0x00 |
| #define ACCEL10_LP_MODE_2 0x01 |
| #define ACCEL10_LP_MODE_3 0x02 |
| #define ACCEL10_LP_MODE_4 0x03 |
| #define ACCEL10_MODE_HIGH_PERF 0x04 |
| #define ACCEL10_MODE_LOW_POWER 0x00 |
| #define ACCEL10_MODE_SINGLE_CONV 0x08 |
| #define ACCEL10_ODR_100Hz 0x50 |
| #define ACCEL10_ODR_12_5_1_6HZ 0x10 |
| #define ACCEL10_ODR_12_5Hz 0x20 |
| #define ACCEL10_ODR_1600_200Hz 0x90 |
| #define ACCEL10_ODR_200Hz 0x60 |
| #define ACCEL10_ODR_25Hz 0x30 |
| #define ACCEL10_ODR_400_200Hz 0x70 |
| #define ACCEL10_ODR_50Hz 0x40 |
| #define ACCEL10_ODR_800_200Hz 0x80 |
| #define ACCEL10_ODR_POWER_DOWN 0x00 |
| #define ACCEL10_PP_OD_OPEN_DRAIN 0x20 |
| #define ACCEL10_PP_OD_PUSH_PULL 0x00 |
| #define ACCEL10_SIM_3_WIRE 0x01 |
| #define ACCEL10_SIM_4_WIRE 0x00 |
| #define ACCEL10_SLP_MODE_1_CONV_START 0x01 |
| #define ACCEL10_SLP_MODE_SEL_EN_INT2 0x00 |
| #define ACCEL10_SLP_MODE_SEL_EN_MODE1 0x02 |
| #define ACCEL10_SOFT_RESET_DISABLE 0x00 |
| #define ACCEL10_SOFT_RESET_ENABLE 0x40 |
| #define ACCEL10_ST_NEGATIVE 0x80 |
| #define ACCEL10_ST_NORMAL 0x00 |
| #define ACCEL10_ST_POSITIVE 0x40 |