Macros
#define	ACCEL10_REG_OUT_T_L 0x0D

#define	ACCEL10_REG_OUT_T_H 0x0E

#define	ACCEL10_REG_WHO_AM_I 0x0F

#define	ACCEL10_REG_CTRL1 0x20

#define	ACCEL10_REG_CTRL2 0x21

#define	ACCEL10_REG_CTRL3 0x22

#define	ACCEL10_REG_CTRL4_INT1_PAD_CTRL 0x23

#define	ACCEL10_REG_CTRL5_INT2_PAD_CTRL 0x24

#define	ACCEL10_REG_CTRL6 0x25

#define	ACCEL10_REG_OUT_T 0x26

#define	ACCEL10_REG_STATUS 0x27

#define	ACCEL10_REG_OUT_X_L 0x28

#define	ACCEL10_REG_OUT_X_H 0x29

#define	ACCEL10_REG_OUT_Y_L 0x2A

#define	ACCEL10_REG_OUT_Y_H 0x2B

#define	ACCEL10_REG_OUT_Z_L 0x2C

#define	ACCEL10_REG_OUT_Z_H 0x2D

#define	ACCEL10_REG_FIFO_CTRL 0x2E

#define	ACCEL10_REG_FIFO_SAMPLES 0x2F

#define	ACCEL10_REG_TAP_THS_X 0x30

#define	ACCEL10_REG_TAP_THS_Y 0x31

#define	ACCEL10_REG_TAP_THS_Z 0x32

#define	ACCEL10_REG_INT_DUR 0x33

#define	ACCEL10_REG_WAKE_UP_THS 0x34

#define	ACCEL10_REG_WAKE_UP_DUR 0x35

#define	ACCEL10_REG_FREE_FALL 0x36

#define	ACCEL10_REG_STATUS_DUP 0x37

#define	ACCEL10_REG_WAKE_UP_SRC 0x38

#define	ACCEL10_REG_TAP_SRC 0x39

#define	ACCEL10_REG_SIXD_SRC 0x3A

#define	ACCEL10_REG_ALL_INT_SRC 0x3B

#define	ACCEL10_REG_X_OFS_USR 0x3C

#define	ACCEL10_REG_Y_OFS_USR 0x3D

#define	ACCEL10_REG_Z_OFS_USR 0x3E

#define	ACCEL10_REG_CTRL_REG7 0x3F

Detailed Description

Macro Definition Documentation

◆ ACCEL10_REG_ALL_INT_SRC

#define ACCEL10_REG_ALL_INT_SRC 0x3B

◆ ACCEL10_REG_CTRL1

#define ACCEL10_REG_CTRL1 0x20

◆ ACCEL10_REG_CTRL2

#define ACCEL10_REG_CTRL2 0x21

◆ ACCEL10_REG_CTRL3

#define ACCEL10_REG_CTRL3 0x22

◆ ACCEL10_REG_CTRL4_INT1_PAD_CTRL

#define ACCEL10_REG_CTRL4_INT1_PAD_CTRL 0x23

◆ ACCEL10_REG_CTRL5_INT2_PAD_CTRL

#define ACCEL10_REG_CTRL5_INT2_PAD_CTRL 0x24

◆ ACCEL10_REG_CTRL6

#define ACCEL10_REG_CTRL6 0x25

◆ ACCEL10_REG_CTRL_REG7

#define ACCEL10_REG_CTRL_REG7 0x3F

◆ ACCEL10_REG_FIFO_CTRL

#define ACCEL10_REG_FIFO_CTRL 0x2E

◆ ACCEL10_REG_FIFO_SAMPLES

#define ACCEL10_REG_FIFO_SAMPLES 0x2F

◆ ACCEL10_REG_FREE_FALL

#define ACCEL10_REG_FREE_FALL 0x36

◆ ACCEL10_REG_INT_DUR

#define ACCEL10_REG_INT_DUR 0x33

◆ ACCEL10_REG_OUT_T

#define ACCEL10_REG_OUT_T 0x26

◆ ACCEL10_REG_OUT_T_H

#define ACCEL10_REG_OUT_T_H 0x0E

◆ ACCEL10_REG_OUT_T_L

#define ACCEL10_REG_OUT_T_L 0x0D

◆ ACCEL10_REG_OUT_X_H

#define ACCEL10_REG_OUT_X_H 0x29

◆ ACCEL10_REG_OUT_X_L

#define ACCEL10_REG_OUT_X_L 0x28

◆ ACCEL10_REG_OUT_Y_H

#define ACCEL10_REG_OUT_Y_H 0x2B

◆ ACCEL10_REG_OUT_Y_L

#define ACCEL10_REG_OUT_Y_L 0x2A

◆ ACCEL10_REG_OUT_Z_H

#define ACCEL10_REG_OUT_Z_H 0x2D

◆ ACCEL10_REG_OUT_Z_L

#define ACCEL10_REG_OUT_Z_L 0x2C

◆ ACCEL10_REG_SIXD_SRC

#define ACCEL10_REG_SIXD_SRC 0x3A

◆ ACCEL10_REG_STATUS

#define ACCEL10_REG_STATUS 0x27

◆ ACCEL10_REG_STATUS_DUP

#define ACCEL10_REG_STATUS_DUP 0x37

◆ ACCEL10_REG_TAP_SRC

#define ACCEL10_REG_TAP_SRC 0x39

◆ ACCEL10_REG_TAP_THS_X

#define ACCEL10_REG_TAP_THS_X 0x30

◆ ACCEL10_REG_TAP_THS_Y

#define ACCEL10_REG_TAP_THS_Y 0x31

◆ ACCEL10_REG_TAP_THS_Z

#define ACCEL10_REG_TAP_THS_Z 0x32

◆ ACCEL10_REG_WAKE_UP_DUR

#define ACCEL10_REG_WAKE_UP_DUR 0x35

◆ ACCEL10_REG_WAKE_UP_SRC

#define ACCEL10_REG_WAKE_UP_SRC 0x38

◆ ACCEL10_REG_WAKE_UP_THS

#define ACCEL10_REG_WAKE_UP_THS 0x34

◆ ACCEL10_REG_WHO_AM_I

#define ACCEL10_REG_WHO_AM_I 0x0F

◆ ACCEL10_REG_X_OFS_USR

#define ACCEL10_REG_X_OFS_USR 0x3C

◆ ACCEL10_REG_Y_OFS_USR

#define ACCEL10_REG_Y_OFS_USR 0x3D

◆ ACCEL10_REG_Z_OFS_USR

#define ACCEL10_REG_Z_OFS_USR 0x3E

Macros