Macros
#define	ACCEL14_CTRL1_XL_POWER_BIT_MASK 0xE0

#define	ACCEL14_CTRL1_XL_POWER_DOWN 0x00

#define	ACCEL14_CTRL1_XL_POWER_UP 0xA0

#define	ACCEL14_CTRL1_XL_HIGH_RES_BIT_MASK 0x02

#define	ACCEL14_CTRL1_XL_HIGH_RES_FS 0x00

#define	ACCEL14_CTRL1_XL_HIGH_RES_SS 0x02

#define	ACCEL14_CTRL1_XL_GSEL_BIT_MASK 0x0C

#define	ACCEL14_CTRL1_XL_GSEL_2G 0x00

#define	ACCEL14_CTRL1_XL_GSEL_16G 0x04

#define	ACCEL14_CTRL1_XL_GSEL_4G 0x08

#define	ACCEL14_CTRL1_XL_GSEL_8G 0x0C

#define	ACCEL14_COEF_RES_2G 0.061

#define	ACCEL14_COEF_RES_4G 0.122

#define	ACCEL14_COEF_RES_8G 0.244

#define	ACCEL14_COEF_RES_16G 0.488

Detailed Description

Macro Definition Documentation

◆ ACCEL14_COEF_RES_16G

#define ACCEL14_COEF_RES_16G 0.488

◆ ACCEL14_COEF_RES_2G

#define ACCEL14_COEF_RES_2G 0.061

◆ ACCEL14_COEF_RES_4G

#define ACCEL14_COEF_RES_4G 0.122

◆ ACCEL14_COEF_RES_8G

#define ACCEL14_COEF_RES_8G 0.244

◆ ACCEL14_CTRL1_XL_GSEL_16G

#define ACCEL14_CTRL1_XL_GSEL_16G 0x04

◆ ACCEL14_CTRL1_XL_GSEL_2G

#define ACCEL14_CTRL1_XL_GSEL_2G 0x00

◆ ACCEL14_CTRL1_XL_GSEL_4G

#define ACCEL14_CTRL1_XL_GSEL_4G 0x08

◆ ACCEL14_CTRL1_XL_GSEL_8G

#define ACCEL14_CTRL1_XL_GSEL_8G 0x0C

◆ ACCEL14_CTRL1_XL_GSEL_BIT_MASK

#define ACCEL14_CTRL1_XL_GSEL_BIT_MASK 0x0C

◆ ACCEL14_CTRL1_XL_HIGH_RES_BIT_MASK

#define ACCEL14_CTRL1_XL_HIGH_RES_BIT_MASK 0x02

◆ ACCEL14_CTRL1_XL_HIGH_RES_FS

#define ACCEL14_CTRL1_XL_HIGH_RES_FS 0x00

◆ ACCEL14_CTRL1_XL_HIGH_RES_SS

#define ACCEL14_CTRL1_XL_HIGH_RES_SS 0x02

◆ ACCEL14_CTRL1_XL_POWER_BIT_MASK

#define ACCEL14_CTRL1_XL_POWER_BIT_MASK 0xE0

◆ ACCEL14_CTRL1_XL_POWER_DOWN

#define ACCEL14_CTRL1_XL_POWER_DOWN 0x00

◆ ACCEL14_CTRL1_XL_POWER_UP

#define ACCEL14_CTRL1_XL_POWER_UP 0xA0

Macros