Settings for registers of Accel 20 Click driver. More...

Macros
#define	ACCEL20_INTERNAL_SOFT_RESET 0x00
	Accel 20 description setting.

#define	ACCEL20_SOFT_RESET_PWR_CYC 0x00

#define	ACCEL20_SOFT_RESET_REBOOT 0x80

#define	ACCEL20_CNTL1_RANGE_8g 0x00

#define	ACCEL20_CNTL1_RANGE_16g 0x01

#define	ACCEL20_CNTL1_RANGE_32g 0x02

#define	ACCEL20_CNTL1_RANGE_64g 0x03

#define	ACCEL20_RANGE_BIT_MASK 0xE7

#define	ACCEL20_ODCNTL_ODR_0_781_Hz 0x00

#define	ACCEL20_ODCNTL_ODR_1_563_Hz 0x01

#define	ACCEL20_ODCNTL_ODR_3_125_Hz 0x02

#define	ACCEL20_ODCNTL_ODR_6_25_Hz 0x03

#define	ACCEL20_ODCNTL_ODR_12_5_Hz 0x04

#define	ACCEL20_ODCNTL_ODR_25_Hz 0x05

#define	ACCEL20_ODCNTL_ODR_50_Hz 0x06

#define	ACCEL20_ODCNTL_ODR_100_Hz 0x07

#define	ACCEL20_ODCNTL_ODR_200_Hz 0x08

#define	ACCEL20_ODCNTL_ODR_400_Hz 0x09

#define	ACCEL20_ODCNTL_ODR_800_Hz 0x0A

#define	ACCEL20_ODCNTL_ODR_1600_Hz 0x0B

#define	ACCEL20_ODCNTL_ODR_3200_Hz 0x0C

#define	ACCEL20_ODCNTL_ODR_6400_Hz 0x0D

#define	ACCEL20_ODCNTL_ODR_12800_Hz 0x0E

#define	ACCEL20_ODCNTL_ODR_25600_Hz 0x0F

#define	ACCEL20_ODR_BIT_MASK 0x0F

#define	ACCEL20_CNTL1_OP_MODE_STB 0x00

#define	ACCEL20_CNTL1_OP_MODE_L_PWR 0x02

#define	ACCEL20_CNTL1_OP_MODE_HP 0x03

#define	ACCEL20_OP_MODE_BIT_MASK 0xC0

#define	ACCEL20_ENABLE_INT_1 0x30

#define	ACCEL20_ENABLE_DATA_READY 0x10

#define	ACCEL20_DATA_READY_BIT_MASK 0x10

#define	ACCEL20_INT1_DATA_READY 0x00

#define	ACCEL20_CHIP_ID 0x46

#define	ACCEL20_TRIGGER_DISABLE 0x00

#define	ACCEL20_TRIGGER_ENABLE 0x01

#define	ACCEL20_SET_DEV_ADDR_GND 0x1E
	Accel 20 device address setting.

#define	ACCEL20_SET_DEV_ADDR_VCC 0x1F

#define	ACCEL20_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE
	Data sample selection.

#define	ACCEL20_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE

Detailed Description

Settings for registers of Accel 20 Click driver.

Macro Definition Documentation

◆ ACCEL20_CHIP_ID

#define ACCEL20_CHIP_ID 0x46

◆ ACCEL20_CNTL1_OP_MODE_HP

#define ACCEL20_CNTL1_OP_MODE_HP 0x03

◆ ACCEL20_CNTL1_OP_MODE_L_PWR

#define ACCEL20_CNTL1_OP_MODE_L_PWR 0x02

◆ ACCEL20_CNTL1_OP_MODE_STB

#define ACCEL20_CNTL1_OP_MODE_STB 0x00

◆ ACCEL20_CNTL1_RANGE_16g

#define ACCEL20_CNTL1_RANGE_16g 0x01

◆ ACCEL20_CNTL1_RANGE_32g

#define ACCEL20_CNTL1_RANGE_32g 0x02

◆ ACCEL20_CNTL1_RANGE_64g

#define ACCEL20_CNTL1_RANGE_64g 0x03

◆ ACCEL20_CNTL1_RANGE_8g

#define ACCEL20_CNTL1_RANGE_8g 0x00

◆ ACCEL20_DATA_READY_BIT_MASK

#define ACCEL20_DATA_READY_BIT_MASK 0x10

◆ ACCEL20_ENABLE_DATA_READY

#define ACCEL20_ENABLE_DATA_READY 0x10

◆ ACCEL20_ENABLE_INT_1

#define ACCEL20_ENABLE_INT_1 0x30

◆ ACCEL20_INT1_DATA_READY

#define ACCEL20_INT1_DATA_READY 0x00

◆ ACCEL20_INTERNAL_SOFT_RESET

#define ACCEL20_INTERNAL_SOFT_RESET 0x00

Accel 20 description setting.

Specified setting for description of Accel 20 Click driver.

◆ ACCEL20_ODCNTL_ODR_0_781_Hz

#define ACCEL20_ODCNTL_ODR_0_781_Hz 0x00

◆ ACCEL20_ODCNTL_ODR_100_Hz

#define ACCEL20_ODCNTL_ODR_100_Hz 0x07

◆ ACCEL20_ODCNTL_ODR_12800_Hz

#define ACCEL20_ODCNTL_ODR_12800_Hz 0x0E

◆ ACCEL20_ODCNTL_ODR_12_5_Hz

#define ACCEL20_ODCNTL_ODR_12_5_Hz 0x04

◆ ACCEL20_ODCNTL_ODR_1600_Hz

#define ACCEL20_ODCNTL_ODR_1600_Hz 0x0B

◆ ACCEL20_ODCNTL_ODR_1_563_Hz

#define ACCEL20_ODCNTL_ODR_1_563_Hz 0x01

◆ ACCEL20_ODCNTL_ODR_200_Hz

#define ACCEL20_ODCNTL_ODR_200_Hz 0x08

◆ ACCEL20_ODCNTL_ODR_25600_Hz

#define ACCEL20_ODCNTL_ODR_25600_Hz 0x0F

◆ ACCEL20_ODCNTL_ODR_25_Hz

#define ACCEL20_ODCNTL_ODR_25_Hz 0x05

◆ ACCEL20_ODCNTL_ODR_3200_Hz

#define ACCEL20_ODCNTL_ODR_3200_Hz 0x0C

◆ ACCEL20_ODCNTL_ODR_3_125_Hz

#define ACCEL20_ODCNTL_ODR_3_125_Hz 0x02

◆ ACCEL20_ODCNTL_ODR_400_Hz

#define ACCEL20_ODCNTL_ODR_400_Hz 0x09

◆ ACCEL20_ODCNTL_ODR_50_Hz

#define ACCEL20_ODCNTL_ODR_50_Hz 0x06

◆ ACCEL20_ODCNTL_ODR_6400_Hz

#define ACCEL20_ODCNTL_ODR_6400_Hz 0x0D

◆ ACCEL20_ODCNTL_ODR_6_25_Hz

#define ACCEL20_ODCNTL_ODR_6_25_Hz 0x03

◆ ACCEL20_ODCNTL_ODR_800_Hz

#define ACCEL20_ODCNTL_ODR_800_Hz 0x0A

◆ ACCEL20_ODR_BIT_MASK

#define ACCEL20_ODR_BIT_MASK 0x0F

◆ ACCEL20_OP_MODE_BIT_MASK

#define ACCEL20_OP_MODE_BIT_MASK 0xC0

◆ ACCEL20_RANGE_BIT_MASK

#define ACCEL20_RANGE_BIT_MASK 0xE7

◆ ACCEL20_SET_DATA_SAMPLE_EDGE

#define ACCEL20_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE

Data sample selection.

This macro sets data samples for SPI modules.

Note: Available only on Microchip PIC family devices. This macro will set data sampling for all SPI modules on MCU. Can be overwritten with accel20_init which will set SET_SPI_DATA_SAMPLE_MIDDLE by default on the mapped mikrobus.

◆ ACCEL20_SET_DATA_SAMPLE_MIDDLE

#define ACCEL20_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE

◆ ACCEL20_SET_DEV_ADDR_GND

#define ACCEL20_SET_DEV_ADDR_GND 0x1E

Accel 20 device address setting.

Specified setting for device slave address selection of Accel 20 Click driver.

◆ ACCEL20_SET_DEV_ADDR_VCC

#define ACCEL20_SET_DEV_ADDR_VCC 0x1F

◆ ACCEL20_SOFT_RESET_PWR_CYC

#define ACCEL20_SOFT_RESET_PWR_CYC 0x00

◆ ACCEL20_SOFT_RESET_REBOOT

#define ACCEL20_SOFT_RESET_REBOOT 0x80

◆ ACCEL20_TRIGGER_DISABLE

#define ACCEL20_TRIGGER_DISABLE 0x00

◆ ACCEL20_TRIGGER_ENABLE

#define ACCEL20_TRIGGER_ENABLE 0x01

Macros