|
#define | ACCEL29_INT_ENABLE_DATA_READY 0x80 |
| Accel 29 INT_ENABLE register setting.
|
|
#define | ACCEL29_INT_ENABLE_ACTIVITY 0x10 |
|
#define | ACCEL29_INT_ENABLE_INACTIVITY 0x08 |
|
#define | ACCEL29_INT_ENABLE_OVERRUN 0x01 |
|
#define | ACCEL29_INT_MAP_DATA_READY_INT2 0x80 |
| Accel 29 INT_MAP register setting.
|
|
#define | ACCEL29_INT_MAP_DATA_READY_INT1 0x00 |
|
#define | ACCEL29_INT_MAP_DATA_READY_MASK 0x80 |
|
#define | ACCEL29_INT_MAP_ACTIVITY_INT2 0x10 |
|
#define | ACCEL29_INT_MAP_ACTIVITY_INT1 0x00 |
|
#define | ACCEL29_INT_MAP_ACTIVITY_MASK 0x10 |
|
#define | ACCEL29_INT_MAP_INACTIVITY_INT2 0x08 |
|
#define | ACCEL29_INT_MAP_INACTIVITY_INT1 0x00 |
|
#define | ACCEL29_INT_MAP_INACTIVITY_MASK 0x08 |
|
#define | ACCEL29_INT_MAP_OVERRUN_INT2 0x01 |
|
#define | ACCEL29_INT_MAP_OVERRUN_INT1 0x00 |
|
#define | ACCEL29_INT_MAP_OVERRUN_MASK 0x01 |
|
#define | ACCEL29_INT_SOURCE_DATA_READY 0x80 |
| Accel 29 INT_SOURCE register setting.
|
|
#define | ACCEL29_INT_SOURCE_ACTIVITY 0x10 |
|
#define | ACCEL29_INT_SOURCE_INACTIVITY 0x08 |
|
#define | ACCEL29_INT_SOURCE_OVERRUN 0x01 |
|
#define | ACCEL29_BW_RATE_LOW_POWER 0x10 |
| Accel 29 BW_RATE register setting.
|
|
#define | ACCEL29_BW_RATE_6_25_HZ 0x06 |
|
#define | ACCEL29_BW_RATE_12_5_HZ 0x07 |
|
#define | ACCEL29_BW_RATE_25_HZ 0x08 |
|
#define | ACCEL29_BW_RATE_50_HZ 0x09 |
|
#define | ACCEL29_BW_RATE_100_HZ 0x0A |
|
#define | ACCEL29_BW_RATE_200_HZ 0x0B |
|
#define | ACCEL29_BW_RATE_400_HZ 0x0C |
|
#define | ACCEL29_BW_RATE_800_HZ 0x0D |
|
#define | ACCEL29_BW_RATE_1600_HZ 0x0E |
|
#define | ACCEL29_BW_RATE_3200_HZ 0x0F |
|
#define | ACCEL29_POWER_CTL_LINK 0x20 |
| Accel 29 POWER_CTL register setting.
|
|
#define | ACCEL29_POWER_CTL_AUTO_SLEEP 0x10 |
|
#define | ACCEL29_POWER_CTL_MEASURE 0x08 |
|
#define | ACCEL29_POWER_CTL_SLEEP 0x04 |
|
#define | ACCEL29_POWER_CTL_WAKEUP_8_HZ 0x00 |
|
#define | ACCEL29_POWER_CTL_WAKEUP_4_HZ 0x01 |
|
#define | ACCEL29_POWER_CTL_WAKEUP_2_HZ 0x02 |
|
#define | ACCEL29_POWER_CTL_WAKEUP_1_HZ 0x03 |
|
#define | ACCEL29_POWER_CTL_WAKEUP_MASK 0x03 |
|
#define | ACCEL29_DEVID 0xE5 |
| Accel 29 device ID setting.
|
|
#define | ACCEL29_OFS_RESET 0 |
| Accel 29 offset settings.
|
|
#define | ACCEL29_OFS_SCALE_FACTOR_G_PER_LSB 0.195f |
|
#define | ACCEL29_SCALE_FACTOR_LSB_PER_G 20.48f |
| Accel 29 data resolution settings.
|
|
#define | ACCEL29_NUM_OF_SAMPLES 100 |
| Accel 29 number of data samples for averaging.
|
|
#define | ACCEL29_SPI_RW_BIT 0x80 |
| Accel 29 communication frame setting.
|
|
#define | ACCEL29_SPI_MB_BIT 0x40 |
|
#define | ACCEL29_ADDRESS_MASK 0x3F |
|
#define | ACCEL29_DEVICE_ADDRESS_0 0x53 |
| Accel 29 device address setting.
|
|
#define | ACCEL29_DEVICE_ADDRESS_1 0x1D |
|
#define | ACCEL29_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE |
| Data sample selection.
|
|
#define | ACCEL29_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE |
|