accel30.h

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/****************************************************************************
** Copyright (C) 2020 MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and associated documentation files (the "Software"), to deal
** in the Software without restriction, including without limitation the rights
** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
** copies of the Software, and to permit persons to whom the Software is
** furnished to do so, subject to the following conditions:
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
**  USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/
 
#ifndef ACCEL30_H
#define ACCEL30_H
 
#ifdef __cplusplus
extern "C"{
#endif
 
#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_i2c_master.h"
#include "drv_spi_master.h"
#include "spi_specifics.h"
 
#define ACCEL30_REG_EXT_STAT_1                0x00
#define ACCEL30_REG_EXT_STAT_2                0x01
#define ACCEL30_REG_XOUT_LSB                  0x02
#define ACCEL30_REG_XOUT_MSB                  0x03
#define ACCEL30_REG_YOUT_LSB                  0x04
#define ACCEL30_REG_YOUT_MSB                  0x05
#define ACCEL30_REG_ZOUT_LSB                  0x06
#define ACCEL30_REG_ZOUT_MSB                  0x07
#define ACCEL30_REG_STATUS_1                  0x08
#define ACCEL30_REG_STATUS_2                  0x09
#define ACCEL30_REG_FREG_1                    0x0D
#define ACCEL30_REG_FREG_2                    0x0E
#define ACCEL30_REG_INIT_1                    0x0F
#define ACCEL30_REG_MODE_C                    0x10
#define ACCEL30_REG_WAKE_C                    0x11
#define ACCEL30_REG_SNIFF_C                   0x12
#define ACCEL30_REG_SNIFFTH_C                 0x13
#define ACCEL30_REG_SNIFFCF_C                 0x14
#define ACCEL30_REG_RANGE_C                   0x15
#define ACCEL30_REG_FIFO_C                    0x16
#define ACCEL30_REG_INTR_C                    0x17
#define ACCEL30_REG_INIT_3                    0x1A
#define ACCEL30_REG_SCRATCH                   0x1B
#define ACCEL30_REG_POWER_MODE                0x1C
#define ACCEL30_REG_DMX                       0x20
#define ACCEL30_REG_DMY                       0x21
#define ACCEL30_REG_DMZ                       0x22
#define ACCEL30_REG_RESET                     0x24
#define ACCEL30_REG_INIT_2                    0x28
#define ACCEL30_REG_TRIGC                     0x29
#define ACCEL30_REG_XOFFL                     0x2A
#define ACCEL30_REG_XOFFH                     0x2B
#define ACCEL30_REG_YOFFL                     0x2C
#define ACCEL30_REG_YOFFH                     0x2D
#define ACCEL30_REG_ZOFFL                     0x2E
#define ACCEL30_REG_ZOFFH                     0x2F
#define ACCEL30_REG_XGAIN                     0x30
#define ACCEL30_REG_YGAIN                     0x31
#define ACCEL30_REG_ZGAIN                     0x32
#define ACCEL30_REG_OPT                       0x3B
#define ACCEL30_REG_GAIN                      0x21
 
 
 // accel30_reg
 
#define ACCEL30_MODE_BIT_MASK                 0xF0
#define ACCEL30_RANGE_BIT_MASK                0x07
#define ACCEL30_GAIN_BIT_MASK                 0x3F
#define ACCEL30_RESOLUTION_BIT_MASK           0x70
#define ACCEL30_DMX_PN_DISABLE                0x00
#define ACCEL30_DMX_RES_BIT_MASK              0x01
#define ACCEL30_ENABLE_XYZ_AXIS_PD            0x00
#define ACCEL30_TRIG_CMD_CONTINUOUS           0x00
#define ACCEL30_TRIG_CMD_ONE_SHOT             0x01
#define ACCEL30_FORCE_RESET                   0x40
#define ACCEL30_I2C_ENABLE                    0x40
#define ACCEL30_SPI_ENABLE                    0x80
#define ACCEL30_MODE_BIT_MASK                 0xF0
 
#define ACCEL30_DEVICE_ADDRESS_GND            0x4C
#define ACCEL30_DEVICE_ADDRESS_VCC            0x6C
 
#define ACCEL30_SET_DATA_SAMPLE_EDGE      SET_SPI_DATA_SAMPLE_EDGE
#define ACCEL30_SET_DATA_SAMPLE_MIDDLE    SET_SPI_DATA_SAMPLE_MIDDLE
 
 // accel30_set
 
#define ACCEL30_MAP_MIKROBUS( cfg, mikrobus )       \
    cfg.scl  = MIKROBUS( mikrobus, MIKROBUS_SCL );  \
    cfg.sda  = MIKROBUS( mikrobus, MIKROBUS_SDA );  \
    cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
    cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
    cfg.sck  = MIKROBUS( mikrobus, MIKROBUS_SCK );  \
    cfg.cs   = MIKROBUS( mikrobus, MIKROBUS_CS );   \
    cfg.rst = MIKROBUS( mikrobus, MIKROBUS_RST );   \
    cfg.int_pin = MIKROBUS( mikrobus, MIKROBUS_INT )
 
 // accel30_map
 // accel30
 
typedef enum
{
    ACCEL30_DRV_SEL_SPI,      
    ACCEL30_DRV_SEL_I2C       
} accel30_drv_t;
 
typedef err_t ( *accel30_master_io_t )( struct accel30_s*, uint8_t, uint8_t*, uint8_t ); 
typedef struct accel30_s
{
    digital_out_t rst;               
    digital_in_t int_pin;            
    i2c_master_t i2c;                
    spi_master_t spi;                
    uint8_t      slave_address;      
    pin_name_t   chip_select;        
    accel30_drv_t drv_sel;           
    accel30_master_io_t write_f;     
    accel30_master_io_t read_f;      
    uint8_t range_cfg;               
    uint8_t resolution_cfg;          
} accel30_t;
 
typedef struct
{
    pin_name_t scl;             
    pin_name_t sda;             
    pin_name_t miso;            
    pin_name_t mosi;            
    pin_name_t sck;             
    pin_name_t cs;              
    pin_name_t rst;             
    pin_name_t int_pin;         
    uint32_t   i2c_speed;       
    uint8_t    i2c_address;     
    uint32_t                          spi_speed;    
    spi_master_mode_t                 spi_mode;     
    spi_master_chip_select_polarity_t cs_polarity;  
    accel30_drv_t drv_sel;      
} accel30_cfg_t;
 
typedef enum
{
    ACCEL30_OK = 0,
    ACCEL30_ERROR = -1
 
} accel30_return_value_t;
 
typedef enum
{
    ACCEL30_GAIN_DEFAULT = 0,
    ACCEL30_GAIN_4X,
    ACCEL30_GAIN_1X,
    ACCEL30_GAIN_NOT_USED
    
} accel30_gain_t;
 
typedef enum
{
    ACCEL30_MODE_SLEEP   = 0,
    ACCEL30_MODE_STANDBY = 1,
    ACCEL30_MODE_SNIFF   = 2,
    ACCEL30_MODE_CWAKE   = 5, 
    ACCEL30_MODE_TRIG    = 7
    
} accel30_op_mode_t;
 
typedef enum
{
    ACCEL30_RANGE_2G = 0,
    ACCEL30_RANGE_4G,
    ACCEL30_RANGE_8G,
    ACCEL30_RANGE_12G,
    ACCEL30_RANGE_16G,
    ACCEL30_RANGE_END
    
} accel30_range_t;
 
typedef enum
{
    ACCEL30_RESOLUTION_6BIT = 0, 
    ACCEL30_RESOLUTION_7BIT, 
    ACCEL30_RESOLUTION_8BIT, 
    ACCEL30_RESOLUTION_10BIT, 
    ACCEL30_RESOLUTION_12BIT, 
    ACCEL30_RESOLUTION_14BIT, 
    ACCEL30_RESOLUTION_END
    
} accel30_resolution_t;
 
typedef enum
{
    ACCEL30_CWAKE_DEFAULT_50Hz = 0,
    ACCEL30_CWAKE_0p4Hz,
    ACCEL30_CWAKE_0p8Hz,
    ACCEL30_CWAKE_2Hz,
    ACCEL30_CWAKE_6Hz,
    ACCEL30_CWAKE_14Hz,
    ACCEL30_CWAKE_28Hz,
    ACCEL30_CWAKE_54Hz,
    ACCEL30_CWAKE_100Hz,
    ACCEL30_CWAKE_210Hz,
    ACCEL30_CWAKE_400Hz,
    ACCEL30_CWAKE_600Hz,
    ACCEL30_CWAKE_RESER0,
    ACCEL30_CWAKE_RESER1,
    ACCEL30_CWAKE_RESER2,
    ACCEL30_CWAKE_750Hz,
    ACCEL30_CWAKE_END
    
} accel30_cwake_t;
 
typedef enum
{
    ACCEL30_SNIFF_SR_DEFAULT_6Hz = 0,
    ACCEL30_SNIFF_SR_0p4Hz,
    ACCEL30_SNIFF_SR_0p8Hz,
    ACCEL30_SNIFF_SR_2Hz,
    ACCEL30_SNIFF_SR_6Hz,
    ACCEL30_SNIFF_SR_13Hz,
    ACCEL30_SNIFF_SR_25Hz,
    ACCEL30_SNIFF_SR_50Hz,
    ACCEL30_SNIFF_SR_100Hz,
    ACCEL30_SNIFF_SR_200Hz,
    ACCEL30_SNIFF_SR_400Hz,
    ACCEL30_SNIFF_SR_END
    
} accel30_sniff_sr_t;
 
typedef enum
{
    ACCEL30_FIFO_MODE_NORMAL = 0,
    ACCEL30_FIFO_MODE_WATERMARK,
    ACCEL30_FIFO_MODE_END
    
} accel30_fifo_mode_t;
 
typedef enum 
{
    ACCEL30_LOW_POWER = 0,
    ACCEL30_RESERVED_1,
    ACCEL30_RESERVED_2,
    ACCEL30_ULOW_POWER,
    ACCEL30_PRE_POWER
    
} accel30_power_mode_t;
 
typedef struct 
{
    int16_t x;
    int16_t y;
    int16_t z;
 
} accel30_axis_t;
 
typedef struct 
{
    float x;
    float y;
    float z;
 
} accel30_avg_axis_t;
 
void accel30_cfg_setup ( accel30_cfg_t *cfg );
 
void accel30_drv_interface_selection ( accel30_cfg_t *cfg, accel30_drv_t drv_sel );
 
err_t accel30_init ( accel30_t *ctx, accel30_cfg_t *cfg );
 
err_t accel30_default_cfg ( accel30_t *ctx );
 
err_t accel30_generic_write ( accel30_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len );
 
err_t accel30_generic_read ( accel30_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len );
 
err_t accel30_set_mode ( accel30_t *ctx, accel30_op_mode_t mode );
 
err_t accel30_set_range_ctrl ( accel30_t *ctx, accel30_range_t range );
 
err_t accel30_soft_reset ( accel30_t *ctx );
 
err_t accel30_set_sniff_gain ( accel30_t *ctx, accel30_gain_t gain );
 
err_t accel30_set_wake_gain ( accel30_t *ctx, accel30_gain_t gain );
 
err_t accel30_set_resolution_ctrl ( accel30_t *ctx, accel30_resolution_t resolution );
 
err_t accel30_set_sample_rate ( accel30_t *ctx, accel30_cwake_t sample_rate );
 
err_t accel30_set_sniff_sample_rate ( accel30_t *ctx, accel30_sniff_sr_t sample_rate );
 
err_t accel30_set_pwr_mode (accel30_t *ctx, accel30_power_mode_t pwr_mode );
 
err_t accel30_get_axis ( accel30_t *ctx, accel30_axis_t *acc_axis );
 
err_t accel30_get_avg_axes ( accel30_t *ctx, accel30_avg_axis_t *acc_avg_axis );
 
uint8_t accel30_get_int_pin ( accel30_t *ctx );
 
#ifdef __cplusplus
}
#endif
#endif // ACCEL30_H
 
 // accel30
 
// ------------------------------------------------------------------------ END