Macros
#define	ACCEL5_CFG_1_ACC_RANGE_2g 0x00

#define	ACCEL5_CFG_1_ACC_RANGE_4g 0x40

#define	ACCEL5_CFG_1_ACC_RANGE_8g 0x80

#define	ACCEL5_CFG_1_ACC_RANGE_16g 0xC0

#define	ACCEL5_CFG_1_OSR_LOW_POWER 0x00

#define	ACCEL5_CFG_1_OSR_HIGH_POWER 0x30

#define	ACCEL5_CFG_1_ODR_12p5_5 0x00

#define	ACCEL5_CFG_1_ODR_12p5_4 0x01

#define	ACCEL5_CFG_1_ODR_12p5_3 0x02

#define	ACCEL5_CFG_1_ODR_12p5_2 0x03

#define	ACCEL5_CFG_1_ODR_12p5_1 0x04

#define	ACCEL5_CFG_1_ODR_12p5 0x05

#define	ACCEL5_CFG_1_ODR_25 0x06

#define	ACCEL5_CFG_1_ODR_50 0x07

#define	ACCEL5_CFG_1_ODR_100 0x08

#define	ACCEL5_CFG_1_ODR_200 0x09

#define	ACCEL5_CFG_1_ODR_400 0x0A

#define	ACCEL5_CFG_1_ODR_800 0x0B

#define	ACCEL5_CFG_1_ODR_800_1 0x0C

#define	ACCEL5_CFG_1_ODR_800_2 0x0D

#define	ACCEL5_CFG_1_ODR_800_3 0x0E

#define	ACCEL5_CFG_1_ODR_800_4 0x0F

Detailed Description

Macro Definition Documentation

◆ ACCEL5_CFG_1_ACC_RANGE_16g

#define ACCEL5_CFG_1_ACC_RANGE_16g 0xC0

◆ ACCEL5_CFG_1_ACC_RANGE_2g

#define ACCEL5_CFG_1_ACC_RANGE_2g 0x00

◆ ACCEL5_CFG_1_ACC_RANGE_4g

#define ACCEL5_CFG_1_ACC_RANGE_4g 0x40

◆ ACCEL5_CFG_1_ACC_RANGE_8g

#define ACCEL5_CFG_1_ACC_RANGE_8g 0x80

◆ ACCEL5_CFG_1_ODR_100

#define ACCEL5_CFG_1_ODR_100 0x08

◆ ACCEL5_CFG_1_ODR_12p5

#define ACCEL5_CFG_1_ODR_12p5 0x05

◆ ACCEL5_CFG_1_ODR_12p5_1

#define ACCEL5_CFG_1_ODR_12p5_1 0x04

◆ ACCEL5_CFG_1_ODR_12p5_2

#define ACCEL5_CFG_1_ODR_12p5_2 0x03

◆ ACCEL5_CFG_1_ODR_12p5_3

#define ACCEL5_CFG_1_ODR_12p5_3 0x02

◆ ACCEL5_CFG_1_ODR_12p5_4

#define ACCEL5_CFG_1_ODR_12p5_4 0x01

◆ ACCEL5_CFG_1_ODR_12p5_5

#define ACCEL5_CFG_1_ODR_12p5_5 0x00

◆ ACCEL5_CFG_1_ODR_200

#define ACCEL5_CFG_1_ODR_200 0x09

◆ ACCEL5_CFG_1_ODR_25

#define ACCEL5_CFG_1_ODR_25 0x06

◆ ACCEL5_CFG_1_ODR_400

#define ACCEL5_CFG_1_ODR_400 0x0A

◆ ACCEL5_CFG_1_ODR_50

#define ACCEL5_CFG_1_ODR_50 0x07

◆ ACCEL5_CFG_1_ODR_800

#define ACCEL5_CFG_1_ODR_800 0x0B

◆ ACCEL5_CFG_1_ODR_800_1

#define ACCEL5_CFG_1_ODR_800_1 0x0C

◆ ACCEL5_CFG_1_ODR_800_2

#define ACCEL5_CFG_1_ODR_800_2 0x0D

◆ ACCEL5_CFG_1_ODR_800_3

#define ACCEL5_CFG_1_ODR_800_3 0x0E

◆ ACCEL5_CFG_1_ODR_800_4

#define ACCEL5_CFG_1_ODR_800_4 0x0F

◆ ACCEL5_CFG_1_OSR_HIGH_POWER

#define ACCEL5_CFG_1_OSR_HIGH_POWER 0x30

◆ ACCEL5_CFG_1_OSR_LOW_POWER

#define ACCEL5_CFG_1_OSR_LOW_POWER 0x00

Macros