Settings for registers of ADAC 2 Click driver. More...

Macros
#define	ADAC2_PRODUCT_ID 0x2D
	ADAC 2 description setting.

#define	ADAC2_GEN_CNFG_CRC_EN_DISABLE 0x000000ul
	ADAC 2 GEN_CNFG register settings.

#define	ADAC2_GEN_CNFG_CRC_EN_ENABLE 0x800000ul

#define	ADAC2_GEN_CNFG_CRC_EN_MASK 0x800000ul

#define	ADAC2_GEN_CNFG_DACREF_SEL_INT 0x000000ul

#define	ADAC2_GEN_CNFG_DACREF_SEL_EXT 0x400000ul

#define	ADAC2_GEN_CNFG_DACREF_SEL_MASK 0x400000ul

#define	ADAC2_GEN_CNFG_ADCREF_SEL_INT 0x000000ul

#define	ADAC2_GEN_CNFG_ADCREF_SEL_EXT 0x200000ul

#define	ADAC2_GEN_CNFG_ADCREF_SEL_MASK 0x200000ul

#define	ADAC2_GEN_CNFG_LINE_CNFG_OPEN 0x000000ul

#define	ADAC2_GEN_CNFG_LINE_CNFG_CLOSED 0x100000ul

#define	ADAC2_GEN_CNFG_LINE_CNFG_MASK 0x100000ul

#define	ADAC2_GEN_CNFG_AO_CNFG_HIGH_Z 0x000000ul

#define	ADAC2_GEN_CNFG_AO_CNFG_25V 0x010000ul

#define	ADAC2_GEN_CNFG_AO_CNFG_12p5V 0x020000ul

#define	ADAC2_GEN_CNFG_AO_CNFG_25mA 0x060000ul

#define	ADAC2_GEN_CNFG_AO_CNFG_12p5mA 0x080000ul

#define	ADAC2_GEN_CNFG_AO_CNFG_MASK 0x0F0000ul

#define	ADAC2_GEN_CNFG_AI1_2_CNFG_BOTH_PD 0x000000ul

#define	ADAC2_GEN_CNFG_AI1_2_CNFG_AI1_SE 0x002000ul

#define	ADAC2_GEN_CNFG_AI1_2_CNFG_AI2_SE 0x004000ul

#define	ADAC2_GEN_CNFG_AI1_2_CNFG_BOTH_SE 0x006000ul

#define	ADAC2_GEN_CNFG_AI1_2_CNFG_DIFF 0x008000ul

#define	ADAC2_GEN_CNFG_AI1_2_CNFG_MASK 0x00E000ul

#define	ADAC2_GEN_CNFG_AI3_CNFG_PD 0x000000ul

#define	ADAC2_GEN_CNFG_AI3_CNFG_SE 0x001000ul

#define	ADAC2_GEN_CNFG_AI3_CNFG_MASK 0x001000ul

#define	ADAC2_GEN_CNFG_AI4_CNFG_PD 0x000000ul

#define	ADAC2_GEN_CNFG_AI4_CNFG_SE 0x000800ul

#define	ADAC2_GEN_CNFG_AI4_CNFG_MASK 0x000800ul

#define	ADAC2_GEN_CNFG_AI5_6_CNFG_PD 0x000000ul

#define	ADAC2_GEN_CNFG_AI5_6_CNFG_DIFF 0x000400ul

#define	ADAC2_GEN_CNFG_AI5_6_CNFG_MASK 0x000700ul

#define	ADAC2_GEN_CNFG_AI5_DF_GAIN_12p5V 0x000000ul

#define	ADAC2_GEN_CNFG_AI5_DF_GAIN_0p5V 0x000040ul

#define	ADAC2_GEN_CNFG_AI5_DF_GAIN_0p25V 0x000080ul

#define	ADAC2_GEN_CNFG_AI5_DF_GAIN_0p125V 0x0000C0ul

#define	ADAC2_GEN_CNFG_AI5_DF_GAIN_MASK 0x0000C0ul

#define	ADAC2_GEN_CNFG_OVC_CTRL_AUTO 0x000000ul

#define	ADAC2_GEN_CNFG_OVC_CTRL_HOST 0x000008ul

#define	ADAC2_GEN_CNFG_OVC_CTRL_MASK 0x000008ul

#define	ADAC2_ADC_DATA_RESOLUTION 0x7FFFFFul
	ADAC 2 voltage calculation values.

#define	ADAC2_DAC_DATA_RESOLUTION 0x03FFFFul

#define	ADAC2_DAC_MIN_VALUE -131072l

#define	ADAC2_DAC_MAX_VALUE 131071l

#define	ADAC2_FULL_SCALE_RANGE_25V 25.0f

#define	ADAC2_FULL_SCALE_RANGE_12p5V 12.5f

#define	ADAC2_FULL_SCALE_RANGE_2p5V 2.5f

#define	ADAC2_FULL_SCALE_RANGE_0p5V 0.5f

#define	ADAC2_FULL_SCALE_RANGE_0p25V 0.25f

#define	ADAC2_FULL_SCALE_RANGE_0p125V 0.125f

#define	ADAC2_START_CONVERSION 0x30
	ADAC 2 DCHNL_CMD register settings.

#define	ADAC2_STOP_CONVERSION 0x10

#define	ADAC2_DATA_RATE_5_SPS 0x00

#define	ADAC2_DATA_RATE_10_SPS 0x01

#define	ADAC2_DATA_RATE_15_SPS 0x02

#define	ADAC2_DATA_RATE_30_SPS 0x03

#define	ADAC2_DATA_RATE_50_SPS 0x04

#define	ADAC2_DATA_RATE_60_SPS 0x05

#define	ADAC2_DATA_RATE_225_SPS 0x06

#define	ADAC2_DATA_RATE_450_SPS 0x07

#define	ADAC2_DATA_RATE_900_SPS 0x08

#define	ADAC2_DATA_RATE_1800_SPS 0x09

#define	ADAC2_DATA_RATE_3600_SPS 0x0A

#define	ADAC2_DATA_RATE_7200_SPS 0x0B

#define	ADAC2_DATA_RATE_14400_SPS 0x0C

#define	ADAC2_DATA_RATE_28800_SPS 0x0D

#define	ADAC2_DATA_RATE_57600_SPS 0x0E

#define	ADAC2_DATA_RATE_115200_SPS 0x0F

#define	ADAC2_PD_STATE_STANDBY 0x00
	ADAC 2 DCHNL_CTRL1 register settings.

#define	ADAC2_PD_STATE_RESET 0x10

#define	ADAC2_CONV_MODE_CONTINUOUS 0x00

#define	ADAC2_CONV_MODE_SINGLE_CYCLE 0x02

#define	ADAC2_CONV_MODE_CONT_SINGLE_CYCLE 0x03

#define	ADAC2_CH_NONE 0x00
	ADAC 2 channel selection values.

#define	ADAC2_CH_AI1_SINGLE_ENDED 0x01

#define	ADAC2_CH_AI2_SINGLE_ENDED 0x02

#define	ADAC2_CH_AI1_AI2_DIFFERENTIAL 0x03

#define	ADAC2_CH_AI3_SINGLE_ENDED 0x04

#define	ADAC2_CH_AI4_SINGLE_ENDED 0x05

#define	ADAC2_CH_AI3_AI4_DIFFERENTIAL 0x06

#define	ADAC2_CH_AI5_AI6_DIFFERENTIAL_25V 0x09

#define	ADAC2_CH_AI5_AI6_DIFFERENTIAL_2p5V 0x0C

#define	ADAC2_CH_AUX1_SINGLE_ENDED 0x0D

#define	ADAC2_CH_AUX2_SINGLE_ENDED 0x0E

#define	ADAC2_CH_AUX1_AUX2_DIFFERENTIAL 0x0F

#define	ADAC2_CH_MASK 0x000F00ul

#define	ADAC2_GPIO_0_MASK 0x01
	ADAC 2 gpio selection values.

#define	ADAC2_GPIO_1_MASK 0x02

#define	ADAC2_GPIO_2_MASK 0x04

#define	ADAC2_GPIO_3_MASK 0x08

#define	ADAC2_GPIO_4_MASK 0x10

#define	ADAC2_GPIO_5_MASK 0x20

#define	ADAC2_GPIO_ALL_MASK 0x3F

#define	ADAC2_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE
	Data sample selection.

#define	ADAC2_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE

Detailed Description

Settings for registers of ADAC 2 Click driver.

Macro Definition Documentation

◆ ADAC2_ADC_DATA_RESOLUTION

#define ADAC2_ADC_DATA_RESOLUTION 0x7FFFFFul

ADAC 2 voltage calculation values.

Specified voltage calculation values of ADAC 2 Click driver.

◆ ADAC2_CH_AI1_AI2_DIFFERENTIAL

#define ADAC2_CH_AI1_AI2_DIFFERENTIAL 0x03

◆ ADAC2_CH_AI1_SINGLE_ENDED

#define ADAC2_CH_AI1_SINGLE_ENDED 0x01

◆ ADAC2_CH_AI2_SINGLE_ENDED

#define ADAC2_CH_AI2_SINGLE_ENDED 0x02

◆ ADAC2_CH_AI3_AI4_DIFFERENTIAL

#define ADAC2_CH_AI3_AI4_DIFFERENTIAL 0x06

◆ ADAC2_CH_AI3_SINGLE_ENDED

#define ADAC2_CH_AI3_SINGLE_ENDED 0x04

◆ ADAC2_CH_AI4_SINGLE_ENDED

#define ADAC2_CH_AI4_SINGLE_ENDED 0x05

◆ ADAC2_CH_AI5_AI6_DIFFERENTIAL_25V

#define ADAC2_CH_AI5_AI6_DIFFERENTIAL_25V 0x09

◆ ADAC2_CH_AI5_AI6_DIFFERENTIAL_2p5V

#define ADAC2_CH_AI5_AI6_DIFFERENTIAL_2p5V 0x0C

◆ ADAC2_CH_AUX1_AUX2_DIFFERENTIAL

#define ADAC2_CH_AUX1_AUX2_DIFFERENTIAL 0x0F

◆ ADAC2_CH_AUX1_SINGLE_ENDED

#define ADAC2_CH_AUX1_SINGLE_ENDED 0x0D

◆ ADAC2_CH_AUX2_SINGLE_ENDED

#define ADAC2_CH_AUX2_SINGLE_ENDED 0x0E

◆ ADAC2_CH_MASK

#define ADAC2_CH_MASK 0x000F00ul

◆ ADAC2_CH_NONE

#define ADAC2_CH_NONE 0x00

ADAC 2 channel selection values.

Specified channel selection values of ADAC 2 Click driver.

◆ ADAC2_CONV_MODE_CONT_SINGLE_CYCLE

#define ADAC2_CONV_MODE_CONT_SINGLE_CYCLE 0x03

◆ ADAC2_CONV_MODE_CONTINUOUS

#define ADAC2_CONV_MODE_CONTINUOUS 0x00

◆ ADAC2_CONV_MODE_SINGLE_CYCLE

#define ADAC2_CONV_MODE_SINGLE_CYCLE 0x02

◆ ADAC2_DAC_DATA_RESOLUTION

#define ADAC2_DAC_DATA_RESOLUTION 0x03FFFFul

◆ ADAC2_DAC_MAX_VALUE

#define ADAC2_DAC_MAX_VALUE 131071l

◆ ADAC2_DAC_MIN_VALUE

#define ADAC2_DAC_MIN_VALUE -131072l

◆ ADAC2_DATA_RATE_10_SPS

#define ADAC2_DATA_RATE_10_SPS 0x01

◆ ADAC2_DATA_RATE_115200_SPS

#define ADAC2_DATA_RATE_115200_SPS 0x0F

◆ ADAC2_DATA_RATE_14400_SPS

#define ADAC2_DATA_RATE_14400_SPS 0x0C

◆ ADAC2_DATA_RATE_15_SPS

#define ADAC2_DATA_RATE_15_SPS 0x02

◆ ADAC2_DATA_RATE_1800_SPS

#define ADAC2_DATA_RATE_1800_SPS 0x09

◆ ADAC2_DATA_RATE_225_SPS

#define ADAC2_DATA_RATE_225_SPS 0x06

◆ ADAC2_DATA_RATE_28800_SPS

#define ADAC2_DATA_RATE_28800_SPS 0x0D

◆ ADAC2_DATA_RATE_30_SPS

#define ADAC2_DATA_RATE_30_SPS 0x03

◆ ADAC2_DATA_RATE_3600_SPS

#define ADAC2_DATA_RATE_3600_SPS 0x0A

◆ ADAC2_DATA_RATE_450_SPS

#define ADAC2_DATA_RATE_450_SPS 0x07

◆ ADAC2_DATA_RATE_50_SPS

#define ADAC2_DATA_RATE_50_SPS 0x04

◆ ADAC2_DATA_RATE_57600_SPS

#define ADAC2_DATA_RATE_57600_SPS 0x0E

◆ ADAC2_DATA_RATE_5_SPS

#define ADAC2_DATA_RATE_5_SPS 0x00

◆ ADAC2_DATA_RATE_60_SPS

#define ADAC2_DATA_RATE_60_SPS 0x05

◆ ADAC2_DATA_RATE_7200_SPS

#define ADAC2_DATA_RATE_7200_SPS 0x0B

◆ ADAC2_DATA_RATE_900_SPS

#define ADAC2_DATA_RATE_900_SPS 0x08

◆ ADAC2_FULL_SCALE_RANGE_0p125V

#define ADAC2_FULL_SCALE_RANGE_0p125V 0.125f

◆ ADAC2_FULL_SCALE_RANGE_0p25V

#define ADAC2_FULL_SCALE_RANGE_0p25V 0.25f

◆ ADAC2_FULL_SCALE_RANGE_0p5V

#define ADAC2_FULL_SCALE_RANGE_0p5V 0.5f

◆ ADAC2_FULL_SCALE_RANGE_12p5V

#define ADAC2_FULL_SCALE_RANGE_12p5V 12.5f

◆ ADAC2_FULL_SCALE_RANGE_25V

#define ADAC2_FULL_SCALE_RANGE_25V 25.0f

◆ ADAC2_FULL_SCALE_RANGE_2p5V

#define ADAC2_FULL_SCALE_RANGE_2p5V 2.5f

◆ ADAC2_GEN_CNFG_ADCREF_SEL_EXT

#define ADAC2_GEN_CNFG_ADCREF_SEL_EXT 0x200000ul

◆ ADAC2_GEN_CNFG_ADCREF_SEL_INT

#define ADAC2_GEN_CNFG_ADCREF_SEL_INT 0x000000ul

◆ ADAC2_GEN_CNFG_ADCREF_SEL_MASK

#define ADAC2_GEN_CNFG_ADCREF_SEL_MASK 0x200000ul

◆ ADAC2_GEN_CNFG_AI1_2_CNFG_AI1_SE

#define ADAC2_GEN_CNFG_AI1_2_CNFG_AI1_SE 0x002000ul

◆ ADAC2_GEN_CNFG_AI1_2_CNFG_AI2_SE

#define ADAC2_GEN_CNFG_AI1_2_CNFG_AI2_SE 0x004000ul

◆ ADAC2_GEN_CNFG_AI1_2_CNFG_BOTH_PD

#define ADAC2_GEN_CNFG_AI1_2_CNFG_BOTH_PD 0x000000ul

◆ ADAC2_GEN_CNFG_AI1_2_CNFG_BOTH_SE

#define ADAC2_GEN_CNFG_AI1_2_CNFG_BOTH_SE 0x006000ul

◆ ADAC2_GEN_CNFG_AI1_2_CNFG_DIFF

#define ADAC2_GEN_CNFG_AI1_2_CNFG_DIFF 0x008000ul

◆ ADAC2_GEN_CNFG_AI1_2_CNFG_MASK

#define ADAC2_GEN_CNFG_AI1_2_CNFG_MASK 0x00E000ul

◆ ADAC2_GEN_CNFG_AI3_CNFG_MASK

#define ADAC2_GEN_CNFG_AI3_CNFG_MASK 0x001000ul

◆ ADAC2_GEN_CNFG_AI3_CNFG_PD

#define ADAC2_GEN_CNFG_AI3_CNFG_PD 0x000000ul

◆ ADAC2_GEN_CNFG_AI3_CNFG_SE

#define ADAC2_GEN_CNFG_AI3_CNFG_SE 0x001000ul

◆ ADAC2_GEN_CNFG_AI4_CNFG_MASK

#define ADAC2_GEN_CNFG_AI4_CNFG_MASK 0x000800ul

◆ ADAC2_GEN_CNFG_AI4_CNFG_PD

#define ADAC2_GEN_CNFG_AI4_CNFG_PD 0x000000ul

◆ ADAC2_GEN_CNFG_AI4_CNFG_SE

#define ADAC2_GEN_CNFG_AI4_CNFG_SE 0x000800ul

◆ ADAC2_GEN_CNFG_AI5_6_CNFG_DIFF

#define ADAC2_GEN_CNFG_AI5_6_CNFG_DIFF 0x000400ul

◆ ADAC2_GEN_CNFG_AI5_6_CNFG_MASK

#define ADAC2_GEN_CNFG_AI5_6_CNFG_MASK 0x000700ul

◆ ADAC2_GEN_CNFG_AI5_6_CNFG_PD

#define ADAC2_GEN_CNFG_AI5_6_CNFG_PD 0x000000ul

◆ ADAC2_GEN_CNFG_AI5_DF_GAIN_0p125V

#define ADAC2_GEN_CNFG_AI5_DF_GAIN_0p125V 0x0000C0ul

◆ ADAC2_GEN_CNFG_AI5_DF_GAIN_0p25V

#define ADAC2_GEN_CNFG_AI5_DF_GAIN_0p25V 0x000080ul

◆ ADAC2_GEN_CNFG_AI5_DF_GAIN_0p5V

#define ADAC2_GEN_CNFG_AI5_DF_GAIN_0p5V 0x000040ul

◆ ADAC2_GEN_CNFG_AI5_DF_GAIN_12p5V

#define ADAC2_GEN_CNFG_AI5_DF_GAIN_12p5V 0x000000ul

◆ ADAC2_GEN_CNFG_AI5_DF_GAIN_MASK

#define ADAC2_GEN_CNFG_AI5_DF_GAIN_MASK 0x0000C0ul

◆ ADAC2_GEN_CNFG_AO_CNFG_12p5mA

#define ADAC2_GEN_CNFG_AO_CNFG_12p5mA 0x080000ul

◆ ADAC2_GEN_CNFG_AO_CNFG_12p5V

#define ADAC2_GEN_CNFG_AO_CNFG_12p5V 0x020000ul

◆ ADAC2_GEN_CNFG_AO_CNFG_25mA

#define ADAC2_GEN_CNFG_AO_CNFG_25mA 0x060000ul

◆ ADAC2_GEN_CNFG_AO_CNFG_25V

#define ADAC2_GEN_CNFG_AO_CNFG_25V 0x010000ul

◆ ADAC2_GEN_CNFG_AO_CNFG_HIGH_Z

#define ADAC2_GEN_CNFG_AO_CNFG_HIGH_Z 0x000000ul

◆ ADAC2_GEN_CNFG_AO_CNFG_MASK

#define ADAC2_GEN_CNFG_AO_CNFG_MASK 0x0F0000ul

◆ ADAC2_GEN_CNFG_CRC_EN_DISABLE

#define ADAC2_GEN_CNFG_CRC_EN_DISABLE 0x000000ul

ADAC 2 GEN_CNFG register settings.

Specified GEN_CNFG register settings of ADAC 2 Click driver.

◆ ADAC2_GEN_CNFG_CRC_EN_ENABLE

#define ADAC2_GEN_CNFG_CRC_EN_ENABLE 0x800000ul

◆ ADAC2_GEN_CNFG_CRC_EN_MASK

#define ADAC2_GEN_CNFG_CRC_EN_MASK 0x800000ul

◆ ADAC2_GEN_CNFG_DACREF_SEL_EXT

#define ADAC2_GEN_CNFG_DACREF_SEL_EXT 0x400000ul

◆ ADAC2_GEN_CNFG_DACREF_SEL_INT

#define ADAC2_GEN_CNFG_DACREF_SEL_INT 0x000000ul

◆ ADAC2_GEN_CNFG_DACREF_SEL_MASK

#define ADAC2_GEN_CNFG_DACREF_SEL_MASK 0x400000ul

◆ ADAC2_GEN_CNFG_LINE_CNFG_CLOSED

#define ADAC2_GEN_CNFG_LINE_CNFG_CLOSED 0x100000ul

◆ ADAC2_GEN_CNFG_LINE_CNFG_MASK

#define ADAC2_GEN_CNFG_LINE_CNFG_MASK 0x100000ul

◆ ADAC2_GEN_CNFG_LINE_CNFG_OPEN

#define ADAC2_GEN_CNFG_LINE_CNFG_OPEN 0x000000ul

◆ ADAC2_GEN_CNFG_OVC_CTRL_AUTO

#define ADAC2_GEN_CNFG_OVC_CTRL_AUTO 0x000000ul

◆ ADAC2_GEN_CNFG_OVC_CTRL_HOST

#define ADAC2_GEN_CNFG_OVC_CTRL_HOST 0x000008ul

◆ ADAC2_GEN_CNFG_OVC_CTRL_MASK

#define ADAC2_GEN_CNFG_OVC_CTRL_MASK 0x000008ul

◆ ADAC2_GPIO_0_MASK

#define ADAC2_GPIO_0_MASK 0x01

ADAC 2 gpio selection values.

Specified gpio selection values of ADAC 2 Click driver.

◆ ADAC2_GPIO_1_MASK

#define ADAC2_GPIO_1_MASK 0x02

◆ ADAC2_GPIO_2_MASK

#define ADAC2_GPIO_2_MASK 0x04

◆ ADAC2_GPIO_3_MASK

#define ADAC2_GPIO_3_MASK 0x08

◆ ADAC2_GPIO_4_MASK

#define ADAC2_GPIO_4_MASK 0x10

◆ ADAC2_GPIO_5_MASK

#define ADAC2_GPIO_5_MASK 0x20

◆ ADAC2_GPIO_ALL_MASK

#define ADAC2_GPIO_ALL_MASK 0x3F

◆ ADAC2_PD_STATE_RESET

#define ADAC2_PD_STATE_RESET 0x10

◆ ADAC2_PD_STATE_STANDBY

#define ADAC2_PD_STATE_STANDBY 0x00

ADAC 2 DCHNL_CTRL1 register settings.

Specified DCHNL_CTRL1 register settings of ADAC 2 Click driver.

◆ ADAC2_PRODUCT_ID

#define ADAC2_PRODUCT_ID 0x2D

ADAC 2 description setting.

Specified setting for description of ADAC 2 Click driver.

◆ ADAC2_SET_DATA_SAMPLE_EDGE

#define ADAC2_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE

Data sample selection.

This macro sets data samples for SPI modules.

Note: Available only on Microchip PIC family devices. This macro will set data sampling for all SPI modules on MCU. Can be overwritten with adac2_init which will set SET_SPI_DATA_SAMPLE_MIDDLE by default on the mapped mikrobus.

◆ ADAC2_SET_DATA_SAMPLE_MIDDLE

#define ADAC2_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE

◆ ADAC2_START_CONVERSION

#define ADAC2_START_CONVERSION 0x30

ADAC 2 DCHNL_CMD register settings.

Specified DCHNL_CMD register settings of ADAC 2 Click driver.

◆ ADAC2_STOP_CONVERSION

#define ADAC2_STOP_CONVERSION 0x10

Macros