Settings for registers of ADC 20 Click driver. More...

Macros
#define	ADC20_DATA_CFG_FIX_PAT 0x80
	ADC 20 DATA_CFG register setting.

#define	ADC20_DATA_CFG_APPEND_CHANNEL_ID 0x10

#define	ADC20_DATA_CFG_SPI_MODE_0 0x00

#define	ADC20_DATA_CFG_SPI_MODE_1 0x01

#define	ADC20_DATA_CFG_SPI_MODE_2 0x02

#define	ADC20_DATA_CFG_SPI_MODE_3 0x03

#define	ADC20_DATA_CFG_SPI_MODE_MASK 0x03

#define	ADC20_FIXED_CODE 0xA5A0
	ADC 20 Fixed code value.

#define	ADC20_CHANNEL_0 0x01
	ADC 20 channel mask.

#define	ADC20_CHANNEL_1 0x02

#define	ADC20_CHANNEL_2 0x04

#define	ADC20_CHANNEL_3 0x08

#define	ADC20_CHANNEL_4 0x10

#define	ADC20_CHANNEL_5 0x20

#define	ADC20_CHANNEL_6 0x40

#define	ADC20_CHANNEL_7 0x80

#define	ADC20_CHANNEL_NONE 0x00

#define	ADC20_CHANNEL_MASK 0xFF

#define	ADC20_CHANNEL_ID_0 0
	ADC 20 channel ID values.

#define	ADC20_CHANNEL_ID_1 1

#define	ADC20_CHANNEL_ID_2 2

#define	ADC20_CHANNEL_ID_3 3

#define	ADC20_CHANNEL_ID_4 4

#define	ADC20_CHANNEL_ID_5 5

#define	ADC20_CHANNEL_ID_6 6

#define	ADC20_CHANNEL_ID_7 7

#define	ADC20_CHANNEL_ID_MASK 0x0F

#define	ADC20_PIN_CFG_ANALOG 0
	ADC 20 PIN_CFG register settings.

#define	ADC20_PIN_CFG_GPIO 1

#define	ADC20_GPIO_CFG_DIG_INPUT 0
	ADC 20 GPIO_CFG register settings.

#define	ADC20_GPIO_CFG_DIG_OUTPUT 1

#define	ADC20_GPO_DRIVE_CFG_OPEN_DRAIN 0
	ADC 20 GPO_DRIVE_CFG register settings.

#define	ADC20_GPO_DRIVE_CFG_PUSH_PULL 1

#define	ADC20_GPIO_VALUE_LOW 0
	ADC 20 GPIO value settings.

#define	ADC20_GPIO_VALUE_HIGH 1

#define	ADC20_OSR_NO_AVERAGING 0x00
	ADC 20 OSR_CFG register setting.

#define	ADC20_OSR_2_SAMPLES 0x01

#define	ADC20_OSR_4_SAMPLES 0x02

#define	ADC20_OSR_8_SAMPLES 0x03

#define	ADC20_OSR_16_SAMPLES 0x04

#define	ADC20_OSR_32_SAMPLES 0x05

#define	ADC20_OSR_64_SAMPLES 0x06

#define	ADC20_OSR_128_SAMPLES 0x07

#define	ADC20_OSR_MASK 0x07

#define	ADC20_SEQ_STOP 0x00
	ADC 20 SEQUENCE_CFG register setting.

#define	ADC20_SEQ_START 0x10

#define	ADC20_SEQ_MODE_MANUAL 0x00

#define	ADC20_SEQ_MODE_AUTO 0x01

#define	ADC20_SEQ_MODE_OTF 0x02

#define	ADC20_SEQ_MODE_MASK 0x03

#define	ADC20_ADC_OFFSET 4
	ADC 20 ADC setting.

#define	ADC20_RES_12BIT 0x0FFF

#define	ADC20_VREF_3V3 3.3f

#define	ADC20_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE
	Data sample selection.

#define	ADC20_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE

Detailed Description

Settings for registers of ADC 20 Click driver.

Macro Definition Documentation

◆ ADC20_ADC_OFFSET

#define ADC20_ADC_OFFSET 4

ADC 20 ADC setting.

Specified setting for ADC of ADC 20 Click driver.

◆ ADC20_CHANNEL_0

#define ADC20_CHANNEL_0 0x01

ADC 20 channel mask.

Specified channel mask of ADC 20 Click driver.

◆ ADC20_CHANNEL_1

#define ADC20_CHANNEL_1 0x02

◆ ADC20_CHANNEL_2

#define ADC20_CHANNEL_2 0x04

◆ ADC20_CHANNEL_3

#define ADC20_CHANNEL_3 0x08

◆ ADC20_CHANNEL_4

#define ADC20_CHANNEL_4 0x10

◆ ADC20_CHANNEL_5

#define ADC20_CHANNEL_5 0x20

◆ ADC20_CHANNEL_6

#define ADC20_CHANNEL_6 0x40

◆ ADC20_CHANNEL_7

#define ADC20_CHANNEL_7 0x80

◆ ADC20_CHANNEL_ID_0

#define ADC20_CHANNEL_ID_0 0

ADC 20 channel ID values.

Specified channel ID values of ADC 20 Click driver.

◆ ADC20_CHANNEL_ID_1

#define ADC20_CHANNEL_ID_1 1

◆ ADC20_CHANNEL_ID_2

#define ADC20_CHANNEL_ID_2 2

◆ ADC20_CHANNEL_ID_3

#define ADC20_CHANNEL_ID_3 3

◆ ADC20_CHANNEL_ID_4

#define ADC20_CHANNEL_ID_4 4

◆ ADC20_CHANNEL_ID_5

#define ADC20_CHANNEL_ID_5 5

◆ ADC20_CHANNEL_ID_6

#define ADC20_CHANNEL_ID_6 6

◆ ADC20_CHANNEL_ID_7

#define ADC20_CHANNEL_ID_7 7

◆ ADC20_CHANNEL_ID_MASK

#define ADC20_CHANNEL_ID_MASK 0x0F

◆ ADC20_CHANNEL_MASK

#define ADC20_CHANNEL_MASK 0xFF

◆ ADC20_CHANNEL_NONE

#define ADC20_CHANNEL_NONE 0x00

◆ ADC20_DATA_CFG_APPEND_CHANNEL_ID

#define ADC20_DATA_CFG_APPEND_CHANNEL_ID 0x10

◆ ADC20_DATA_CFG_FIX_PAT

#define ADC20_DATA_CFG_FIX_PAT 0x80

ADC 20 DATA_CFG register setting.

Specified setting for DATA_CFG register of ADC 20 Click driver.

◆ ADC20_DATA_CFG_SPI_MODE_0

#define ADC20_DATA_CFG_SPI_MODE_0 0x00

◆ ADC20_DATA_CFG_SPI_MODE_1

#define ADC20_DATA_CFG_SPI_MODE_1 0x01

◆ ADC20_DATA_CFG_SPI_MODE_2

#define ADC20_DATA_CFG_SPI_MODE_2 0x02

◆ ADC20_DATA_CFG_SPI_MODE_3

#define ADC20_DATA_CFG_SPI_MODE_3 0x03

◆ ADC20_DATA_CFG_SPI_MODE_MASK

#define ADC20_DATA_CFG_SPI_MODE_MASK 0x03

◆ ADC20_FIXED_CODE

#define ADC20_FIXED_CODE 0xA5A0

ADC 20 Fixed code value.

Specified Fixed code value of ADC 20 Click driver.

◆ ADC20_GPIO_CFG_DIG_INPUT

#define ADC20_GPIO_CFG_DIG_INPUT 0

ADC 20 GPIO_CFG register settings.

Specified settings for GPIO_CFG register of ADC 20 Click driver.

◆ ADC20_GPIO_CFG_DIG_OUTPUT

#define ADC20_GPIO_CFG_DIG_OUTPUT 1

◆ ADC20_GPIO_VALUE_HIGH

#define ADC20_GPIO_VALUE_HIGH 1

◆ ADC20_GPIO_VALUE_LOW

#define ADC20_GPIO_VALUE_LOW 0

ADC 20 GPIO value settings.

Specified settings for GPIO value of ADC 20 Click driver.

◆ ADC20_GPO_DRIVE_CFG_OPEN_DRAIN

#define ADC20_GPO_DRIVE_CFG_OPEN_DRAIN 0

ADC 20 GPO_DRIVE_CFG register settings.

Specified settings for GPO_DRIVE_CFG register of ADC 20 Click driver.

◆ ADC20_GPO_DRIVE_CFG_PUSH_PULL

#define ADC20_GPO_DRIVE_CFG_PUSH_PULL 1

◆ ADC20_OSR_128_SAMPLES

#define ADC20_OSR_128_SAMPLES 0x07

◆ ADC20_OSR_16_SAMPLES

#define ADC20_OSR_16_SAMPLES 0x04

◆ ADC20_OSR_2_SAMPLES

#define ADC20_OSR_2_SAMPLES 0x01

◆ ADC20_OSR_32_SAMPLES

#define ADC20_OSR_32_SAMPLES 0x05

◆ ADC20_OSR_4_SAMPLES

#define ADC20_OSR_4_SAMPLES 0x02

◆ ADC20_OSR_64_SAMPLES

#define ADC20_OSR_64_SAMPLES 0x06

◆ ADC20_OSR_8_SAMPLES

#define ADC20_OSR_8_SAMPLES 0x03

◆ ADC20_OSR_MASK

#define ADC20_OSR_MASK 0x07

◆ ADC20_OSR_NO_AVERAGING

#define ADC20_OSR_NO_AVERAGING 0x00

ADC 20 OSR_CFG register setting.

Specified setting for OSR_CFG register of ADC 20 Click driver.

◆ ADC20_PIN_CFG_ANALOG

#define ADC20_PIN_CFG_ANALOG 0

ADC 20 PIN_CFG register settings.

Specified settings for PIN_CFG register of ADC 20 Click driver.

◆ ADC20_PIN_CFG_GPIO

#define ADC20_PIN_CFG_GPIO 1

◆ ADC20_RES_12BIT

#define ADC20_RES_12BIT 0x0FFF

◆ ADC20_SEQ_MODE_AUTO

#define ADC20_SEQ_MODE_AUTO 0x01

◆ ADC20_SEQ_MODE_MANUAL

#define ADC20_SEQ_MODE_MANUAL 0x00

◆ ADC20_SEQ_MODE_MASK

#define ADC20_SEQ_MODE_MASK 0x03

◆ ADC20_SEQ_MODE_OTF

#define ADC20_SEQ_MODE_OTF 0x02

◆ ADC20_SEQ_START

#define ADC20_SEQ_START 0x10

◆ ADC20_SEQ_STOP

#define ADC20_SEQ_STOP 0x00

ADC 20 SEQUENCE_CFG register setting.

Specified setting for SEQUENCE_CFG register of ADC 20 Click driver.

◆ ADC20_SET_DATA_SAMPLE_EDGE

#define ADC20_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE

Data sample selection.

This macro sets data samples for SPI modules.

Note: Available only on Microchip PIC family devices. This macro will set data sampling for all SPI modules on MCU. Can be overwritten with adc20_init which will set SET_SPI_DATA_SAMPLE_MIDDLE by default on the mapped mikrobus.

◆ ADC20_SET_DATA_SAMPLE_MIDDLE

#define ADC20_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE

◆ ADC20_VREF_3V3

#define ADC20_VREF_3V3 3.3f

Macros