Macros
#define	ADC9_CFG_0_VREF_SEL_0 0x00

#define	ADC9_CFG_0_VREF_SEL_1 0x40

#define	ADC9_CFG_0_VREF_SEL_2 0x80

#define	ADC9_CFG_0_VREF_SEL_3 0xC0

#define	ADC9_CFG_0_CLK_SEL_0 0x00

#define	ADC9_CFG_0_CLK_SEL_1 0x10

#define	ADC9_CFG_0_CLK_SEL_2 0x20

#define	ADC9_CFG_0_CLK_SEL_3 0x30

#define	ADC9_CFG_0_CS_SEL_0 0x00

#define	ADC9_CFG_0_CS_SEL_1 0x04

#define	ADC9_CFG_0_CS_SEL_2 0x08

#define	ADC9_CFG_0_CS_SEL_3 0x0C

#define	ADC9_CFG_0_MODE_SHD_DEF 0x00

#define	ADC9_CFG_0_MODE_SHD 0x01

#define	ADC9_CFG_0_MODE_STANDBY 0x02

#define	ADC9_CFG_0_MODE_CONV 0x03

Detailed Description

Macro Definition Documentation

◆ ADC9_CFG_0_CLK_SEL_0

#define ADC9_CFG_0_CLK_SEL_0 0x00

◆ ADC9_CFG_0_CLK_SEL_1

#define ADC9_CFG_0_CLK_SEL_1 0x10

◆ ADC9_CFG_0_CLK_SEL_2

#define ADC9_CFG_0_CLK_SEL_2 0x20

◆ ADC9_CFG_0_CLK_SEL_3

#define ADC9_CFG_0_CLK_SEL_3 0x30

◆ ADC9_CFG_0_CS_SEL_0

#define ADC9_CFG_0_CS_SEL_0 0x00

◆ ADC9_CFG_0_CS_SEL_1

#define ADC9_CFG_0_CS_SEL_1 0x04

◆ ADC9_CFG_0_CS_SEL_2

#define ADC9_CFG_0_CS_SEL_2 0x08

◆ ADC9_CFG_0_CS_SEL_3

#define ADC9_CFG_0_CS_SEL_3 0x0C

◆ ADC9_CFG_0_MODE_CONV

#define ADC9_CFG_0_MODE_CONV 0x03

◆ ADC9_CFG_0_MODE_SHD

#define ADC9_CFG_0_MODE_SHD 0x01

◆ ADC9_CFG_0_MODE_SHD_DEF

#define ADC9_CFG_0_MODE_SHD_DEF 0x00

◆ ADC9_CFG_0_MODE_STANDBY

#define ADC9_CFG_0_MODE_STANDBY 0x02

◆ ADC9_CFG_0_VREF_SEL_0

#define ADC9_CFG_0_VREF_SEL_0 0x00

◆ ADC9_CFG_0_VREF_SEL_1

#define ADC9_CFG_0_VREF_SEL_1 0x40

◆ ADC9_CFG_0_VREF_SEL_2

#define ADC9_CFG_0_VREF_SEL_2 0x80

◆ ADC9_CFG_0_VREF_SEL_3

#define ADC9_CFG_0_VREF_SEL_3 0xC0

Macros