|
#define | ADSWIO2_MAP_MIKROBUS(cfg, mikrobus) |
|
#define | adswio2_obj_t const uint8_t* |
|
#define | adswio2_err_t uint8_t |
|
#define | ADSWIO2_RETVAL uint8_t |
|
#define | ADSWIO2_OK 0x00 |
|
#define | ADSWIO2_INIT_ERROR 0xFF |
|
#define | ADSWIO2_FRAME_LENGTH 4 |
|
#define | ADSWIO2_MASK_RD_FRAME_RESERVED_BIT 0x80 |
|
#define | ADSWIO2_MASK_RD_FRAME_REG_ADDR 0x7F |
|
#define | ADSWIO2_MASK_RD_FRAME_STATUS 0x7F |
|
#define | ADSWIO2_RD_RET_INFO 0x1 |
|
#define | ADSWIO2_OFFSET_REG_CONV_RES 0x25 |
|
#define | ADSWIO2_OFFSET_REG_DIAG_RES 0x29 |
|
#define | DUMMY 0 |
|
#define | ADSWIO2_NULL 0 |
|
#define | ADSWIO2_RD_AUTO_EN 0x2 |
|
#define | ADSWIO2_RD_AUTO_DIS 0x0 |
|
#define | ADSWIO2_MASK_CONV_EN 0xF |
|
#define | ADSWIO2_OFFSET_CONV_EN_CH 0 |
|
#define | ADSWIO2_OFFSET_CONV_EN_DIAG 4 |
|
#define | ADSWIO2_MASK_DIAG_ASSIGN 0xF |
|
#define | ADSWIO2_OFFSET_ASSIGN_DIAG0 0 |
|
#define | ADSWIO2_OFFSET_ASSIGN_DIAG1 4 |
|
#define | ADSWIO2_OFFSET_ASSIGN_DIAG2 8 |
|
#define | ADSWIO2_OFFSET_ASSIGN_DIAG3 12 |
|
#define | ADSWIO2_MASK_CONV_MODE 0x300 |
|
#define | ADSWIO2_OFFSET_CONV_MODE 8 |
|
#define | ADSWIO2_MASK_DAC_CODE 0x1FFF |
|
#define | ADSWIO2_MASK_ALERT 0x7FFF |
|
#define | ADSWIO2_MASK_DIN_THRESH_COMP 0x3E |
|
#define | ADSWIO2_MASK_STATUS_ALRT_CAL_MEM_ERR 0x4000 |
|
#define | ADSWIO2_MASK_STATUS_ALRT_SPI_CRC_ERR 0x2000 |
|
#define | ADSWIO2_MASK_STATUS_ALRT_RST 0x8000 |
|
#define | ADSWIO2_MASK_STATUS_ALRT_SPI_SCLK_CNT_ERR 0x1000 |
|
#define | ADSWIO2_MASK_STATUS_ALRT_ADC_SAT_ERR 0x800 |
|
#define | ADSWIO2_MASK_STATUS_ALRT_ADC_CONV_ERR 0x400 |
|
#define | ADSWIO2_MASK_STATUS_ALRT_ALDO1V8_ERR 0x200 |
|
#define | ADSWIO2_MASK_STATUS_ALRT_DVCC_ERR 0x100 |
|
#define | ADSWIO2_MASK_STATUS_ALRT_AVDD_ERR 0x80 |
|
#define | ADSWIO2_MASK_STATUS_ALRT_ALDO5V_ERR 0x40 |
|
#define | ADSWIO2_MASK_STATUS_ALRT_CHARGE_PUMP_ERR 0x20 |
|
#define | ADSWIO2_MASK_STATUS_ALRT_HI_TEMP_ERR 0x10 |
|
#define | ADSWIO2_MASK_STATUS_ALRT_VI_ERR_D 0x8 |
|
#define | ADSWIO2_MASK_STATUS_ALRT_VI_ERR_C 0x4 |
|
#define | ADSWIO2_MASK_STATUS_ALRT_VI_ERR_B 0x2 |
|
#define | ADSWIO2_MASK_STATUS_ALRT_VI_ERR_A 0x1 |
|
#define | ADSWIO2_MASK_STATUS_LIVE_ADC_DRDY 0x4000 |
|
#define | ADSWIO2_MASK_STATUS_LIVE_ADC_BUSY 0x2000 |
|
#define | ADSWIO2_MASK_STATUS_LIVE_ADC_CURR_CH 0x1C00 |
|
#define | ADSWIO2_MASK_STATUS_LIVE_ALDO1V8 0x200 |
|
#define | ADSWIO2_MASK_STATUS_LIVE_DVCC 0x100 |
|
#define | ADSWIO2_MASK_STATUS_LIVE_AVDD 0x80 |
|
#define | ADSWIO2_MASK_STATUS_LIVE_ALDO5V 0x40 |
|
#define | ADSWIO2_MASK_STATUS_LIVE_CHARGE_PUMP 0x20 |
|
#define | ADSWIO2_MASK_STATUS_LIVE_HI_TEMP 0x10 |
|
#define | ADSWIO2_MASK_STATUS_LIVE_VI_ERR_CURR_D 0x8 |
|
#define | ADSWIO2_MASK_STATUS_LIVE_VI_ERR_CURR_C 0x4 |
|
#define | ADSWIO2_MASK_STATUS_LIVE_VI_ERR_CURR_B 0x2 |
|
#define | ADSWIO2_MASK_STATUS_LIVE_VI_ERR_CURR_A 0x1 |
|
#define | ADSWIO2_MAX_NWORDS 4 |
|
#define | ADSWIO2_MIN_NWORDS 1 |
|
#define | ADSWIO2_REG_NOP 0x0 |
|
#define | ADSWIO2_REG_FUNC_SETUP_CHA 0x1 |
|
#define | ADSWIO2_REG_FUNC_SETUP_CHB 0x2 |
|
#define | ADSWIO2_REG_FUNC_SETUP_CHC 0x3 |
|
#define | ADSWIO2_REG_FUNC_SETUP_CHD 0x4 |
|
#define | ADSWIO2_REG_CFG_ADC_CHA 0x5 |
|
#define | ADSWIO2_REG_CFG_ADC_CHB 0x6 |
|
#define | ADSWIO2_REG_CFG_ADC_CHC 0x7 |
|
#define | ADSWIO2_REG_CFG_ADC_CHD 0x8 |
|
#define | ADSWIO2_REG_CFG_DIN_CHA 0x9 |
|
#define | ADSWIO2_REG_CFG_DIN_CHB 0xA |
|
#define | ADSWIO2_REG_CFG_DIN_CHC 0xB |
|
#define | ADSWIO2_REG_CFG_DIN_CHD 0xC |
|
#define | ADSWIO2_REG_GPO_PARALLEL 0xD |
|
#define | ADSWIO2_REG_CFG_GPO_CHA 0xE |
|
#define | ADSWIO2_REG_CFG_GPO_CHB 0xF |
|
#define | ADSWIO2_REG_CFG_GPO_CHC 0x10 |
|
#define | ADSWIO2_REG_CFG_GPO_CHD 0x11 |
|
#define | ADSWIO2_REG_CFG_OUTPUT_CHA 0x12 |
|
#define | ADSWIO2_REG_CFG_OUTPUT_CHB 0x13 |
|
#define | ADSWIO2_REG_CFG_OUTPUT_CHC 0x14 |
|
#define | ADSWIO2_REG_CFG_OUTPUT_CHD 0x15 |
|
#define | ADSWIO2_REG_DAC_CODE_CHA 0x16 |
|
#define | ADSWIO2_REG_DAC_CODE_CHB 0x17 |
|
#define | ADSWIO2_REG_DAC_CODE_CHC 0x18 |
|
#define | ADSWIO2_REG_DAC_CODE_CHD 0x19 |
|
#define | ADSWIO2_REG_DAC_CODE_CLR_CHA 0x1A |
|
#define | ADSWIO2_REG_DAC_CODE_CLR_CHB 0x1B |
|
#define | ADSWIO2_REG_DAC_CODE_CLR_CHC 0x1C |
|
#define | ADSWIO2_REG_DAC_CODE_CLR_CHD 0x1D |
|
#define | ADSWIO2_REG_DAC_CODE_ACT_CHA 0x1E |
|
#define | ADSWIO2_REG_DAC_CODE_ACT_CHB 0x1F |
|
#define | ADSWIO2_REG_DAC_CODE_ACT_CHC 0x20 |
|
#define | ADSWIO2_REG_DAC_CODE_ACT_CHD 0x21 |
|
#define | ADSWIO2_REG_DIN_THRESH 0x22 |
|
#define | ADSWIO2_REG_ADC_CONV_CTRL 0x23 |
|
#define | ADSWIO2_REG_DIAG_ASSIGN 0x24 |
|
#define | ADSWIO2_REG_DIN_COMP_OUT 0x25 |
|
#define | ADSWIO2_REG_RESULT_ADC_CHA 0x26 |
|
#define | ADSWIO2_REG_RESULT_ADC_CHB 0x27 |
|
#define | ADSWIO2_REG_RESULT_ADC_CHC 0x28 |
|
#define | ADSWIO2_REG_RESULT_ADC_CHD 0x29 |
|
#define | ADSWIO2_REG_RESULT_DIAG1 0x2A |
|
#define | ADSWIO2_REG_RESULT_DIAG2 0x2B |
|
#define | ADSWIO2_REG_RESULT_DIAG3 0x2C |
|
#define | ADSWIO2_REG_RESULT_DIAG4 0x2D |
|
#define | ADSWIO2_REG_STATUS_ALERT 0x2E |
|
#define | ADSWIO2_REG_STATUS_LIVE 0x2F |
|
#define | ADSWIO2_REG_MASK_ALERT 0x3C |
|
#define | ADSWIO2_REG_DIN_COUNTER_CHA 0x3D |
|
#define | ADSWIO2_REG_DIN_COUNTER_CHB 0x3E |
|
#define | ADSWIO2_REG_DIN_COUNTER_CHC 0x3F |
|
#define | ADSWIO2_REG_DIN_COUNTER_CHD 0x40 |
|
#define | ADSWIO2_REG_READ_SELECT 0x41 |
|
#define | ADSWIO2_REG_THERM_RST 0x43 |
|
#define | ADSWIO2_REG_CMD_KEY 0x44 |
|
#define | ADSWIO2_REG_SCRATCH 0x45 |
|
#define | ADSWIO2_REG_SILICON_REV 0x46 |
|
#define | ADSWIO2_SETUP_CONV_EN_CHD 0x8 |
|
#define | ADSWIO2_SETUP_CONV_EN_CHC 0x4 |
|
#define | ADSWIO2_SETUP_CONV_EN_CHB 0x2 |
|
#define | ADSWIO2_SETUP_CONV_EN_CHA 0x1 |
|
#define | ADSWIO2_SETUP_CH_FUNC_HZ 0x0 |
|
#define | ADSWIO2_SETUP_CH_FUNC_VOLT_OUTPUT 0x1 |
|
#define | ADSWIO2_SETUP_CH_FUNC_CURR_OUTPUT 0x2 |
|
#define | ADSWIO2_SETUP_CH_FUNC_VOLT_INPUT 0x3 |
|
#define | ADSWIO2_SETUP_CH_FUNC_CURR_INPUT_PWR_EXT 0x4 |
|
#define | ADSWIO2_SETUP_CH_FUNC_CURR_INPUT_PWR_LOOP 0x5 |
|
#define | ADSWIO2_SETUP_CH_FUNC_RES_MEAS 0x6 |
|
#define | ADSWIO2_SETUP_CH_FUNC_DIG_INPUT_LOGIC 0x7 |
|
#define | ADSWIO2_SETUP_CH_FUNC_DIG_INPUT_PWR_LOOP 0x8 |
|
#define | ADSWIO2_SETUP_CH_FUNC_CURR_INPUT_PWR_EXT_HART 0x9 |
|
#define | ADSWIO2_SETUP_CH_FUNC_CURR_INPUT_PWR_LOOP_HART 0xA |
|
#define | ADSWIO2_SETUP_CONV_EN_DIAG3 0x8 |
|
#define | ADSWIO2_SETUP_CONV_EN_DIAG2 0x4 |
|
#define | ADSWIO2_SETUP_CONV_EN_DIAG1 0x2 |
|
#define | ADSWIO2_SETUP_CONV_EN_DIAG0 0x1 |
|
#define | ADSWIO2_SETUP_DIAG_ASSIGN_AGND 0x0 |
|
#define | ADSWIO2_SETUP_DIAG_ASSIGN_TEMP 0x1 |
|
#define | ADSWIO2_SETUP_DIAG_ASSIGN_AVDD 0x2 |
|
#define | ADSWIO2_SETUP_DIAG_ASSIGN_VAVSS 0x3 |
|
#define | ADSWIO2_SETUP_DIAG_ASSIGN_REFOUT 0x4 |
|
#define | ADSWIO2_SETUP_DIAG_ASSIGN_ALDO5V 0x5 |
|
#define | ADSWIO2_SETUP_DIAG_ASSIGN_ALDO1V8 0x6 |
|
#define | ADSWIO2_SETUP_DIAG_ASSIGN_DLDO1V8 0x7 |
|
#define | ADSWIO2_SETUP_DIAG_ASSIGN_DVCC 0x8 |
|
#define | ADSWIO2_SETUP_DIAG_ASSIGN_IOVDD 0x9 |
|
#define | ADSWIO2_SETUP_DIAG_ASSIGN_SENSELA 0xA |
|
#define | ADSWIO2_SETUP_DIAG_ASSIGN_SENSELB 0xB |
|
#define | ADSWIO2_SETUP_DIAG_ASSIGN_SENSELC 0xC |
|
#define | ADSWIO2_SETUP_DIAG_ASSIGN_SENSELD 0xD |
|
#define | ADSWIO2_SETUP_DIAG_ASSIGN_LVIN 0xE |
|
#define | ADSWIO2_SETUP_CONV_STOP_CONT_CONV_ADC_PWR_UP 0x0 |
|
#define | ADSWIO2_SETUP_CONV_START_SING_SEQ_CONV 0x1 |
|
#define | ADSWIO2_SETUP_CONV_START_CONT_CONV 0x2 |
|
#define | ADSWIO2_SETUP_CONV_STOP_CONT_CONV_ADC_PWR_DWN 0x3 |
|
#define | ADSWIO2_SETUP_ADC_RANGE_0V_TO_10V 0x0 |
|
#define | ADSWIO2_SETUP_ADC_RANGE_2500MV_PWR_EXT 0x20 |
|
#define | ADSWIO2_SETUP_ADC_RANGE_2500MV_PWR_LOOP 0x40 |
|
#define | ADSWIO2_SETUP_ADC_RANGE_2500MV_NEG_TO_2500MV_POS 0x60 |
|
#define | ADSWIO2_SETUP_ADC_RANGE_104MV_NEG_TO_104MV_POS 0x80 |
|
#define | ADSWIO2_SETUP_ADC_SAMPLE_RATE_20SPS 0x0 |
|
#define | ADSWIO2_SETUP_ADC_SAMPLE_RATE_4800SPS 0x8 |
|
#define | ADSWIO2_SETUP_ADC_SAMPLE_RATE_10SPS 0x10 |
|
#define | ADSWIO2_SETUP_ADC_SAMPLE_RATE_1200SPS 0x18 |
|
#define | ADSWIO2_SETUP_ADC_CH_200K_TO_GND 0x4 |
|
#define | ADSWIO2_SETUP_ADC_INPUT_VOLTAGE_AGND_SENSE 0x0 |
|
#define | ADSWIO2_SETUP_ADC_INPUT_VOLTAGE_100_OHM_RES 0x1 |
|
#define | ADSWIO2_SETUP_DIN_COUNT_EN 0x8000 |
|
#define | ADSWIO2_SETUP_DIN_COMP_IN_FILTERED 0x4000 |
|
#define | ADSWIO2_SETUP_DIN_COMP_OUT_INV 0x2000 |
|
#define | ADSWIO2_SETUP_DIN_COMP_EN 0x1000 |
|
#define | ADSWIO2_SETUP_DIN_RANGE_0 0x0 |
|
#define | ADSWIO2_SETUP_DIN_RANGE_1 0x800 |
|
#define | ADSWIO2_SETUP_DIN_DEBOUNCE_MODE_0 0x0 |
|
#define | ADSWIO2_SETUP_DIN_DEBOUNCE_MODE_1 0x20 |
|
#define | ADSWIO2_SETUP_GPO_PARALL_DATA_D 0x8 |
|
#define | ADSWIO2_SETUP_GPO_PARALL_DATA_C 0x4 |
|
#define | ADSWIO2_SETUP_GPO_PARALL_DATA_B 0x2 |
|
#define | ADSWIO2_SETUP_GPO_PARALL_DATA_A 0x1 |
|
#define | ADSWIO2_SETUP_GPO_LOGIC_LOW 0x0 |
|
#define | ADSWIO2_SETUP_GPO_LOGIC_HIGH 0x8 |
|
#define | ADSWIO2_SETUP_OUT_SLEW_EN_LINEAR 0x40 |
|
#define | ADSWIO2_SETUP_OUT_SLEW_EN_HART 0x80 |
|
#define | ADSWIO2_SETUP_OUT_SLEW_LIN_STEP_64_DEC_CODES 0x0 |
|
#define | ADSWIO2_SETUP_OUT_SLEW_LIN_STEP_120_DEC_CODES 0x10 |
|
#define | ADSWIO2_SETUP_OUT_SLEW_LIN_STEP_500_DEC_CODES 0x20 |
|
#define | ADSWIO2_SETUP_OUT_SLEW_LIN_STEP_1820_DEC_CODES 0x30 |
|
#define | ADSWIO2_SETUP_OUT_SLEW_LIN_RATE_4KHZ 0x0 |
|
#define | ADSWIO2_SETUP_OUT_SLEW_LIN_RATE_64KHZ 0x4 |
|
#define | ADSWIO2_SETUP_OUT_SLEW_LIN_RATE_150KHZ 0x8 |
|
#define | ADSWIO2_SETUP_OUT_SLEW_LIN_RATE_240KHZ 0xC |
|
#define | ADSWIO2_SETUP_OUT_CLR_EN 0x2 |
|
#define | ADSWIO2_SETUP_OUT_CURR_LIM_30MA 0x0 |
|
#define | ADSWIO2_SETUP_OUT_CURR_LIM_7_5MA 0x1 |
|
#define | ADSWIO2_SETUP_DIN_THRESH_GND_AND_AVDD 0x0 |
|
#define | ADSWIO2_SETUP_DIN_THRESH_GND_AND_16V 0x1 |
|
#define | ADSWIO2_SETUP_CONV_EN_50_60_HZ_REJ_DIAG 0x400 |
|
#define | ADSWIO2_SETUP_CONV_EN_ALL_CH 0xF |
|
#define | ADSWIO2_SETUP_CONV_EN_ALL_DIAG 0xF |
|
#define | ADSWIO2_SETUP_CONV_DIS_ALL_CH 0x0 |
|
#define | ADSWIO2_SETUP_CONV_DIS_ALL_DIAG 0x0 |
|
#define | ADSWIO2_SETUP_THERM_RST_EN 0x1 |
|
#define | ADSWIO2_STATUS_LIVE_ADC_CURR_CHA 0x0 |
|
#define | ADSWIO2_STATUS_LIVE_ADC_CURR_CHB 0x400 |
|
#define | ADSWIO2_STATUS_LIVE_ADC_CURR_CHC 0x800 |
|
#define | ADSWIO2_STATUS_LIVE_ADC_CURR_CHD 0xC00 |
|
#define | ADSWIO2_STATUS_LIVE_ADC_CURR_DIAG0 0x1000 |
|
#define | ADSWIO2_STATUS_LIVE_ADC_CURR_DIAG1 0x1400 |
|
#define | ADSWIO2_STATUS_LIVE_ADC_CURR_DIAG2 0x1800 |
|
#define | ADSWIO2_STATUS_LIVE_ADC_CURR_DIAG3 0x1C00 |
|
#define | ADSWIO2_CMD_NOP 0x0 |
|
#define | ADSWIO2_CMD_SW_RST_KEY1 0x15FA |
|
#define | ADSWIO2_CMD_SW_RST_KEY2 0xAF51 |
|
#define | ADSWIO2_CMD_LDAC_KEY 0x953A |
|
#define | ADSWIO2_CMD_DAC_CLR_KEY 0x73D1 |
|
#define | ADSWIO2_ERR_STATUS_OK 0 |
|
#define | ADSWIO2_ERR_INIT_DRV 1 |
|
#define | ADSWIO2_ERR_UNSUPPORTED_PIN 2 |
|
#define | ADSWIO2_ERR_RD_STATUS 3 |
|
#define | ADSWIO2_ERR_RD_MODE 4 |
|
#define | ADSWIO2_ERR_RD_NWORDS 5 |
|
#define | ADSWIO2_ERR_CMD_KEY 6 |
|
#define | ADSWIO2_ERR_EN_CH 7 |
|
#define | ADSWIO2_ERR_EN_DIAG 8 |
|
#define | ADSWIO2_ERR_CRC 9 |
|
#define | ADSWIO2_ERR_REG_ADDR 10 |
|
#define | ADSWIO2_ERR_CONV_MODE 11 |
|
#define | ADSWIO2_ERR_CH_FUNC 12 |
|
#define | ADSWIO2_ERR_DIAG_ASSIGN 13 |
|
#define | ADSWIO2_ID_SILICON_REV 0x8 |
|
#define | ADSWIO2_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE |
| Data sample selection.
|
|
#define | ADSWIO2_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE |
|