balancer4 2.0.0.0
balancer4.h
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1/****************************************************************************
2** Copyright (C) 2020 MikroElektronika d.o.o.
3** Contact: https://www.mikroe.com/contact
4**
5** Permission is hereby granted, free of charge, to any person obtaining a copy
6** of this software and associated documentation files (the "Software"), to deal
7** in the Software without restriction, including without limitation the rights
8** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9** copies of the Software, and to permit persons to whom the Software is
10** furnished to do so, subject to the following conditions:
11** The above copyright notice and this permission notice shall be
12** included in all copies or substantial portions of the Software.
13**
14** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
17** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
18** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
19** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20** USE OR OTHER DEALINGS IN THE SOFTWARE.
21****************************************************************************/
22
28#ifndef BALANCER4_H
29#define BALANCER4_H
30
31#ifdef __cplusplus
32extern "C"{
33#endif
34
39#ifdef PREINIT_SUPPORTED
40#include "preinit.h"
41#endif
42
43#ifdef MikroCCoreVersion
44 #if MikroCCoreVersion >= 1
45 #include "delays.h"
46 #endif
47#endif
48
49#include "drv_digital_out.h"
50#include "drv_digital_in.h"
51#include "drv_i2c_master.h"
52
73#define BALANCER4_REG_CONFIG0 0x00
74#define BALANCER4_REG_CONFIG1 0x01
75#define BALANCER4_REG_TIMER 0x02
76#define BALANCER4_REG_STATUS 0x03
77#define BALANCER4_REG_FAULT 0x04
78
79 // balancer4_reg
80
95#define BALANCER4_CONFIG0_VBAT_REG_8p3V 0x00
96#define BALANCER4_CONFIG0_VBAT_REG_8p4V 0x20
97#define BALANCER4_CONFIG0_VBAT_REG_8p5V 0x40
98#define BALANCER4_CONFIG0_VBAT_REG_8p6V 0x60
99#define BALANCER4_CONFIG0_VBAT_REG_8p7V 0x80
100#define BALANCER4_CONFIG0_VBAT_REG_8p8V 0xA0
101#define BALANCER4_CONFIG0_VBAT_REG_8p9V 0xC0
102#define BALANCER4_CONFIG0_VBAT_REG_8p2V 0xE0
103#define BALANCER4_CONFIG0_CHARGING_DIS 0x00
104#define BALANCER4_CONFIG0_CHARGING_EN 0x10
105#define BALANCER4_CONFIG0_VBAT_PRE_6V 0x00
106#define BALANCER4_CONFIG0_VBAT_PRE_6p1V 0x02
107#define BALANCER4_CONFIG0_VBAT_PRE_6p2V 0x04
108#define BALANCER4_CONFIG0_VBAT_PRE_6p3V 0x06
109#define BALANCER4_CONFIG0_VBAT_PRE_6p4V 0x08
110#define BALANCER4_CONFIG0_VBAT_PRE_6p5V 0x0A
111#define BALANCER4_CONFIG0_VBAT_PRE_6p6V 0x0C
112#define BALANCER4_CONFIG0_VBAT_PRE_6p7V 0x0E
113#define BALANCER4_CONFIG0_CELL_OVP_HYS_80mV 0x00
114#define BALANCER4_CONFIG0_CELL_OVP_HYS_0mV 0x01
115
120#define BALANCER4_CONFIG1_NTC_TYPE_STANDARD 0x00
121#define BALANCER4_CONFIG1_NTC_TYPE_JEITA 0x80
122#define BALANCER4_CONFIG1_VCELL_BAL_3p5V 0x00
123#define BALANCER4_CONFIG1_VCELL_BAL_3p7V 0x40
124#define BALANCER4_CONFIG1_BAL_THD_H2L_50mV 0x00
125#define BALANCER4_CONFIG1_BAL_THD_H2L_70mV 0x20
126#define BALANCER4_CONFIG1_BAL_THD_L2H_50mV 0x00
127#define BALANCER4_CONFIG1_BAL_THD_L2H_70mV 0x10
128#define BALANCER4_CONFIG1_ICC_250mA 0x00
129#define BALANCER4_CONFIG1_ICC_300mA 0x01
130#define BALANCER4_CONFIG1_ICC_350mA 0x02
131#define BALANCER4_CONFIG1_ICC_400mA 0x03
132#define BALANCER4_CONFIG1_ICC_450mA 0x04
133#define BALANCER4_CONFIG1_ICC_500mA 0x05
134#define BALANCER4_CONFIG1_ICC_550mA 0x06
135#define BALANCER4_CONFIG1_ICC_600mA 0x07
136#define BALANCER4_CONFIG1_ICC_650mA 0x08
137#define BALANCER4_CONFIG1_ICC_700mA 0x09
138#define BALANCER4_CONFIG1_ICC_750mA 0x0A
139#define BALANCER4_CONFIG1_ICC_800mA 0x0B
140#define BALANCER4_CONFIG1_ICC_850mA 0x0C
141#define BALANCER4_CONFIG1_ICC_900mA 0x0D
142#define BALANCER4_CONFIG1_ICC_950mA 0x0E
143#define BALANCER4_CONFIG1_ICC_1000mA 0x0F
144
149#define BALANCER4_TIMER_FSW_600KHZ 0x00
150#define BALANCER4_TIMER_FSW_1200KHZ 0x80
151#define BALANCER4_TIMER_I2C_WD_TIMER_NORMAL 0x00
152#define BALANCER4_TIMER_I2C_WD_TIMER_RESET 0x40
153#define BALANCER4_TIMER_WD_TIMER_DIS 0x00
154#define BALANCER4_TIMER_WD_TIMER_40S 0x10
155#define BALANCER4_TIMER_WD_TIMER_80S 0x20
156#define BALANCER4_TIMER_WD_TIMER_160S 0x30
157#define BALANCER4_TIMER_REGISTER_KEEP 0x00
158#define BALANCER4_TIMER_REGISTER_RESET 0x08
159#define BALANCER4_TIMER_CHG_TIMER_DIS 0x00
160#define BALANCER4_TIMER_CHG_TIMER_8H 0x02
161#define BALANCER4_TIMER_CHG_TIMER_20H 0x04
162#define BALANCER4_TIMER_CHG_TIMER_12H 0x06
163#define BALANCER4_TIMER_EN_SUSP_BOOST_DIS 0x00
164#define BALANCER4_TIMER_EN_SUSP_BOOST_EN 0x01
165
170#define BALANCER4_STATUS_NOT_CHARGING 0x00
171#define BALANCER4_STATUS_PRE_CHARGE 0x10
172#define BALANCER4_STATUS_CONSTANT_CHARGE 0x20
173#define BALANCER4_STATUS_CHARGING_COMPLETE 0x30
174#define BALANCER4_STATUS_CHG_STAT_MASK 0x30
175#define BALANCER4_STATUS_NOT_IN_PPM 0x00
176#define BALANCER4_STATUS_IN_VIN_PPM 0x08
177#define BALANCER4_STATUS_PPM_STAT_MASK 0x08
178#define BALANCER4_STATUS_BATTERY_PRESENT 0x00
179#define BALANCER4_STATUS_BATTERY_MISSING 0x04
180#define BALANCER4_STATUS_BATFLOAT_STAT_MASK 0x04
181#define BALANCER4_STATUS_THERM_NORMAL 0x00
182#define BALANCER4_STATUS_THERM_REGULATION 0x02
183#define BALANCER4_STATUS_THERM_STAT_MASK 0x02
184#define BALANCER4_STATUS_NOT_IN_VSYS_MIN 0x00
185#define BALANCER4_STATUS_IN_VSYS_MIN_REG 0x01
186#define BALANCER4_STATUS_VSYS_STAT_MASK 0x01
187
192#define BALANCER4_FAULT_WD 0x80
193#define BALANCER4_FAULT_INPUT 0x40
194#define BALANCER4_FAULT_THERMAL_SD 0x20
195#define BALANCER4_FAULT_TIMER 0x10
196#define BALANCER4_FAULT_BAT 0x08
197#define BALANCER4_FAULT_NTC_COLD 0x01
198#define BALANCER4_FAULT_NTC_COOL 0x02
199#define BALANCER4_FAULT_NTC_WARM 0x03
200#define BALANCER4_FAULT_NTC_HOT 0x04
201#define BALANCER4_FAULT_NTC_MASK 0x07
202
208#define BALANCER4_SET_DEV_ADDR 0x4B
209
210 // balancer4_set
211
226#define BALANCER4_MAP_MIKROBUS( cfg, mikrobus ) \
227 cfg.scl = MIKROBUS( mikrobus, MIKROBUS_SCL ); \
228 cfg.sda = MIKROBUS( mikrobus, MIKROBUS_SDA )
229
230 // balancer4_map
231 // balancer4
232
237typedef struct
238{
239 // Modules
240 i2c_master_t i2c;
242 // I2C slave address
246
251typedef struct
252{
253 pin_name_t scl;
254 pin_name_t sda;
256 uint32_t i2c_speed;
257 uint8_t i2c_address;
260
271
288
303
317
331err_t balancer4_write_register ( balancer4_t *ctx, uint8_t reg, uint8_t data_in );
332
346err_t balancer4_write_and_verify_register ( balancer4_t *ctx, uint8_t reg, uint8_t data_in );
347
361err_t balancer4_read_register ( balancer4_t *ctx, uint8_t reg, uint8_t *data_out );
362
363#ifdef __cplusplus
364}
365#endif
366#endif // BALANCER4_H
367
368 // balancer4
369
370// ------------------------------------------------------------------------ END
balancer4_return_value_t
Balancer 4 Click return value data.
Definition balancer4.h:266
@ BALANCER4_ERROR
Definition balancer4.h:268
@ BALANCER4_OK
Definition balancer4.h:267
err_t balancer4_write_and_verify_register(balancer4_t *ctx, uint8_t reg, uint8_t data_in)
Balancer 4 write and verify register function.
err_t balancer4_default_cfg(balancer4_t *ctx)
Balancer 4 default configuration function.
err_t balancer4_write_register(balancer4_t *ctx, uint8_t reg, uint8_t data_in)
Balancer 4 write register function.
err_t balancer4_read_register(balancer4_t *ctx, uint8_t reg, uint8_t *data_out)
Balancer 4 read register function.
err_t balancer4_init(balancer4_t *ctx, balancer4_cfg_t *cfg)
Balancer 4 initialization function.
void balancer4_cfg_setup(balancer4_cfg_t *cfg)
Balancer 4 configuration object setup function.
Balancer 4 Click configuration object.
Definition balancer4.h:252
uint32_t i2c_speed
Definition balancer4.h:256
pin_name_t scl
Definition balancer4.h:253
pin_name_t sda
Definition balancer4.h:254
uint8_t i2c_address
Definition balancer4.h:257
Balancer 4 Click context object.
Definition balancer4.h:238
i2c_master_t i2c
Definition balancer4.h:240
uint8_t slave_address
Definition balancer4.h:243