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balancer5 2.0.0.0
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| #define BALANCER5_REG_ADC_CTRL 0x15 |
| #define BALANCER5_REG_ADC_FUNCTION_DISABLE 0x16 |
| #define BALANCER5_REG_CELL_BALANCING_CTRL1 0x28 |
| #define BALANCER5_REG_CELL_BALANCING_CTRL2 0x29 |
| #define BALANCER5_REG_CELL_BALANCING_FLAG 0x2B |
| #define BALANCER5_REG_CELL_BALANCING_MASK 0x2C |
| #define BALANCER5_REG_CELL_BALANCING_STATUS_N_CNTRL 0x2A |
| #define BALANCER5_REG_CELL_V_LIMIT 0x00 |
| #define BALANCER5_REG_CHARGE_CURR_LIMIT 0x01 |
| #define BALANCER5_REG_CHARGER_CTRL_1 0x05 |
| #define BALANCER5_REG_CHARGER_CTRL_2 0x06 |
| #define BALANCER5_REG_CHARGER_CTRL_3 0x07 |
| #define BALANCER5_REG_CHARGER_CTRL_4 0x08 |
| #define BALANCER5_REG_CHARGER_FLAG_1 0x0F |
| #define BALANCER5_REG_CHARGER_FLAG_2 0x10 |
| #define BALANCER5_REG_CHARGER_MASK_1 0x12 |
| #define BALANCER5_REG_CHARGER_MASK_2 0x13 |
| #define BALANCER5_REG_CHARGER_STATUS_1 0x0B |
| #define BALANCER5_REG_CHARGER_STATUS_2 0x0C |
| #define BALANCER5_REG_FAULT_FLAG 0x11 |
| #define BALANCER5_REG_FAULT_MASK 0x14 |
| #define BALANCER5_REG_FAULT_STATUS 0x0E |
| #define BALANCER5_REG_IBUS_ADC0 0x18 |
| #define BALANCER5_REG_IBUS_ADC1 0x17 |
| #define BALANCER5_REG_ICHG_ADC0 0x1A |
| #define BALANCER5_REG_ICHG_ADC1 0x19 |
| #define BALANCER5_REG_ICO_CURR_LIMIT 0x0A |
| #define BALANCER5_REG_INPUT_CURR_LIMIT 0x03 |
| #define BALANCER5_REG_INPUT_V_LIMIT 0x02 |
| #define BALANCER5_REG_NTC_STATUS 0x0D |
| #define BALANCER5_REG_PART_INFO 0x25 |
| #define BALANCER5_REG_PRECHARGE_N_TERMINATION_CTRL 0x04 |
| #define BALANCER5_REG_TDIE_ADC0 0x24 |
| #define BALANCER5_REG_TDIE_ADC1 0x23 |
| #define BALANCER5_REG_TS_ADC0 0x22 |
| #define BALANCER5_REG_TS_ADC1 0x21 |
| #define BALANCER5_REG_VBAT_ADC0 0x1E |
| #define BALANCER5_REG_VBAT_ADC1 0x1D |
| #define BALANCER5_REG_VBUS_ADC0 0x1C |
| #define BALANCER5_REG_VBUS_ADC1 0x1B |
| #define BALANCER5_REG_VCELLBOT_ADC0 0x27 |
| #define BALANCER5_REG_VCELLBOT_ADC1 0x26 |
| #define BALANCER5_REG_VCELLTOP_ADC0 0x20 |
| #define BALANCER5_REG_VCELLTOP_ADC1 0x1F |