c3dhall3 2.0.0.0
CFG-A Register bits

Macros

#define C3DHALL3_CFGA_TEMPERATURE_COMPENSATION   0x80
 
#define C3DHALL3_CFGA_REBOOT_MEMORY   0x40
 
#define C3DHALL3_CFGA_SOFT_RESET   0x20
 
#define C3DHALL3_CFGA_LOW_POWER_MODE   0x10
 
#define C3DHALL3_CFGA_OUTPUT_DATA_RATE_10   0x00
 
#define C3DHALL3_CFGA_OUTPUT_DATA_RATE_20   0x04
 
#define C3DHALL3_CFGA_OUTPUT_DATA_RATE_50   0x08
 
#define C3DHALL3_CFGA_OUTPUT_DATA_RATE_100   0x0C
 
#define C3DHALL3_CFGA_MODE_CONTINIOUS   0x00
 
#define C3DHALL3_CFGA_MODE_SINGLE   0x01
 
#define C3DHALL3_CFGA_MODE_IDLE   0x02
 
#define C3DHALL3_CFGA_MODE_IDLE_DEFAULT   0x03
 

Detailed Description

Macro Definition Documentation

◆ C3DHALL3_CFGA_LOW_POWER_MODE

#define C3DHALL3_CFGA_LOW_POWER_MODE   0x10

◆ C3DHALL3_CFGA_MODE_CONTINIOUS

#define C3DHALL3_CFGA_MODE_CONTINIOUS   0x00

◆ C3DHALL3_CFGA_MODE_IDLE

#define C3DHALL3_CFGA_MODE_IDLE   0x02

◆ C3DHALL3_CFGA_MODE_IDLE_DEFAULT

#define C3DHALL3_CFGA_MODE_IDLE_DEFAULT   0x03

◆ C3DHALL3_CFGA_MODE_SINGLE

#define C3DHALL3_CFGA_MODE_SINGLE   0x01

◆ C3DHALL3_CFGA_OUTPUT_DATA_RATE_10

#define C3DHALL3_CFGA_OUTPUT_DATA_RATE_10   0x00

◆ C3DHALL3_CFGA_OUTPUT_DATA_RATE_100

#define C3DHALL3_CFGA_OUTPUT_DATA_RATE_100   0x0C

◆ C3DHALL3_CFGA_OUTPUT_DATA_RATE_20

#define C3DHALL3_CFGA_OUTPUT_DATA_RATE_20   0x04

◆ C3DHALL3_CFGA_OUTPUT_DATA_RATE_50

#define C3DHALL3_CFGA_OUTPUT_DATA_RATE_50   0x08

◆ C3DHALL3_CFGA_REBOOT_MEMORY

#define C3DHALL3_CFGA_REBOOT_MEMORY   0x40

◆ C3DHALL3_CFGA_SOFT_RESET

#define C3DHALL3_CFGA_SOFT_RESET   0x20

◆ C3DHALL3_CFGA_TEMPERATURE_COMPENSATION

#define C3DHALL3_CFGA_TEMPERATURE_COMPENSATION   0x80