List of registers of 3D Hall 4 Click driver. More...

Macros
#define	C3DHALL4_REG_0 0x00
	3D Hall 4 register map.

#define	C3DHALL4_REG_1 0x01

#define	C3DHALL4_REG_2 0x02

#define	C3DHALL4_REG_3 0x03

#define	C3DHALL4_REG_4 0x04

#define	C3DHALL4_REG_5 0x05

#define	C3DHALL4_REG_6 0x06

#define	C3DHALL4_REG_7 0x07

#define	C3DHALL4_REG_PWM_CTRL 0x08

#define	C3DHALL4_REG_CHANNEL_CTRL 0x09

#define	C3DHALL4_REG_OSC_TRIM 0x0A

#define	C3DHALL4_REG_THRES_X 0x0B

#define	C3DHALL4_REG_THRES_Z 0x0C

#define	C3DHALL4_REG_THRES_Y 0x0D

#define	C3DHALL4_REG_G_CTRL_X 0x0E

#define	C3DHALL4_REG_G_CTRL_Z 0x0F

#define	C3DHALL4_REG_G_CTRL_Y 0x10

#define	C3DHALL4_REG_DAC_X 0x11

#define	C3DHALL4_REG_DAC_Z 0x12

#define	C3DHALL4_REG_DAC_Y 0x13

#define	C3DHALL4_REG_SENS_X 0x14

#define	C3DHALL4_REG_SENS_Z 0x15

#define	C3DHALL4_REG_SENS_Y 0x16

#define	C3DHALL4_REG_SENS_TC_X 0x17

#define	C3DHALL4_REG_SENS_TC_Z 0x18

#define	C3DHALL4_REG_SENS_TC_Y 0x19

#define	C3DHALL4_REG_OFFSET_X 0x1A

#define	C3DHALL4_REG_OFFSET_Z 0x1B

#define	C3DHALL4_REG_OFFSET_Y 0x1C

#define	C3DHALL4_REG_OFFSET_TC_X 0x1D

#define	C3DHALL4_REG_OFFSET_TC_Z 0x1E

#define	C3DHALL4_REG_OFFSET_TC_Y 0x1F

#define	C3DHALL4_REG_STATUS 0x3F

#define	C3DHALL4_REG_ADC_DATAXL 0x40

#define	C3DHALL4_REG_ADC_DATAXH 0x41

#define	C3DHALL4_REG_ADC_DATAZL 0x42

#define	C3DHALL4_REG_ADC_DATAZH 0x43

#define	C3DHALL4_REG_ADC_DATAYL 0x44

#define	C3DHALL4_REG_ADC_DATAYH 0x45

#define	C3DHALL4_REG_ADC_DATATL 0x46

#define	C3DHALL4_REG_ADC_DATATH 0x47

#define	C3DHALL4_EREG_0 0x00
	3D Hall 4 eeprom map.

#define	C3DHALL4_EREG_1 0x01

#define	C3DHALL4_EREG_2 0x02

#define	C3DHALL4_EREG_3 0x03

#define	C3DHALL4_EREG_4 0x04

#define	C3DHALL4_EREG_5 0x05

#define	C3DHALL4_EREG_6 0x06

#define	C3DHALL4_EREG_7 0x07

#define	C3DHALL4_EREG_PWM_CTRL 0x08

#define	C3DHALL4_EREG_CHANNEL_CTRL 0x09

#define	C3DHALL4_EREG_OSC_TRIM 0x0A

#define	C3DHALL4_EREG_THRES_Y 0x0B

#define	C3DHALL4_EREG_THRES_X 0x0C

#define	C3DHALL4_EREG_THRES_Z 0x0D

#define	C3DHALL4_EREG_GAIN_SEL 0x0E

#define	C3DHALL4_EREG_DAC_Y_G0 0x40

#define	C3DHALL4_EREG_DAC_X_G0 0x41

#define	C3DHALL4_EREG_DAC_Z_G0 0x42

#define	C3DHALL4_EREG_SENS_Y_G0 0x43

#define	C3DHALL4_EREG_SENS_X_G0 0x44

#define	C3DHALL4_EREG_SENS_Z_G0 0x45

#define	C3DHALL4_EREG_SENS_TC_Y_G0 0x46

#define	C3DHALL4_EREG_SENS_TC_X_G0 0x47

#define	C3DHALL4_EREG_SENS_TC_Z_G0 0x48

#define	C3DHALL4_EREG_OFFSET_Y_G0 0x49

#define	C3DHALL4_EREG_OFFSET_X_G0 0x4A

#define	C3DHALL4_EREG_OFFSET_Z_G0 0x4B

#define	C3DHALL4_EREG_OFFSET_TC_Y_G0 0x4C

#define	C3DHALL4_EREG_OFFSET_TC_X_G0 0x4D

#define	C3DHALL4_EREG_OFFSET_TC_Z_G0 0x4E

#define	C3DHALL4_EREG_DAC_Y_G1 0x50

#define	C3DHALL4_EREG_DAC_X_G1 0x51

#define	C3DHALL4_EREG_DAC_Z_G1 0x52

#define	C3DHALL4_EREG_SENS_Y_G1 0x53

#define	C3DHALL4_EREG_SENS_X_G1 0x54

#define	C3DHALL4_EREG_SENS_Z_G1 0x55

#define	C3DHALL4_EREG_SENS_TC_Y_G1 0x56

#define	C3DHALL4_EREG_SENS_TC_X_G1 0x57

#define	C3DHALL4_EREG_SENS_TC_Z_G1 0x58

#define	C3DHALL4_EREG_OFFSET_Y_G1 0x59

#define	C3DHALL4_EREG_OFFSET_X_G1 0x5A

#define	C3DHALL4_EREG_OFFSET_Z_G1 0x5B

#define	C3DHALL4_EREG_OFFSET_TC_Y_G1 0x5C

#define	C3DHALL4_EREG_OFFSET_TC_X_G1 0x5D

#define	C3DHALL4_EREG_OFFSET_TC_Z_G1 0x5E

#define	C3DHALL4_EREG_DAC_Y_G2 0x60

#define	C3DHALL4_EREG_DAC_X_G2 0x61

#define	C3DHALL4_EREG_DAC_Z_G2 0x62

#define	C3DHALL4_EREG_SENS_Y_G2 0x63

#define	C3DHALL4_EREG_SENS_X_G2 0x64

#define	C3DHALL4_EREG_SENS_Z_G2 0x65

#define	C3DHALL4_EREG_SENS_TC_Y_G2 0x66

#define	C3DHALL4_EREG_SENS_TC_X_G2 0x67

#define	C3DHALL4_EREG_SENS_TC_Z_G2 0x68

#define	C3DHALL4_EREG_OFFSET_Y_G2 0x69

#define	C3DHALL4_EREG_OFFSET_X_G2 0x6A

#define	C3DHALL4_EREG_OFFSET_Z_G2 0x6B

#define	C3DHALL4_EREG_OFFSET_TC_Y_G2 0x6C

#define	C3DHALL4_EREG_OFFSET_TC_X_G2 0x6D

#define	C3DHALL4_EREG_OFFSET_TC_Z_G2 0x6E

#define	C3DHALL4_EREG_DAC_Y_G3 0x70

#define	C3DHALL4_EREG_DAC_X_G3 0x71

#define	C3DHALL4_EREG_DAC_Z_G3 0x72

#define	C3DHALL4_EREG_SENS_Y_G3 0x73

#define	C3DHALL4_EREG_SENS_X_G3 0x74

#define	C3DHALL4_EREG_SENS_Z_G3 0x75

#define	C3DHALL4_EREG_SENS_TC_Y_G3 0x76

#define	C3DHALL4_EREG_SENS_TC_X_G3 0x77

#define	C3DHALL4_EREG_SENS_TC_Z_G3 0x78

#define	C3DHALL4_EREG_OFFSET_Y_G3 0x79

#define	C3DHALL4_EREG_OFFSET_X_G3 0x7A

#define	C3DHALL4_EREG_OFFSET_Z_G3 0x7B

#define	C3DHALL4_EREG_OFFSET_TC_Y_G3 0x7C

#define	C3DHALL4_EREG_OFFSET_TC_X_G3 0x7D

#define	C3DHALL4_EREG_OFFSET_TC_Z_G3 0x7E

#define	C3DHALL4_EREG_KEY 0xFE

#define	C3DHALL4_EREG_CHECKSUM 0xFF

Detailed Description

List of registers of 3D Hall 4 Click driver.

Macro Definition Documentation

◆ C3DHALL4_EREG_0

#define C3DHALL4_EREG_0 0x00

3D Hall 4 eeprom map.

Specified eeprom map of 3D Hall 4 Click driver.

◆ C3DHALL4_EREG_1

#define C3DHALL4_EREG_1 0x01

◆ C3DHALL4_EREG_2

#define C3DHALL4_EREG_2 0x02

◆ C3DHALL4_EREG_3

#define C3DHALL4_EREG_3 0x03

◆ C3DHALL4_EREG_4

#define C3DHALL4_EREG_4 0x04

◆ C3DHALL4_EREG_5

#define C3DHALL4_EREG_5 0x05

◆ C3DHALL4_EREG_6

#define C3DHALL4_EREG_6 0x06

◆ C3DHALL4_EREG_7

#define C3DHALL4_EREG_7 0x07

◆ C3DHALL4_EREG_CHANNEL_CTRL

#define C3DHALL4_EREG_CHANNEL_CTRL 0x09

◆ C3DHALL4_EREG_CHECKSUM

#define C3DHALL4_EREG_CHECKSUM 0xFF

◆ C3DHALL4_EREG_DAC_X_G0

#define C3DHALL4_EREG_DAC_X_G0 0x41

◆ C3DHALL4_EREG_DAC_X_G1

#define C3DHALL4_EREG_DAC_X_G1 0x51

◆ C3DHALL4_EREG_DAC_X_G2

#define C3DHALL4_EREG_DAC_X_G2 0x61

◆ C3DHALL4_EREG_DAC_X_G3

#define C3DHALL4_EREG_DAC_X_G3 0x71

◆ C3DHALL4_EREG_DAC_Y_G0

#define C3DHALL4_EREG_DAC_Y_G0 0x40

◆ C3DHALL4_EREG_DAC_Y_G1

#define C3DHALL4_EREG_DAC_Y_G1 0x50

◆ C3DHALL4_EREG_DAC_Y_G2

#define C3DHALL4_EREG_DAC_Y_G2 0x60

◆ C3DHALL4_EREG_DAC_Y_G3

#define C3DHALL4_EREG_DAC_Y_G3 0x70

◆ C3DHALL4_EREG_DAC_Z_G0

#define C3DHALL4_EREG_DAC_Z_G0 0x42

◆ C3DHALL4_EREG_DAC_Z_G1

#define C3DHALL4_EREG_DAC_Z_G1 0x52

◆ C3DHALL4_EREG_DAC_Z_G2

#define C3DHALL4_EREG_DAC_Z_G2 0x62

◆ C3DHALL4_EREG_DAC_Z_G3

#define C3DHALL4_EREG_DAC_Z_G3 0x72

◆ C3DHALL4_EREG_GAIN_SEL

#define C3DHALL4_EREG_GAIN_SEL 0x0E

◆ C3DHALL4_EREG_KEY

#define C3DHALL4_EREG_KEY 0xFE

◆ C3DHALL4_EREG_OFFSET_TC_X_G0

#define C3DHALL4_EREG_OFFSET_TC_X_G0 0x4D

◆ C3DHALL4_EREG_OFFSET_TC_X_G1

#define C3DHALL4_EREG_OFFSET_TC_X_G1 0x5D

◆ C3DHALL4_EREG_OFFSET_TC_X_G2

#define C3DHALL4_EREG_OFFSET_TC_X_G2 0x6D

◆ C3DHALL4_EREG_OFFSET_TC_X_G3

#define C3DHALL4_EREG_OFFSET_TC_X_G3 0x7D

◆ C3DHALL4_EREG_OFFSET_TC_Y_G0

#define C3DHALL4_EREG_OFFSET_TC_Y_G0 0x4C

◆ C3DHALL4_EREG_OFFSET_TC_Y_G1

#define C3DHALL4_EREG_OFFSET_TC_Y_G1 0x5C

◆ C3DHALL4_EREG_OFFSET_TC_Y_G2

#define C3DHALL4_EREG_OFFSET_TC_Y_G2 0x6C

◆ C3DHALL4_EREG_OFFSET_TC_Y_G3

#define C3DHALL4_EREG_OFFSET_TC_Y_G3 0x7C

◆ C3DHALL4_EREG_OFFSET_TC_Z_G0

#define C3DHALL4_EREG_OFFSET_TC_Z_G0 0x4E

◆ C3DHALL4_EREG_OFFSET_TC_Z_G1

#define C3DHALL4_EREG_OFFSET_TC_Z_G1 0x5E

◆ C3DHALL4_EREG_OFFSET_TC_Z_G2

#define C3DHALL4_EREG_OFFSET_TC_Z_G2 0x6E

◆ C3DHALL4_EREG_OFFSET_TC_Z_G3

#define C3DHALL4_EREG_OFFSET_TC_Z_G3 0x7E

◆ C3DHALL4_EREG_OFFSET_X_G0

#define C3DHALL4_EREG_OFFSET_X_G0 0x4A

◆ C3DHALL4_EREG_OFFSET_X_G1

#define C3DHALL4_EREG_OFFSET_X_G1 0x5A

◆ C3DHALL4_EREG_OFFSET_X_G2

#define C3DHALL4_EREG_OFFSET_X_G2 0x6A

◆ C3DHALL4_EREG_OFFSET_X_G3

#define C3DHALL4_EREG_OFFSET_X_G3 0x7A

◆ C3DHALL4_EREG_OFFSET_Y_G0

#define C3DHALL4_EREG_OFFSET_Y_G0 0x49

◆ C3DHALL4_EREG_OFFSET_Y_G1

#define C3DHALL4_EREG_OFFSET_Y_G1 0x59

◆ C3DHALL4_EREG_OFFSET_Y_G2

#define C3DHALL4_EREG_OFFSET_Y_G2 0x69

◆ C3DHALL4_EREG_OFFSET_Y_G3

#define C3DHALL4_EREG_OFFSET_Y_G3 0x79

◆ C3DHALL4_EREG_OFFSET_Z_G0

#define C3DHALL4_EREG_OFFSET_Z_G0 0x4B

◆ C3DHALL4_EREG_OFFSET_Z_G1

#define C3DHALL4_EREG_OFFSET_Z_G1 0x5B

◆ C3DHALL4_EREG_OFFSET_Z_G2

#define C3DHALL4_EREG_OFFSET_Z_G2 0x6B

◆ C3DHALL4_EREG_OFFSET_Z_G3

#define C3DHALL4_EREG_OFFSET_Z_G3 0x7B

◆ C3DHALL4_EREG_OSC_TRIM

#define C3DHALL4_EREG_OSC_TRIM 0x0A

◆ C3DHALL4_EREG_PWM_CTRL

#define C3DHALL4_EREG_PWM_CTRL 0x08

◆ C3DHALL4_EREG_SENS_TC_X_G0

#define C3DHALL4_EREG_SENS_TC_X_G0 0x47

◆ C3DHALL4_EREG_SENS_TC_X_G1

#define C3DHALL4_EREG_SENS_TC_X_G1 0x57

◆ C3DHALL4_EREG_SENS_TC_X_G2

#define C3DHALL4_EREG_SENS_TC_X_G2 0x67

◆ C3DHALL4_EREG_SENS_TC_X_G3

#define C3DHALL4_EREG_SENS_TC_X_G3 0x77

◆ C3DHALL4_EREG_SENS_TC_Y_G0

#define C3DHALL4_EREG_SENS_TC_Y_G0 0x46

◆ C3DHALL4_EREG_SENS_TC_Y_G1

#define C3DHALL4_EREG_SENS_TC_Y_G1 0x56

◆ C3DHALL4_EREG_SENS_TC_Y_G2

#define C3DHALL4_EREG_SENS_TC_Y_G2 0x66

◆ C3DHALL4_EREG_SENS_TC_Y_G3

#define C3DHALL4_EREG_SENS_TC_Y_G3 0x76

◆ C3DHALL4_EREG_SENS_TC_Z_G0

#define C3DHALL4_EREG_SENS_TC_Z_G0 0x48

◆ C3DHALL4_EREG_SENS_TC_Z_G1

#define C3DHALL4_EREG_SENS_TC_Z_G1 0x58

◆ C3DHALL4_EREG_SENS_TC_Z_G2

#define C3DHALL4_EREG_SENS_TC_Z_G2 0x68

◆ C3DHALL4_EREG_SENS_TC_Z_G3

#define C3DHALL4_EREG_SENS_TC_Z_G3 0x78

◆ C3DHALL4_EREG_SENS_X_G0

#define C3DHALL4_EREG_SENS_X_G0 0x44

◆ C3DHALL4_EREG_SENS_X_G1

#define C3DHALL4_EREG_SENS_X_G1 0x54

◆ C3DHALL4_EREG_SENS_X_G2

#define C3DHALL4_EREG_SENS_X_G2 0x64

◆ C3DHALL4_EREG_SENS_X_G3

#define C3DHALL4_EREG_SENS_X_G3 0x74

◆ C3DHALL4_EREG_SENS_Y_G0

#define C3DHALL4_EREG_SENS_Y_G0 0x43

◆ C3DHALL4_EREG_SENS_Y_G1

#define C3DHALL4_EREG_SENS_Y_G1 0x53

◆ C3DHALL4_EREG_SENS_Y_G2

#define C3DHALL4_EREG_SENS_Y_G2 0x63

◆ C3DHALL4_EREG_SENS_Y_G3

#define C3DHALL4_EREG_SENS_Y_G3 0x73

◆ C3DHALL4_EREG_SENS_Z_G0

#define C3DHALL4_EREG_SENS_Z_G0 0x45

◆ C3DHALL4_EREG_SENS_Z_G1

#define C3DHALL4_EREG_SENS_Z_G1 0x55

◆ C3DHALL4_EREG_SENS_Z_G2

#define C3DHALL4_EREG_SENS_Z_G2 0x65

◆ C3DHALL4_EREG_SENS_Z_G3

#define C3DHALL4_EREG_SENS_Z_G3 0x75

◆ C3DHALL4_EREG_THRES_X

#define C3DHALL4_EREG_THRES_X 0x0C

◆ C3DHALL4_EREG_THRES_Y

#define C3DHALL4_EREG_THRES_Y 0x0B

◆ C3DHALL4_EREG_THRES_Z

#define C3DHALL4_EREG_THRES_Z 0x0D

◆ C3DHALL4_REG_0

#define C3DHALL4_REG_0 0x00

3D Hall 4 register map.

Specified register map of 3D Hall 4 Click driver.

◆ C3DHALL4_REG_1

#define C3DHALL4_REG_1 0x01

◆ C3DHALL4_REG_2

#define C3DHALL4_REG_2 0x02

◆ C3DHALL4_REG_3

#define C3DHALL4_REG_3 0x03

◆ C3DHALL4_REG_4

#define C3DHALL4_REG_4 0x04

◆ C3DHALL4_REG_5

#define C3DHALL4_REG_5 0x05

◆ C3DHALL4_REG_6

#define C3DHALL4_REG_6 0x06

◆ C3DHALL4_REG_7

#define C3DHALL4_REG_7 0x07

◆ C3DHALL4_REG_ADC_DATATH

#define C3DHALL4_REG_ADC_DATATH 0x47

◆ C3DHALL4_REG_ADC_DATATL

#define C3DHALL4_REG_ADC_DATATL 0x46

◆ C3DHALL4_REG_ADC_DATAXH

#define C3DHALL4_REG_ADC_DATAXH 0x41

◆ C3DHALL4_REG_ADC_DATAXL

#define C3DHALL4_REG_ADC_DATAXL 0x40

◆ C3DHALL4_REG_ADC_DATAYH

#define C3DHALL4_REG_ADC_DATAYH 0x45

◆ C3DHALL4_REG_ADC_DATAYL

#define C3DHALL4_REG_ADC_DATAYL 0x44

◆ C3DHALL4_REG_ADC_DATAZH

#define C3DHALL4_REG_ADC_DATAZH 0x43

◆ C3DHALL4_REG_ADC_DATAZL

#define C3DHALL4_REG_ADC_DATAZL 0x42

◆ C3DHALL4_REG_CHANNEL_CTRL

#define C3DHALL4_REG_CHANNEL_CTRL 0x09

◆ C3DHALL4_REG_DAC_X

#define C3DHALL4_REG_DAC_X 0x11

◆ C3DHALL4_REG_DAC_Y

#define C3DHALL4_REG_DAC_Y 0x13

◆ C3DHALL4_REG_DAC_Z

#define C3DHALL4_REG_DAC_Z 0x12

◆ C3DHALL4_REG_G_CTRL_X

#define C3DHALL4_REG_G_CTRL_X 0x0E

◆ C3DHALL4_REG_G_CTRL_Y

#define C3DHALL4_REG_G_CTRL_Y 0x10

◆ C3DHALL4_REG_G_CTRL_Z

#define C3DHALL4_REG_G_CTRL_Z 0x0F

◆ C3DHALL4_REG_OFFSET_TC_X

#define C3DHALL4_REG_OFFSET_TC_X 0x1D

◆ C3DHALL4_REG_OFFSET_TC_Y

#define C3DHALL4_REG_OFFSET_TC_Y 0x1F

◆ C3DHALL4_REG_OFFSET_TC_Z

#define C3DHALL4_REG_OFFSET_TC_Z 0x1E

◆ C3DHALL4_REG_OFFSET_X

#define C3DHALL4_REG_OFFSET_X 0x1A

◆ C3DHALL4_REG_OFFSET_Y

#define C3DHALL4_REG_OFFSET_Y 0x1C

◆ C3DHALL4_REG_OFFSET_Z

#define C3DHALL4_REG_OFFSET_Z 0x1B

◆ C3DHALL4_REG_OSC_TRIM

#define C3DHALL4_REG_OSC_TRIM 0x0A

◆ C3DHALL4_REG_PWM_CTRL

#define C3DHALL4_REG_PWM_CTRL 0x08

◆ C3DHALL4_REG_SENS_TC_X

#define C3DHALL4_REG_SENS_TC_X 0x17

◆ C3DHALL4_REG_SENS_TC_Y

#define C3DHALL4_REG_SENS_TC_Y 0x19

◆ C3DHALL4_REG_SENS_TC_Z

#define C3DHALL4_REG_SENS_TC_Z 0x18

◆ C3DHALL4_REG_SENS_X

#define C3DHALL4_REG_SENS_X 0x14

◆ C3DHALL4_REG_SENS_Y

#define C3DHALL4_REG_SENS_Y 0x16

◆ C3DHALL4_REG_SENS_Z

#define C3DHALL4_REG_SENS_Z 0x15

◆ C3DHALL4_REG_STATUS

#define C3DHALL4_REG_STATUS 0x3F

◆ C3DHALL4_REG_THRES_X

#define C3DHALL4_REG_THRES_X 0x0B

◆ C3DHALL4_REG_THRES_Y

#define C3DHALL4_REG_THRES_Y 0x0D

◆ C3DHALL4_REG_THRES_Z

#define C3DHALL4_REG_THRES_Z 0x0C

Macros