c3dhall7 2.0.0.0
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Macros | |
#define | C3DHALL7_INT_DRDY_ENBALE 0x0001 |
#define | C3DHALL7_INT_DRDY_DISABLE 0x0000 |
#define | C3DHALL7_INT_SW_X1_ENABLE 0x0002 |
#define | C3DHALL7_INT_SW_X1_DISABLE 0x0000 |
#define | C3DHALL7_INT_SW_X2_ENABLE 0x0004 |
#define | C3DHALL7_INT_SW_X2_DISABLE 0x0000 |
#define | C3DHALL7_INT_SW_Y1_ENABLE 0x0008 |
#define | C3DHALL7_INT_SW_Y1_DISABLE 0x0000 |
#define | C3DHALL7_INT_SW_Y2_ENABLE 0x0010 |
#define | C3DHALL7_INT_SW_Y2_DISABLE 0x0000 |
#define | C3DHALL7_INT_SW_Z1_ENABLE 0x0020 |
#define | C3DHALL7_INT_SW_Z1_DISABLE 0x0000 |
#define | C3DHALL7_INT_SW_Z2_ENABLE 0x0040 |
#define | C3DHALL7_INT_SW_Z2_DISABLE 0x0000 |
#define | C3DHALL7_INT_ERROR_X_Y_ENABLE 0x0080 |
#define | C3DHALL7_INT_ERROR_X_Y_DISABLE 0x0000 |
#define | C3DHALL7_INT_ERROR_ADC_ENABLE 0x0100 |
#define | C3DHALL7_INT_ERROR_ADC_DISABLE 0x0000 |
#define | C3DHALL7_INT_INTERRUPT_ENABLE 0x0200 |
#define | C3DHALL7_INT_INTERRUPT_DISABLE 0x0000 |
#define | C3DHALL7_INT_ODINT_ENABLE 0x0400 |
#define | C3DHALL7_INT_ODINT_DISABLE 0x0000 |
#define C3DHALL7_INT_DRDY_DISABLE 0x0000 |
#define C3DHALL7_INT_DRDY_ENBALE 0x0001 |
#define C3DHALL7_INT_ERROR_ADC_DISABLE 0x0000 |
#define C3DHALL7_INT_ERROR_ADC_ENABLE 0x0100 |
#define C3DHALL7_INT_ERROR_X_Y_DISABLE 0x0000 |
#define C3DHALL7_INT_ERROR_X_Y_ENABLE 0x0080 |
#define C3DHALL7_INT_INTERRUPT_DISABLE 0x0000 |
#define C3DHALL7_INT_INTERRUPT_ENABLE 0x0200 |
#define C3DHALL7_INT_ODINT_DISABLE 0x0000 |
#define C3DHALL7_INT_ODINT_ENABLE 0x0400 |
#define C3DHALL7_INT_SW_X1_DISABLE 0x0000 |
#define C3DHALL7_INT_SW_X1_ENABLE 0x0002 |
#define C3DHALL7_INT_SW_X2_DISABLE 0x0000 |
#define C3DHALL7_INT_SW_X2_ENABLE 0x0004 |
#define C3DHALL7_INT_SW_Y1_DISABLE 0x0000 |
#define C3DHALL7_INT_SW_Y1_ENABLE 0x0008 |
#define C3DHALL7_INT_SW_Y2_DISABLE 0x0000 |
#define C3DHALL7_INT_SW_Y2_ENABLE 0x0010 |
#define C3DHALL7_INT_SW_Z1_DISABLE 0x0000 |
#define C3DHALL7_INT_SW_Z1_ENABLE 0x0020 |
#define C3DHALL7_INT_SW_Z2_DISABLE 0x0000 |
#define C3DHALL7_INT_SW_Z2_ENABLE 0x0040 |