Macros
#define	C3DHALL7_REG_DEVICE_ID 0x00

#define	C3DHALL7_REG_STATUS 0x10

#define	C3DHALL7_REG_ST_AXIS_X 0x11

#define	C3DHALL7_REG_ST_AXIS_Y 0x12

#define	C3DHALL7_REG_ST_AXIS_X_Y 0x13

#define	C3DHALL7_REG_ST_AXIS_Z 0x14

#define	C3DHALL7_REG_ST_AXIS_X_Z 0x15

#define	C3DHALL7_REG_ST_AXIS_Y_Z 0x16

#define	C3DHALL7_REG_ST_AXIS_X_Y_Z 0x17

#define	C3DHALL7_REG_STATUS_UP8 0x18

#define	C3DHALL7_REG_STUP8_AXIS_X 0x19

#define	C3DHALL7_REG_STUP8_AXIS_Y 0x1A

#define	C3DHALL7_REG_STUP8_AXIS_X_Y 0x1B

#define	C3DHALL7_REG_ST8UP_AXIS_Z 0x1C

#define	C3DHALL7_REG_STUP8_AXIS_X_Z 0x1D

#define	C3DHALL7_REG_STUP8_AXIS_Y_Z 0x1E

#define	C3DHALL7_REG_STUP8_AXIS_X_Y_Z 0x1F

#define	C3DHALL7_REG_INTERRUPT_SETTINGS 0x20

#define	C3DHALL7_REG_SENSOR_SETTINGS 0x21

#define	C3DHALL7_REG_THRESHOLD_1_AXIS_X 0x22

#define	C3DHALL7_REG_THRESHOLD_2_AXIS_X 0x23

#define	C3DHALL7_REG_THRESHOLD_1_AXIS_Y 0x24

#define	C3DHALL7_REG_THRESHOLD_2_AXIS_Y 0x25

#define	C3DHALL7_REG_THRESHOLD_1_AXIS_Z 0x26

#define	C3DHALL7_REG_THRESHOLD_2_AXIS_Z 0x27

#define	C3DHALL7_REG_SOFTWARE_RESET 0x30

#define	C3DHALL7_REG_I2C_DISABLE 0x31

Detailed Description

Macro Definition Documentation

◆ C3DHALL7_REG_DEVICE_ID

#define C3DHALL7_REG_DEVICE_ID 0x00

◆ C3DHALL7_REG_I2C_DISABLE

#define C3DHALL7_REG_I2C_DISABLE 0x31

◆ C3DHALL7_REG_INTERRUPT_SETTINGS

#define C3DHALL7_REG_INTERRUPT_SETTINGS 0x20

◆ C3DHALL7_REG_SENSOR_SETTINGS

#define C3DHALL7_REG_SENSOR_SETTINGS 0x21

◆ C3DHALL7_REG_SOFTWARE_RESET

#define C3DHALL7_REG_SOFTWARE_RESET 0x30

◆ C3DHALL7_REG_ST8UP_AXIS_Z

#define C3DHALL7_REG_ST8UP_AXIS_Z 0x1C

◆ C3DHALL7_REG_ST_AXIS_X

#define C3DHALL7_REG_ST_AXIS_X 0x11

◆ C3DHALL7_REG_ST_AXIS_X_Y

#define C3DHALL7_REG_ST_AXIS_X_Y 0x13

◆ C3DHALL7_REG_ST_AXIS_X_Y_Z

#define C3DHALL7_REG_ST_AXIS_X_Y_Z 0x17

◆ C3DHALL7_REG_ST_AXIS_X_Z

#define C3DHALL7_REG_ST_AXIS_X_Z 0x15

◆ C3DHALL7_REG_ST_AXIS_Y

#define C3DHALL7_REG_ST_AXIS_Y 0x12

◆ C3DHALL7_REG_ST_AXIS_Y_Z

#define C3DHALL7_REG_ST_AXIS_Y_Z 0x16

◆ C3DHALL7_REG_ST_AXIS_Z

#define C3DHALL7_REG_ST_AXIS_Z 0x14

◆ C3DHALL7_REG_STATUS

#define C3DHALL7_REG_STATUS 0x10

◆ C3DHALL7_REG_STATUS_UP8

#define C3DHALL7_REG_STATUS_UP8 0x18

◆ C3DHALL7_REG_STUP8_AXIS_X

#define C3DHALL7_REG_STUP8_AXIS_X 0x19

◆ C3DHALL7_REG_STUP8_AXIS_X_Y

#define C3DHALL7_REG_STUP8_AXIS_X_Y 0x1B

◆ C3DHALL7_REG_STUP8_AXIS_X_Y_Z

#define C3DHALL7_REG_STUP8_AXIS_X_Y_Z 0x1F

◆ C3DHALL7_REG_STUP8_AXIS_X_Z

#define C3DHALL7_REG_STUP8_AXIS_X_Z 0x1D

◆ C3DHALL7_REG_STUP8_AXIS_Y

#define C3DHALL7_REG_STUP8_AXIS_Y 0x1A

◆ C3DHALL7_REG_STUP8_AXIS_Y_Z

#define C3DHALL7_REG_STUP8_AXIS_Y_Z 0x1E

◆ C3DHALL7_REG_THRESHOLD_1_AXIS_X

#define C3DHALL7_REG_THRESHOLD_1_AXIS_X 0x22

◆ C3DHALL7_REG_THRESHOLD_1_AXIS_Y

#define C3DHALL7_REG_THRESHOLD_1_AXIS_Y 0x24

◆ C3DHALL7_REG_THRESHOLD_1_AXIS_Z

#define C3DHALL7_REG_THRESHOLD_1_AXIS_Z 0x26

◆ C3DHALL7_REG_THRESHOLD_2_AXIS_X

#define C3DHALL7_REG_THRESHOLD_2_AXIS_X 0x23

◆ C3DHALL7_REG_THRESHOLD_2_AXIS_Y

#define C3DHALL7_REG_THRESHOLD_2_AXIS_Y 0x25

◆ C3DHALL7_REG_THRESHOLD_2_AXIS_Z

#define C3DHALL7_REG_THRESHOLD_2_AXIS_Z 0x27

Macros