c6dofimu11 2.0.0.0
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#define C6DOFIMU11_AMI_CNTL3_AMI_EN_MASK 0x80 |
#define C6DOFIMU11_AMI_CNTL3_OAMI_MASK 0x07 |
#define C6DOFIMU11_BUF_CTRL_1_SMT_TH_MASK 0xFF |
#define C6DOFIMU11_BUF_CTRL_2_BUF_M_FIFO 0x00 |
#define C6DOFIMU11_BUF_CTRL_2_BUF_M_FILO 0x03 |
#define C6DOFIMU11_BUF_CTRL_2_BUF_M_MASK 0x06 |
#define C6DOFIMU11_BUF_CTRL_2_BUF_M_STREAM 0x02 |
#define C6DOFIMU11_BUF_CTRL_2_BUF_M_TRIGGER 0x04 |
#define C6DOFIMU11_BUF_CTRL_2_SMT_TH8 0x01 |
#define C6DOFIMU11_BUF_CTRL_3_BFI_EN_DISABLED 0x00 |
#define C6DOFIMU11_BUF_CTRL_3_BFI_EN_ENABLED 0x80 |
#define C6DOFIMU11_BUF_CTRL_3_BUF_AX_DISABLED 0x00 |
#define C6DOFIMU11_BUF_CTRL_3_BUF_AX_ENABLED 0x40 |
#define C6DOFIMU11_BUF_CTRL_3_BUF_AY_DISABLED 0x00 |
#define C6DOFIMU11_BUF_CTRL_3_BUF_AY_ENABLED 0x20 |
#define C6DOFIMU11_BUF_CTRL_3_BUF_AZ_DISABLED 0x00 |
#define C6DOFIMU11_BUF_CTRL_3_BUF_AZ_ENABLED 0x10 |
#define C6DOFIMU11_BUF_CTRL_3_BUF_MX_DISABLED 0x00 |
#define C6DOFIMU11_BUF_CTRL_3_BUF_MX_ENABLED 0x08 |
#define C6DOFIMU11_BUF_CTRL_3_BUF_MY_DISABLED 0x00 |
#define C6DOFIMU11_BUF_CTRL_3_BUF_MY_ENABLED 0x04 |
#define C6DOFIMU11_BUF_CTRL_3_BUF_MZ_DISABLED 0x00 |
#define C6DOFIMU11_BUF_CTRL_3_BUF_MZ_ENABLED 0x02 |
#define C6DOFIMU11_BUF_CTRL_3_BUF_TEMP_DISABLED 0x00 |
#define C6DOFIMU11_BUF_CTRL_3_BUF_TEMP_ENABLED 0x01 |
#define C6DOFIMU11_BUF_STATUS_2_BUF_TRIG 0x02 |
#define C6DOFIMU11_BUF_STATUS_2_SMP_LEV_H 0x01 |
#define C6DOFIMU11_CNTL1_STEN_MASK 0x40 |
#define C6DOFIMU11_CNTL2_ACCEL_DISABLE 0x00 |
#define C6DOFIMU11_CNTL2_ACCEL_EN_MASK 0x01 |
#define C6DOFIMU11_CNTL2_ACCEL_EN_OPERATING_MODE 0x01 |
#define C6DOFIMU11_CNTL2_ACCEL_EN_STANDBY_MODE 0x00 |
#define C6DOFIMU11_CNTL2_ACCEL_ENABLE 0x01 |
#define C6DOFIMU11_CNTL2_GSEL_16G 0x10 |
#define C6DOFIMU11_CNTL2_GSEL_32G 0x20 |
#define C6DOFIMU11_CNTL2_GSEL_64G 0x30 |
#define C6DOFIMU11_CNTL2_GSEL_8G 0x00 |
#define C6DOFIMU11_CNTL2_GSEL_MASK 0x30 |
#define C6DOFIMU11_CNTL2_MAG_DISABLE 0x00 |
#define C6DOFIMU11_CNTL2_MAG_EN_MASK 0x02 |
#define C6DOFIMU11_CNTL2_MAG_EN_OPERATING_MODE 0x02 |
#define C6DOFIMU11_CNTL2_MAG_EN_STANDBY_MODE 0x00 |
#define C6DOFIMU11_CNTL2_MAG_ENABLE 0x01 |
#define C6DOFIMU11_CNTL2_RES_A32M16 0x04 |
#define C6DOFIMU11_CNTL2_RES_A4M2 0x00 |
#define C6DOFIMU11_CNTL2_RES_MASK 0x0C |
#define C6DOFIMU11_CNTL2_RES_MAX1 0x08 |
#define C6DOFIMU11_CNTL2_RES_MAX2 0x0C |
#define C6DOFIMU11_CNTL2_TEMP_EN_MASK 0x40 |
#define C6DOFIMU11_CNTL2_TEMP_EN_OPERATING_MODE 0x40 |
#define C6DOFIMU11_CNTL2_TEMP_EN_STANDBY_MODE 0x00 |
#define C6DOFIMU11_CNTL2_TEMPERATURE_DISABLE 0x00 |
#define C6DOFIMU11_CNTL2_TEMPERATURE_ENABLE 0x01 |
#define C6DOFIMU11_COTR_TEST_RESP_DEFAULT 0x55 |
#define C6DOFIMU11_COTR_TEST_RESP_MASK 0xFF |
#define C6DOFIMU11_COTR_TEST_RESP_TEST 0xAA |
#define C6DOFIMU11_FFI_CNTL3_FFI_EN_MASK 0x80 |
#define C6DOFIMU11_FFI_CNTL3_OFFI_MASK 0x07 |
#define C6DOFIMU11_INC3_IEA1_MASK 0x04 |
#define C6DOFIMU11_INC3_IEA2_MASK 0x40 |
#define C6DOFIMU11_INC3_IED1_MASK 0x08 |
#define C6DOFIMU11_INC3_IED2_MASK 0x80 |
#define C6DOFIMU11_INC3_IEL1_MASK 0x03 |
#define C6DOFIMU11_INC3_IEL2_MASK 0x30 |
#define C6DOFIMU11_INS1_AMI_MASK 0x02 |
#define C6DOFIMU11_INS1_BFI_MASK 0x40 |
#define C6DOFIMU11_INS1_DRDY_A_MASK 0x10 |
#define C6DOFIMU11_INS1_DRDY_M_MASK 0x08 |
#define C6DOFIMU11_INS1_FFI_MASK 0x04 |
#define C6DOFIMU11_INS1_INT_MASK 0x80 |
#define C6DOFIMU11_INS1_MMI_MASK 0x01 |
#define C6DOFIMU11_INS1_WMI_MASK 0x20 |
#define C6DOFIMU11_MMI_CNTL3_MMI_EN_MASK 0x80 |
#define C6DOFIMU11_MMI_CNTL3_OMMI_MASK 0x07 |
#define C6DOFIMU11_ODCNTL_OSA_MASK 0x0F |
#define C6DOFIMU11_ODCNTL_OSM_MASK 0xF0 |
#define C6DOFIMU11_WHO_AM_I_WIA_MASK 0xFF |