c6dofimu14 2.0.0.0
6DOF IMU 14 Registers Settings

Settings for registers of 6DOF IMU 14 Click driver. More...

Macros

#define C6DOFIMU14_SPR_DMP_INIT_EN   0x40
 6DOF IMU 14 Signal path reset register settings.
 
#define C6DOFIMU14_SPR_DMP_MEM_RST_EN   0x20
 
#define C6DOFIMU14_SPR_ABORT_AND_RESET   0x08
 
#define C6DOFIMU14_SPR_TMST_STROBE   0x04
 
#define C6DOFIMU14_SPR_FIFO_FLUSH   0x02
 
#define C6DOFIMU14_INTF0_FIFO_HOLD_LAST_DATA_EN   0x80
 6DOF IMU 14 INTF config 0 register settings.
 
#define C6DOFIMU14_INTF0_FIFO_HOLD_LAST_DATA_DIS   0x00
 
#define C6DOFIMU14_INTF0_FIFO_COUNT_REC_0   0x00
 
#define C6DOFIMU14_INTF0_FIFO_COUNT_REC_1   0x40
 
#define C6DOFIMU14_INTF0_FIFO_COUNT_ENDIAN_0   0x00
 
#define C6DOFIMU14_INTF0_FIFO_COUNT_ENDIAN_1   0x20
 
#define C6DOFIMU14_INTF0_SENSOR_DATA_ENDIAN_0   0x00
 
#define C6DOFIMU14_INTF0_SENSOR_DATA_ENDIAN_1   0x10
 
#define C6DOFIMU14_INTF0_UI_SIFS_CFG_DISABLE_SPI   0x00
 
#define C6DOFIMU14_INTF0_UI_SIFS_CFG_DISABLE_I2C   0x01
 
#define C6DOFIMU14_INTF1_ACLP_CLK_SEL_WAKEUP_CLK   0x00
 6DOF IMU 14 INTF config 1 register settings.
 
#define C6DOFIMU14_INTF1_ACLP_CLK_SEL_RC_CLK   0x08
 
#define C6DOFIMU14_INTF1_RTC_MODE_NO_INPUT   0x00
 
#define C6DOFIMU14_INTF1_RTC_MODE_INPUT   0x04
 
#define C6DOFIMU14_INTF1_CLKSEL_RC_OS   0x00
 
#define C6DOFIMU14_INTF1_CLKSEL_PLL_RC_OS   0x01
 
#define C6DOFIMU14_INTF1_CLKSEL_DISABLE_ALL_OS   0x11
 
#define C6DOFIMU14_PWR_TEMP_ENABLE   0x00
 6DOF IMU 14 PWR-MEGMT0 register settings.
 
#define C6DOFIMU14_PWR_TEMP_DISABLE   0x20
 
#define C6DOFIMU14_PWR_IDLE_1   0x10
 
#define C6DOFIMU14_PWR_IDLE_0   0x00
 
#define C6DOFIMU14_PWR_GYRO_MODE_OFF   0x00
 
#define C6DOFIMU14_PWR_GYRO_MODE_STAND_BY   0x04
 
#define C6DOFIMU14_PWR_GYRO_MODE_LOW_NOISE   0x0C
 
#define C6DOFIMU14_PWR_ACCEL_MODE_OFF   0x00
 
#define C6DOFIMU14_PWR_ACCEL_MODE_LOW_POWER   0x02
 
#define C6DOFIMU14_PWR_ACCEL_MODE_LOW_NOISE   0x03
 
#define C6DOFIMU14_GCFG0_FS_SEL_2000DPS   0x00
 6DOF IMU 14 GYRO CONFIG 0 register settings.
 
#define C6DOFIMU14_GCFG0_FS_SEL_1000DPS   0x20
 
#define C6DOFIMU14_GCFG0_FS_SEL_500DPS   0x40
 
#define C6DOFIMU14_GCFG0_FS_SEL_250DPS   0x60
 
#define C6DOFIMU14_GCFG0_FS_SEL_125DPS   0x80
 
#define C6DOFIMU14_GCFG0_FS_SEL_62p5DPS   0xA0
 
#define C6DOFIMU14_GCFG0_FS_SEL_31p25DPS   0xC0
 
#define C6DOFIMU14_GCFG0_FS_SEL_15p625DPS   0xE0
 
#define C6DOFIMU14_GCFG0_ODR_32KHZ   0x01
 
#define C6DOFIMU14_GCFG0_ODR_16KHZ   0x02
 
#define C6DOFIMU14_GCFG0_ODR_8KHZ   0x03
 
#define C6DOFIMU14_GCFG0_ODR_4KHZ   0x04
 
#define C6DOFIMU14_GCFG0_ODR_2KHZ   0x05
 
#define C6DOFIMU14_GCFG0_ODR_1KHZ   0x06
 
#define C6DOFIMU14_GCFG0_ODR_200HZ   0x07
 
#define C6DOFIMU14_GCFG0_ODR_100HZ   0x08
 
#define C6DOFIMU14_GCFG0_ODR_50HZ   0x09
 
#define C6DOFIMU14_GCFG0_ODR_25HZ   0x0A
 
#define C6DOFIMU14_GCFG0_ODR_12p5HZ   0x0B
 
#define C6DOFIMU14_GCFG0_ODR_500HZ   0x0F
 
#define C6DOFIMU14_ACFG0_FS_SEL_16G   0x00
 6DOF IMU 14 ACCEL CONFIG 0 register settings.
 
#define C6DOFIMU14_ACFG0_FS_SEL_8G   0x20
 
#define C6DOFIMU14_ACFG0_FS_SEL_4G   0x40
 
#define C6DOFIMU14_ACFG0_FS_SEL_2G   0x60
 
#define C6DOFIMU14_ACFG0_ODR_32KHZ   0x01
 
#define C6DOFIMU14_ACFG0_ODR_16KHZ   0x02
 
#define C6DOFIMU14_ACFG0_ODR_8KHZ   0x03
 
#define C6DOFIMU14_ACFG0_ODR_4KHZ   0x04
 
#define C6DOFIMU14_ACFG0_ODR_2KHZ   0x05
 
#define C6DOFIMU14_ACFG0_ODR_1KHZ   0x06
 
#define C6DOFIMU14_ACFG0_ODR_200HZ   0x07
 
#define C6DOFIMU14_ACFG0_ODR_100HZ   0x08
 
#define C6DOFIMU14_ACFG0_ODR_50HZ   0x09
 
#define C6DOFIMU14_ACFG0_ODR_25HZ   0x0A
 
#define C6DOFIMU14_ACFG0_ODR_12p5HZ   0x0B
 
#define C6DOFIMU14_ACFG0_ODR_6p25HZ   0x0C
 
#define C6DOFIMU14_ACFG0_ODR_3p125HZ   0x0D
 
#define C6DOFIMU14_ACFG0_ODR_1p562HZ   0x0E
 
#define C6DOFIMU14_ACFG0_ODR_500HZ   0x0F
 
#define C6DOFIMU14_GCFG1_FILT_BW_4000HZ   0x00
 6DOF IMU 14 GYRO CONFIG 1 register settings.
 
#define C6DOFIMU14_GCFG1_FILT_BW_170HZ   0x20
 
#define C6DOFIMU14_GCFG1_FILT_BW_82HZ   0x40
 
#define C6DOFIMU14_GCFG1_FILT_BW_40HZ   0x60
 
#define C6DOFIMU14_GCFG1_FILT_BW_20HZ   0x80
 
#define C6DOFIMU14_GCFG1_FILT_BW_10HZ   0xA0
 
#define C6DOFIMU14_GCFG1_FILT_BW_5HZ   0xC0
 
#define C6DOFIMU14_GCFG1_UI_FILT_ORD_1ST_OTHER   0x00
 
#define C6DOFIMU14_GCFG1_UI_FILT_ORD_2ND_OTHER   0x04
 
#define C6DOFIMU14_GCFG1_UI_FILT_ORD_3RD_OTHER   0x08
 
#define C6DOFIMU14_GCFG1_DEC2_M2_ORD_3RD_OTHER   0x02
 
#define C6DOFIMU14_GACFG0_AC_UI_BW_ODR_2   0x00
 6DOF IMU 14 GYRO ACCEL CONFIG 0 register settings.
 
#define C6DOFIMU14_GACFG0_AC_UI_BW_ODR_4   0x10
 
#define C6DOFIMU14_GACFG0_AC_UI_BW_ODR_5   0x20
 
#define C6DOFIMU14_GACFG0_AC_UI_BW_ODR_8   0x30
 
#define C6DOFIMU14_GACFG0_AC_UI_BW_ODR_10   0x40
 
#define C6DOFIMU14_GACFG0_AC_UI_BW_ODR_16   0x50
 
#define C6DOFIMU14_GACFG0_AC_UI_BW_ODR_20   0x60
 
#define C6DOFIMU14_GACFG0_AC_UI_BW_ODR_40   0x70
 
#define C6DOFIMU14_GACFG0_GY_UI_BW_ODR_2   0x00
 
#define C6DOFIMU14_GACFG0_GY_UI_BW_ODR_4   0x01
 
#define C6DOFIMU14_GACFG0_GY_UI_BW_ODR_5   0x02
 
#define C6DOFIMU14_GACFG0_GY_UI_BW_ODR_8   0x03
 
#define C6DOFIMU14_GACFG0_GY_UI_BW_ODR_10   0x04
 
#define C6DOFIMU14_GACFG0_GY_UI_BW_ODR_16   0x05
 
#define C6DOFIMU14_GACFG0_GY_UI_BW_ODR_20   0x06
 
#define C6DOFIMU14_GACFG0_GY_UI_BW_ODR_40   0x07
 
#define C6DOFIMU14_ACFG1_UI_FILT_ORD_1ST_OTHER   0x00
 6DOF IMU 14 ACCEL CONFIG 1 register settings.
 
#define C6DOFIMU14_ACFG1_UI_FILT_ORD_2ND_OTHER   0x04
 
#define C6DOFIMU14_ACFG1_UI_FILT_ORD_3RD_OTHER   0x08
 
#define C6DOFIMU14_ACFG1_DEC2_M2_ORD_3RD_OTHER   0x02
 
#define C6DOFIMU14_TMSTCFG_TO_REGS_EN   0x10
 6DOF IMU 14 TMST CONFIG register settings.
 
#define C6DOFIMU14_TMSTCFG_TO_REGS_DIS   0x00
 
#define C6DOFIMU14_TMSTCFG_RES_0   0x00
 
#define C6DOFIMU14_TMSTCFG_RES_1   0x08
 
#define C6DOFIMU14_TMSTCFG_DELTA_EN   0x04
 
#define C6DOFIMU14_TMSTCFG_DELTA_DIS   0x00
 
#define C6DOFIMU14_TMSTCFG_FSYNC_EN   0x02
 
#define C6DOFIMU14_TMSTCFG_FSYNC_DIS   0x00
 
#define C6DOFIMU14_TMSTCFG_TMST_ENABLE   0x01
 
#define C6DOFIMU14_TMSTCFG_TMST_DISABLE   0x00
 
#define C6DOFIMU14_APEXCFG0_DMP_NOT_ACTIVE   0x00
 6DOF IMU 14 APEX CONFIG 0 register settings.
 
#define C6DOFIMU14_APEXCFG0_DMP_ACTIVE   0x80
 
#define C6DOFIMU14_APEXCFG0_TAP_ENABLE   0x40
 
#define C6DOFIMU14_APEXCFG0_TAP_DISABLE   0x00
 
#define C6DOFIMU14_APEXCFG0_PED_ENABLE   0x20
 
#define C6DOFIMU14_APEXCFG0_PED_DISABLE   0x00
 
#define C6DOFIMU14_APEXCFG0_TILT_ENABLE   0x10
 
#define C6DOFIMU14_APEXCFG0_TILT_DISABLE   0x00
 
#define C6DOFIMU14_APEXCFG0_R2W_EMABLE   0x08
 
#define C6DOFIMU14_APEXCFG0_R2W_DISABLE   0x00
 
#define C6DOFIMU14_APEXCFG0_DMP_ODR_25HZ   0x00
 
#define C6DOFIMU14_APEXCFG0_DMP_ODR_50HZ   0x03
 
#define C6DOFIMU14_SMDCFG_WOM_INT_MODE_0   0x00
 6DOF IMU 14 SMD CONFIG register settings.
 
#define C6DOFIMU14_SMDCFG_WOM_INT_MODE_1   0x08
 
#define C6DOFIMU14_SMDCFG_WOM_MODE_0   0x00
 
#define C6DOFIMU14_SMDCFG_WOM_MODE_1   0x04
 
#define C6DOFIMU14_SMDCFG_SMD_MODE_DISABLE   0x00
 
#define C6DOFIMU14_SMDCFG_SMD_MODE_SHORT   0x02
 
#define C6DOFIMU14_SMDCFG_SMD_MODE_LONG   0x03
 
#define C6DOFIMU14_ISRC0_UI_FSYNC_INT1_EN   0x40
 6DOF IMU 14 INT SOURCE 0 register settings.
 
#define C6DOFIMU14_ISRC0_UI_FSYNC_INT1_DIS   0x00
 
#define C6DOFIMU14_ISRC0_PLL_RDY_INT1_EN   0x20
 
#define C6DOFIMU14_ISRC0_PLL_RDY_INT1_DIS   0x00
 
#define C6DOFIMU14_ISRC0_RESET_DONE_INT1_EN   0x10
 
#define C6DOFIMU14_ISRC0_RESET_DONE_INT1_DIS   0x00
 
#define C6DOFIMU14_ISRC0_UI_DRDY_INT1_EN   0x08
 
#define C6DOFIMU14_ISRC0_UI_DRDY_INT1_DIS   0x00
 
#define C6DOFIMU14_ISRC0_FIFO_THS_INT1_EN   0x04
 
#define C6DOFIMU14_ISRC0_FIFO_THS_INT1_DIS   0x00
 
#define C6DOFIMU14_ISRC0_FIFO_FULL_INT1_EN   0x02
 
#define C6DOFIMU14_ISRC0_FIFO_FULL_INT1_DIS   0x00
 
#define C6DOFIMU14_ISRC0_UI_AGC_RDY_INT1_EN   0x01
 
#define C6DOFIMU14_ISRC0_UI_AGC_RDY_INT1_DIS   0x00
 
#define C6DOFIMU14_DEF_WHO_AM_I   0x47
 6DOF IMU 14 WHO AM I register settings.
 
#define C6DOFIMU14_BANK_0   0x00
 6DOF IMU 14 REG BANK SELECT register settings.
 
#define C6DOFIMU14_BANK_1   0x01
 
#define C6DOFIMU14_BANK_2   0x02
 
#define C6DOFIMU14_BANK_3   0x03
 
#define C6DOFIMU14_BANK_4   0x04
 
#define C6DOFIMU14_SENSOR_CFG_GYRO_Z_EN   0x00
 6DOF IMU 14 SENSOR CONFIG 0 register settings.
 
#define C6DOFIMU14_SENSOR_CFG_GYRO_Z_DIS   0x20
 
#define C6DOFIMU14_SENSOR_CFG_GYRO_Y_EN   0x00
 
#define C6DOFIMU14_SENSOR_CFG_GYRO_Y_DIS   0x10
 
#define C6DOFIMU14_SENSOR_CFG_GYRO_X_EN   0x00
 
#define C6DOFIMU14_SENSOR_CFG_GYRO_X_DIS   0x08
 
#define C6DOFIMU14_SENSOR_CFG_ACCEL_Z_EN   0x00
 
#define C6DOFIMU14_SENSOR_CFG_ACCEL_Z_DIS   0x04
 
#define C6DOFIMU14_SENSOR_CFG_ACCEL_Y_EN   0x00
 
#define C6DOFIMU14_SENSOR_CFG_ACCEL_Y_DIS   0x02
 
#define C6DOFIMU14_SENSOR_CFG_ACCEL_X_EN   0x00
 
#define C6DOFIMU14_SENSOR_CFG_ACCEL_X_DIS   0x01
 
#define C6DOFIMU14_APEX_CFG1_LOW_ENERGY_SEL   0xA0
 6DOF IMU 14 APEX CONFIG 1 register settings.
 
#define C6DOFIMU14_APEX_CFG1_TIME_SEL_0SEC   0x00
 
#define C6DOFIMU14_APEX_CFG1_TIME_SEL_4SEC   0x01
 
#define C6DOFIMU14_APEX_CFG1_TIME_SEL_8SEC   0x02
 
#define C6DOFIMU14_APEX_CFG1_TIME_SEL_12SEC   0x03
 
#define C6DOFIMU14_APEX_CFG1_TIME_SEL_16SEC   0x04
 
#define C6DOFIMU14_APEX_CFG1_TIME_SEL_20SEC   0x05
 
#define C6DOFIMU14_APEX_CFG1_TIME_SEL_24SEC   0x06
 
#define C6DOFIMU14_APEX_CFG1_TIME_SEL_28SEC   0x07
 
#define C6DOFIMU14_APEX_CFG1_TIME_SEL_32SEC   0x08
 
#define C6DOFIMU14_APEX_CFG1_TIME_SEL_36SEC   0x09
 
#define C6DOFIMU14_APEX_CFG1_TIME_SEL_40SEC   0x0A
 
#define C6DOFIMU14_APEX_CFG1_TIME_SEL_44SEC   0x0B
 
#define C6DOFIMU14_APEX_CFG1_TIME_SEL_48SEC   0x0C
 
#define C6DOFIMU14_APEX_CFG1_TIME_SEL_52SEC   0x0D
 
#define C6DOFIMU14_APEX_CFG1_TIME_SEL_56SEC   0x0E
 
#define C6DOFIMU14_APEX_CFG1_TIME_SEL_60SEC   0x0F
 
#define C6DOFIMU14_APEX_CFG2_PED_AMP_TH_SEL   0x80
 6DOF IMU 14 APEX CONFIG 2 register settings.
 
#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_0   0x00
 
#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_1   0x01
 
#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_2   0x02
 
#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_3   0x03
 
#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_4   0x04
 
#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_5   0x05
 
#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_6   0x06
 
#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_7   0x07
 
#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_8   0x08
 
#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_9   0x09
 
#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_10   0x0A
 
#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_11   0x0B
 
#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_12   0x0C
 
#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_13   0x0D
 
#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_14   0x0E
 
#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_15   0x0F
 
#define C6DOFIMU14_APEX_CFG3_STEP_DET_SEL_0   0x00
 6DOF IMU 14 APEX CONFIG 3 register settings.
 
#define C6DOFIMU14_APEX_CFG3_STEP_DET_SEL_1   0x20
 
#define C6DOFIMU14_APEX_CFG3_STEP_DET_SEL_2   0x40
 
#define C6DOFIMU14_APEX_CFG3_STEP_DET_SEL_3   0x60
 
#define C6DOFIMU14_APEX_CFG3_STEP_DET_SEL_4   0x80
 
#define C6DOFIMU14_APEX_CFG3_STEP_DET_SEL_5   0xA0
 
#define C6DOFIMU14_APEX_CFG3_STEP_DET_SEL_6   0xC0
 
#define C6DOFIMU14_APEX_CFG3_STEP_DET_SEL_7   0xE0
 
#define C6DOFIMU14_APEX_CFG3_TIMER_SEL_0   0x00
 
#define C6DOFIMU14_APEX_CFG3_TIMER_SEL_1   0x04
 
#define C6DOFIMU14_APEX_CFG3_TIMER_SEL_2   0x08
 
#define C6DOFIMU14_APEX_CFG3_TIMER_SEL_3   0x0C
 
#define C6DOFIMU14_APEX_CFG3_TIMER_SEL_4   0x10
 
#define C6DOFIMU14_APEX_CFG3_TIMER_SEL_5   0x14
 
#define C6DOFIMU14_APEX_CFG3_TIMER_SEL_6   0x18
 
#define C6DOFIMU14_APEX_CFG3_TIMER_SEL_7   0x1C
 
#define C6DOFIMU14_APEX_CFG3_HI_EN_TH_SEL   0x01
 
#define C6DOFIMU14_APEX_CFG4_TILT_WAIT_SEL_0S   0x00
 6DOF IMU 14 APEX CONFIG 4 register settings.
 
#define C6DOFIMU14_APEX_CFG4_TILT_WAIT_SEL_2S   0x40
 
#define C6DOFIMU14_APEX_CFG4_TILT_WAIT_SEL_4S   0x80
 
#define C6DOFIMU14_APEX_CFG4_TILT_WAIT_SEL_6S   0xC0
 
#define C6DOFIMU14_APEX_CFG4_TILT_SLEEP_TIME_1p28SEC   0x00
 
#define C6DOFIMU14_APEX_CFG4_TILT_SLEEP_TIME_2p56SEC   0x08
 
#define C6DOFIMU14_APEX_CFG4_TILT_SLEEP_TIME_3p84SEC   0x10
 
#define C6DOFIMU14_APEX_CFG4_TILT_SLEEP_TIME_5p12SEC   0x18
 
#define C6DOFIMU14_APEX_CFG4_TILT_SLEEP_TIME_6p40SEC   0x20
 
#define C6DOFIMU14_APEX_CFG4_TILT_SLEEP_TIME_7p68SEC   0x28
 
#define C6DOFIMU14_APEX_CFG4_TILT_SLEEP_TIME_8p96SEC   0x30
 
#define C6DOFIMU14_APEX_CFG4_TILT_SLEEP_TIME_10p24SEC   0x38
 
#define C6DOFIMU14_INTSRC6_STEP_DET_INT1_EN   0x20
 6DOF IMU 14 INT SOURCE 6 register settings.
 
#define C6DOFIMU14_INTSRC6_STEP_DET_INT1_DIS   0x00
 
#define C6DOFIMU14_INTSRC6_STEP_CNT_OFL_INT1_EN   0x10
 
#define C6DOFIMU14_INTSRC6_STEP_CNT_OFL_INT1_DIS   0x00
 
#define C6DOFIMU14_INTSRC6_TILT_DET_INT1_EN   0x08
 
#define C6DOFIMU14_INTSRC6_TILT_DET_INT1_DIS   0x00
 
#define C6DOFIMU14_INTSRC6_WAKE_DET_INT1_EN   0x04
 
#define C6DOFIMU14_INTSRC6_WAKE_DET_INT1_DIS   0x00
 
#define C6DOFIMU14_INTSRC6_SLEEP_DET_INT1_EN   0x02
 
#define C6DOFIMU14_INTSRC6_SLEEP_DET_INT1_DIS   0x00
 
#define C6DOFIMU14_INTSRC6_TAP_DET_INT1_EN   0x01
 
#define C6DOFIMU14_INTSRC6_TAP_DET_INT1_DIS   0x00
 
#define C6DOFIMU14_INTSRC7_STEP_DET_INT2_EN   0x20
 6DOF IMU 14 INT SOURCE 7 register settings.
 
#define C6DOFIMU14_INTSRC7_STEP_DET_INT2_DIS   0x00
 
#define C6DOFIMU14_INTSRC7_STEP_CNT_OFL_INT2_EN   0x10
 
#define C6DOFIMU14_INTSRC7_STEP_CNT_OFL_INT2_DIS   0x00
 
#define C6DOFIMU14_INTSRC7_TILT_DET_INT2_EN   0x08
 
#define C6DOFIMU14_INTSRC7_TILT_DET_INT2_DIS   0x00
 
#define C6DOFIMU14_INTSRC7_WAKE_DET_INT2_EN   0x04
 
#define C6DOFIMU14_INTSRC7_WAKE_DET_INT2_DIS   0x00
 
#define C6DOFIMU14_INTSRC7_SLEEP_DET_INT2_EN   0x02
 
#define C6DOFIMU14_INTSRC7_SLEEP_DET_INT2_DIS   0x00
 
#define C6DOFIMU14_INTSRC7_TAP_DET_INT2_EN   0x01
 
#define C6DOFIMU14_INTSRC7_TAP_DET_INT2_DIS   0x00
 
#define C6DOFIMU14_DEVCONFIG_SPI_MODE_03   0x00
 6DOF IMU 14 DEVICE CONFIG register settings.
 
#define C6DOFIMU14_DEVCONFIG_SPI_MODE_12   0x10
 
#define C6DOFIMU14_DEVCONFIG_SOFT_RESET_NORMAL   0x00
 
#define C6DOFIMU14_DEVCONFIG_SOFT_RESET_ENABLE   0x01
 
#define C6DOFIMU14_DRIVECONFIG_MAX_SLEW_RATE   0x55
 6DOF IMU 14 DRIVE CONFIG register settings.
 
#define C6DOFIMU14_DRIVECONFIG_MIN_SLEW_RATE   0x00
 
#define C6DOFIMU14_FIFOCONFIG_BYPASS_MODE   0x00
 6DOF IMU 14 FIFO CONFIG register settings.
 
#define C6DOFIMU14_FIFOCONFIG_STREAM_TO_FIFO_MODE   0x40
 
#define C6DOFIMU14_FIFOCONFIG_STOP_ON_FULL_MODE   0x80
 
#define C6DOFIMU14_FIFOCONFIG1_RESUME_PARTIAL_RD   0x40
 6DOF IMU 14 FIFO CONFIG 1 register settings.
 
#define C6DOFIMU14_FIFOCONFIG1_HIRES_EN   0x10
 
#define C6DOFIMU14_FIFOCONFIG1_TMST_FSYNC_EN   0x08
 
#define C6DOFIMU14_FIFOCONFIG1_TEMP_EN   0x04
 
#define C6DOFIMU14_FIFOCONFIG1_GYRO_EN   0x02
 
#define C6DOFIMU14_FIFOCONFIG1_ACCEL_EN   0x01
 
#define C6DOFIMU14_INTSTATUS_UI_FSYNC   0x40
 6DOF IMU 14 INT STATUS register settings.
 
#define C6DOFIMU14_INTSTATUS_PLL_RDY   0x20
 
#define C6DOFIMU14_INTSTATUS_RESET_DONE   0x10
 
#define C6DOFIMU14_INTSTATUS_DATA_RDY   0x08
 
#define C6DOFIMU14_INTSTATUS_FIFO_THS   0x04
 
#define C6DOFIMU14_INTSTATUS_FIFO_FULL   0x02
 
#define C6DOFIMU14_INTSTATUS_AGC_RDY   0x01
 
#define C6DOFIMU14_FIFOHEADER_MSG   0x80
 6DOF IMU 14 FIFO HEADER byte settings.
 
#define C6DOFIMU14_FIFOHEADER_ACCEL   0x40
 
#define C6DOFIMU14_FIFOHEADER_GYRO   0x20
 
#define C6DOFIMU14_FIFOHEADER_20   0x10
 
#define C6DOFIMU14_FIFOHEADER_TIMESTAMP_ODR   0x08
 
#define C6DOFIMU14_FIFOHEADER_ODR_ACCEL   0x02
 
#define C6DOFIMU14_FIFOHEADER_ODR_GYRO   0x01
 
#define C6DOFIMU14_SPI_READ_MASK   0x80
 6DOF IMU 14 SPI read/write bit settings.
 
#define C6DOFIMU14_SPI_WRITE_MASK   0x7F
 
#define C6DOFIMU14_SET_DEV_ADDR_GND   0x68
 6DOF IMU 14 device address setting.
 
#define C6DOFIMU14_SET_DEV_ADDR_VCC   0x69
 

Detailed Description

Settings for registers of 6DOF IMU 14 Click driver.

Macro Definition Documentation

◆ C6DOFIMU14_ACFG0_FS_SEL_16G

#define C6DOFIMU14_ACFG0_FS_SEL_16G   0x00

6DOF IMU 14 ACCEL CONFIG 0 register settings.

ACCEL CONFIG 0 register setting flags ( Default - 0x06 ).

◆ C6DOFIMU14_ACFG0_FS_SEL_2G

#define C6DOFIMU14_ACFG0_FS_SEL_2G   0x60

◆ C6DOFIMU14_ACFG0_FS_SEL_4G

#define C6DOFIMU14_ACFG0_FS_SEL_4G   0x40

◆ C6DOFIMU14_ACFG0_FS_SEL_8G

#define C6DOFIMU14_ACFG0_FS_SEL_8G   0x20

◆ C6DOFIMU14_ACFG0_ODR_100HZ

#define C6DOFIMU14_ACFG0_ODR_100HZ   0x08

◆ C6DOFIMU14_ACFG0_ODR_12p5HZ

#define C6DOFIMU14_ACFG0_ODR_12p5HZ   0x0B

◆ C6DOFIMU14_ACFG0_ODR_16KHZ

#define C6DOFIMU14_ACFG0_ODR_16KHZ   0x02

◆ C6DOFIMU14_ACFG0_ODR_1KHZ

#define C6DOFIMU14_ACFG0_ODR_1KHZ   0x06

◆ C6DOFIMU14_ACFG0_ODR_1p562HZ

#define C6DOFIMU14_ACFG0_ODR_1p562HZ   0x0E

◆ C6DOFIMU14_ACFG0_ODR_200HZ

#define C6DOFIMU14_ACFG0_ODR_200HZ   0x07

◆ C6DOFIMU14_ACFG0_ODR_25HZ

#define C6DOFIMU14_ACFG0_ODR_25HZ   0x0A

◆ C6DOFIMU14_ACFG0_ODR_2KHZ

#define C6DOFIMU14_ACFG0_ODR_2KHZ   0x05

◆ C6DOFIMU14_ACFG0_ODR_32KHZ

#define C6DOFIMU14_ACFG0_ODR_32KHZ   0x01

◆ C6DOFIMU14_ACFG0_ODR_3p125HZ

#define C6DOFIMU14_ACFG0_ODR_3p125HZ   0x0D

◆ C6DOFIMU14_ACFG0_ODR_4KHZ

#define C6DOFIMU14_ACFG0_ODR_4KHZ   0x04

◆ C6DOFIMU14_ACFG0_ODR_500HZ

#define C6DOFIMU14_ACFG0_ODR_500HZ   0x0F

◆ C6DOFIMU14_ACFG0_ODR_50HZ

#define C6DOFIMU14_ACFG0_ODR_50HZ   0x09

◆ C6DOFIMU14_ACFG0_ODR_6p25HZ

#define C6DOFIMU14_ACFG0_ODR_6p25HZ   0x0C

◆ C6DOFIMU14_ACFG0_ODR_8KHZ

#define C6DOFIMU14_ACFG0_ODR_8KHZ   0x03

◆ C6DOFIMU14_ACFG1_DEC2_M2_ORD_3RD_OTHER

#define C6DOFIMU14_ACFG1_DEC2_M2_ORD_3RD_OTHER   0x02

◆ C6DOFIMU14_ACFG1_UI_FILT_ORD_1ST_OTHER

#define C6DOFIMU14_ACFG1_UI_FILT_ORD_1ST_OTHER   0x00

6DOF IMU 14 ACCEL CONFIG 1 register settings.

ACCEL CONFIG 1 register setting flags ( Default - 0x0D ).

◆ C6DOFIMU14_ACFG1_UI_FILT_ORD_2ND_OTHER

#define C6DOFIMU14_ACFG1_UI_FILT_ORD_2ND_OTHER   0x04

◆ C6DOFIMU14_ACFG1_UI_FILT_ORD_3RD_OTHER

#define C6DOFIMU14_ACFG1_UI_FILT_ORD_3RD_OTHER   0x08

◆ C6DOFIMU14_APEX_CFG1_LOW_ENERGY_SEL

#define C6DOFIMU14_APEX_CFG1_LOW_ENERGY_SEL   0xA0

6DOF IMU 14 APEX CONFIG 1 register settings.

APEX CONFIG 1 register setting flags.

◆ C6DOFIMU14_APEX_CFG1_TIME_SEL_0SEC

#define C6DOFIMU14_APEX_CFG1_TIME_SEL_0SEC   0x00

◆ C6DOFIMU14_APEX_CFG1_TIME_SEL_12SEC

#define C6DOFIMU14_APEX_CFG1_TIME_SEL_12SEC   0x03

◆ C6DOFIMU14_APEX_CFG1_TIME_SEL_16SEC

#define C6DOFIMU14_APEX_CFG1_TIME_SEL_16SEC   0x04

◆ C6DOFIMU14_APEX_CFG1_TIME_SEL_20SEC

#define C6DOFIMU14_APEX_CFG1_TIME_SEL_20SEC   0x05

◆ C6DOFIMU14_APEX_CFG1_TIME_SEL_24SEC

#define C6DOFIMU14_APEX_CFG1_TIME_SEL_24SEC   0x06

◆ C6DOFIMU14_APEX_CFG1_TIME_SEL_28SEC

#define C6DOFIMU14_APEX_CFG1_TIME_SEL_28SEC   0x07

◆ C6DOFIMU14_APEX_CFG1_TIME_SEL_32SEC

#define C6DOFIMU14_APEX_CFG1_TIME_SEL_32SEC   0x08

◆ C6DOFIMU14_APEX_CFG1_TIME_SEL_36SEC

#define C6DOFIMU14_APEX_CFG1_TIME_SEL_36SEC   0x09

◆ C6DOFIMU14_APEX_CFG1_TIME_SEL_40SEC

#define C6DOFIMU14_APEX_CFG1_TIME_SEL_40SEC   0x0A

◆ C6DOFIMU14_APEX_CFG1_TIME_SEL_44SEC

#define C6DOFIMU14_APEX_CFG1_TIME_SEL_44SEC   0x0B

◆ C6DOFIMU14_APEX_CFG1_TIME_SEL_48SEC

#define C6DOFIMU14_APEX_CFG1_TIME_SEL_48SEC   0x0C

◆ C6DOFIMU14_APEX_CFG1_TIME_SEL_4SEC

#define C6DOFIMU14_APEX_CFG1_TIME_SEL_4SEC   0x01

◆ C6DOFIMU14_APEX_CFG1_TIME_SEL_52SEC

#define C6DOFIMU14_APEX_CFG1_TIME_SEL_52SEC   0x0D

◆ C6DOFIMU14_APEX_CFG1_TIME_SEL_56SEC

#define C6DOFIMU14_APEX_CFG1_TIME_SEL_56SEC   0x0E

◆ C6DOFIMU14_APEX_CFG1_TIME_SEL_60SEC

#define C6DOFIMU14_APEX_CFG1_TIME_SEL_60SEC   0x0F

◆ C6DOFIMU14_APEX_CFG1_TIME_SEL_8SEC

#define C6DOFIMU14_APEX_CFG1_TIME_SEL_8SEC   0x02

◆ C6DOFIMU14_APEX_CFG2_PED_AMP_TH_SEL

#define C6DOFIMU14_APEX_CFG2_PED_AMP_TH_SEL   0x80

6DOF IMU 14 APEX CONFIG 2 register settings.

APEX CONFIG 2 register setting flags.

◆ C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_0

#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_0   0x00

◆ C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_1

#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_1   0x01

◆ C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_10

#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_10   0x0A

◆ C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_11

#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_11   0x0B

◆ C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_12

#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_12   0x0C

◆ C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_13

#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_13   0x0D

◆ C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_14

#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_14   0x0E

◆ C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_15

#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_15   0x0F

◆ C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_2

#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_2   0x02

◆ C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_3

#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_3   0x03

◆ C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_4

#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_4   0x04

◆ C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_5

#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_5   0x05

◆ C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_6

#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_6   0x06

◆ C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_7

#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_7   0x07

◆ C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_8

#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_8   0x08

◆ C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_9

#define C6DOFIMU14_APEX_CFG2_PED_CNT_SEL_9   0x09

◆ C6DOFIMU14_APEX_CFG3_HI_EN_TH_SEL

#define C6DOFIMU14_APEX_CFG3_HI_EN_TH_SEL   0x01

◆ C6DOFIMU14_APEX_CFG3_STEP_DET_SEL_0

#define C6DOFIMU14_APEX_CFG3_STEP_DET_SEL_0   0x00

6DOF IMU 14 APEX CONFIG 3 register settings.

APEX CONFIG 3 register setting flags.

◆ C6DOFIMU14_APEX_CFG3_STEP_DET_SEL_1

#define C6DOFIMU14_APEX_CFG3_STEP_DET_SEL_1   0x20

◆ C6DOFIMU14_APEX_CFG3_STEP_DET_SEL_2

#define C6DOFIMU14_APEX_CFG3_STEP_DET_SEL_2   0x40

◆ C6DOFIMU14_APEX_CFG3_STEP_DET_SEL_3

#define C6DOFIMU14_APEX_CFG3_STEP_DET_SEL_3   0x60

◆ C6DOFIMU14_APEX_CFG3_STEP_DET_SEL_4

#define C6DOFIMU14_APEX_CFG3_STEP_DET_SEL_4   0x80

◆ C6DOFIMU14_APEX_CFG3_STEP_DET_SEL_5

#define C6DOFIMU14_APEX_CFG3_STEP_DET_SEL_5   0xA0

◆ C6DOFIMU14_APEX_CFG3_STEP_DET_SEL_6

#define C6DOFIMU14_APEX_CFG3_STEP_DET_SEL_6   0xC0

◆ C6DOFIMU14_APEX_CFG3_STEP_DET_SEL_7

#define C6DOFIMU14_APEX_CFG3_STEP_DET_SEL_7   0xE0

◆ C6DOFIMU14_APEX_CFG3_TIMER_SEL_0

#define C6DOFIMU14_APEX_CFG3_TIMER_SEL_0   0x00

◆ C6DOFIMU14_APEX_CFG3_TIMER_SEL_1

#define C6DOFIMU14_APEX_CFG3_TIMER_SEL_1   0x04

◆ C6DOFIMU14_APEX_CFG3_TIMER_SEL_2

#define C6DOFIMU14_APEX_CFG3_TIMER_SEL_2   0x08

◆ C6DOFIMU14_APEX_CFG3_TIMER_SEL_3

#define C6DOFIMU14_APEX_CFG3_TIMER_SEL_3   0x0C

◆ C6DOFIMU14_APEX_CFG3_TIMER_SEL_4

#define C6DOFIMU14_APEX_CFG3_TIMER_SEL_4   0x10

◆ C6DOFIMU14_APEX_CFG3_TIMER_SEL_5

#define C6DOFIMU14_APEX_CFG3_TIMER_SEL_5   0x14

◆ C6DOFIMU14_APEX_CFG3_TIMER_SEL_6

#define C6DOFIMU14_APEX_CFG3_TIMER_SEL_6   0x18

◆ C6DOFIMU14_APEX_CFG3_TIMER_SEL_7

#define C6DOFIMU14_APEX_CFG3_TIMER_SEL_7   0x1C

◆ C6DOFIMU14_APEX_CFG4_TILT_SLEEP_TIME_10p24SEC

#define C6DOFIMU14_APEX_CFG4_TILT_SLEEP_TIME_10p24SEC   0x38

◆ C6DOFIMU14_APEX_CFG4_TILT_SLEEP_TIME_1p28SEC

#define C6DOFIMU14_APEX_CFG4_TILT_SLEEP_TIME_1p28SEC   0x00

◆ C6DOFIMU14_APEX_CFG4_TILT_SLEEP_TIME_2p56SEC

#define C6DOFIMU14_APEX_CFG4_TILT_SLEEP_TIME_2p56SEC   0x08

◆ C6DOFIMU14_APEX_CFG4_TILT_SLEEP_TIME_3p84SEC

#define C6DOFIMU14_APEX_CFG4_TILT_SLEEP_TIME_3p84SEC   0x10

◆ C6DOFIMU14_APEX_CFG4_TILT_SLEEP_TIME_5p12SEC

#define C6DOFIMU14_APEX_CFG4_TILT_SLEEP_TIME_5p12SEC   0x18

◆ C6DOFIMU14_APEX_CFG4_TILT_SLEEP_TIME_6p40SEC

#define C6DOFIMU14_APEX_CFG4_TILT_SLEEP_TIME_6p40SEC   0x20

◆ C6DOFIMU14_APEX_CFG4_TILT_SLEEP_TIME_7p68SEC

#define C6DOFIMU14_APEX_CFG4_TILT_SLEEP_TIME_7p68SEC   0x28

◆ C6DOFIMU14_APEX_CFG4_TILT_SLEEP_TIME_8p96SEC

#define C6DOFIMU14_APEX_CFG4_TILT_SLEEP_TIME_8p96SEC   0x30

◆ C6DOFIMU14_APEX_CFG4_TILT_WAIT_SEL_0S

#define C6DOFIMU14_APEX_CFG4_TILT_WAIT_SEL_0S   0x00

6DOF IMU 14 APEX CONFIG 4 register settings.

APEX CONFIG 4 register setting flags.

◆ C6DOFIMU14_APEX_CFG4_TILT_WAIT_SEL_2S

#define C6DOFIMU14_APEX_CFG4_TILT_WAIT_SEL_2S   0x40

◆ C6DOFIMU14_APEX_CFG4_TILT_WAIT_SEL_4S

#define C6DOFIMU14_APEX_CFG4_TILT_WAIT_SEL_4S   0x80

◆ C6DOFIMU14_APEX_CFG4_TILT_WAIT_SEL_6S

#define C6DOFIMU14_APEX_CFG4_TILT_WAIT_SEL_6S   0xC0

◆ C6DOFIMU14_APEXCFG0_DMP_ACTIVE

#define C6DOFIMU14_APEXCFG0_DMP_ACTIVE   0x80

◆ C6DOFIMU14_APEXCFG0_DMP_NOT_ACTIVE

#define C6DOFIMU14_APEXCFG0_DMP_NOT_ACTIVE   0x00

6DOF IMU 14 APEX CONFIG 0 register settings.

APEX CONFIG 0 register setting flags.

◆ C6DOFIMU14_APEXCFG0_DMP_ODR_25HZ

#define C6DOFIMU14_APEXCFG0_DMP_ODR_25HZ   0x00

◆ C6DOFIMU14_APEXCFG0_DMP_ODR_50HZ

#define C6DOFIMU14_APEXCFG0_DMP_ODR_50HZ   0x03

◆ C6DOFIMU14_APEXCFG0_PED_DISABLE

#define C6DOFIMU14_APEXCFG0_PED_DISABLE   0x00

◆ C6DOFIMU14_APEXCFG0_PED_ENABLE

#define C6DOFIMU14_APEXCFG0_PED_ENABLE   0x20

◆ C6DOFIMU14_APEXCFG0_R2W_DISABLE

#define C6DOFIMU14_APEXCFG0_R2W_DISABLE   0x00

◆ C6DOFIMU14_APEXCFG0_R2W_EMABLE

#define C6DOFIMU14_APEXCFG0_R2W_EMABLE   0x08

◆ C6DOFIMU14_APEXCFG0_TAP_DISABLE

#define C6DOFIMU14_APEXCFG0_TAP_DISABLE   0x00

◆ C6DOFIMU14_APEXCFG0_TAP_ENABLE

#define C6DOFIMU14_APEXCFG0_TAP_ENABLE   0x40

◆ C6DOFIMU14_APEXCFG0_TILT_DISABLE

#define C6DOFIMU14_APEXCFG0_TILT_DISABLE   0x00

◆ C6DOFIMU14_APEXCFG0_TILT_ENABLE

#define C6DOFIMU14_APEXCFG0_TILT_ENABLE   0x10

◆ C6DOFIMU14_BANK_0

#define C6DOFIMU14_BANK_0   0x00

6DOF IMU 14 REG BANK SELECT register settings.

REG BANK SELECT register setting flags ( Default - 0x00 ).

◆ C6DOFIMU14_BANK_1

#define C6DOFIMU14_BANK_1   0x01

◆ C6DOFIMU14_BANK_2

#define C6DOFIMU14_BANK_2   0x02

◆ C6DOFIMU14_BANK_3

#define C6DOFIMU14_BANK_3   0x03

◆ C6DOFIMU14_BANK_4

#define C6DOFIMU14_BANK_4   0x04

◆ C6DOFIMU14_DEF_WHO_AM_I

#define C6DOFIMU14_DEF_WHO_AM_I   0x47

6DOF IMU 14 WHO AM I register settings.

WHO AM I register setting ( Default - 0x47 ).

◆ C6DOFIMU14_DEVCONFIG_SOFT_RESET_ENABLE

#define C6DOFIMU14_DEVCONFIG_SOFT_RESET_ENABLE   0x01

◆ C6DOFIMU14_DEVCONFIG_SOFT_RESET_NORMAL

#define C6DOFIMU14_DEVCONFIG_SOFT_RESET_NORMAL   0x00

◆ C6DOFIMU14_DEVCONFIG_SPI_MODE_03

#define C6DOFIMU14_DEVCONFIG_SPI_MODE_03   0x00

6DOF IMU 14 DEVICE CONFIG register settings.

DEVICE CONFIG register setting flags.

◆ C6DOFIMU14_DEVCONFIG_SPI_MODE_12

#define C6DOFIMU14_DEVCONFIG_SPI_MODE_12   0x10

◆ C6DOFIMU14_DRIVECONFIG_MAX_SLEW_RATE

#define C6DOFIMU14_DRIVECONFIG_MAX_SLEW_RATE   0x55

6DOF IMU 14 DRIVE CONFIG register settings.

DRIVE CONFIG register setting flags.

◆ C6DOFIMU14_DRIVECONFIG_MIN_SLEW_RATE

#define C6DOFIMU14_DRIVECONFIG_MIN_SLEW_RATE   0x00

◆ C6DOFIMU14_FIFOCONFIG1_ACCEL_EN

#define C6DOFIMU14_FIFOCONFIG1_ACCEL_EN   0x01

◆ C6DOFIMU14_FIFOCONFIG1_GYRO_EN

#define C6DOFIMU14_FIFOCONFIG1_GYRO_EN   0x02

◆ C6DOFIMU14_FIFOCONFIG1_HIRES_EN

#define C6DOFIMU14_FIFOCONFIG1_HIRES_EN   0x10

◆ C6DOFIMU14_FIFOCONFIG1_RESUME_PARTIAL_RD

#define C6DOFIMU14_FIFOCONFIG1_RESUME_PARTIAL_RD   0x40

6DOF IMU 14 FIFO CONFIG 1 register settings.

FIFO CONFIG 1 register setting flags.

◆ C6DOFIMU14_FIFOCONFIG1_TEMP_EN

#define C6DOFIMU14_FIFOCONFIG1_TEMP_EN   0x04

◆ C6DOFIMU14_FIFOCONFIG1_TMST_FSYNC_EN

#define C6DOFIMU14_FIFOCONFIG1_TMST_FSYNC_EN   0x08

◆ C6DOFIMU14_FIFOCONFIG_BYPASS_MODE

#define C6DOFIMU14_FIFOCONFIG_BYPASS_MODE   0x00

6DOF IMU 14 FIFO CONFIG register settings.

FIFO CONFIG register setting flags.

◆ C6DOFIMU14_FIFOCONFIG_STOP_ON_FULL_MODE

#define C6DOFIMU14_FIFOCONFIG_STOP_ON_FULL_MODE   0x80

◆ C6DOFIMU14_FIFOCONFIG_STREAM_TO_FIFO_MODE

#define C6DOFIMU14_FIFOCONFIG_STREAM_TO_FIFO_MODE   0x40

◆ C6DOFIMU14_FIFOHEADER_20

#define C6DOFIMU14_FIFOHEADER_20   0x10

◆ C6DOFIMU14_FIFOHEADER_ACCEL

#define C6DOFIMU14_FIFOHEADER_ACCEL   0x40

◆ C6DOFIMU14_FIFOHEADER_GYRO

#define C6DOFIMU14_FIFOHEADER_GYRO   0x20

◆ C6DOFIMU14_FIFOHEADER_MSG

#define C6DOFIMU14_FIFOHEADER_MSG   0x80

6DOF IMU 14 FIFO HEADER byte settings.

FIFO HEADER byte setting flags.

◆ C6DOFIMU14_FIFOHEADER_ODR_ACCEL

#define C6DOFIMU14_FIFOHEADER_ODR_ACCEL   0x02

◆ C6DOFIMU14_FIFOHEADER_ODR_GYRO

#define C6DOFIMU14_FIFOHEADER_ODR_GYRO   0x01

◆ C6DOFIMU14_FIFOHEADER_TIMESTAMP_ODR

#define C6DOFIMU14_FIFOHEADER_TIMESTAMP_ODR   0x08

◆ C6DOFIMU14_GACFG0_AC_UI_BW_ODR_10

#define C6DOFIMU14_GACFG0_AC_UI_BW_ODR_10   0x40

◆ C6DOFIMU14_GACFG0_AC_UI_BW_ODR_16

#define C6DOFIMU14_GACFG0_AC_UI_BW_ODR_16   0x50

◆ C6DOFIMU14_GACFG0_AC_UI_BW_ODR_2

#define C6DOFIMU14_GACFG0_AC_UI_BW_ODR_2   0x00

6DOF IMU 14 GYRO ACCEL CONFIG 0 register settings.

GYRO ACCEL CONFIG 0 register setting flags ( Default - 0x11 ).

◆ C6DOFIMU14_GACFG0_AC_UI_BW_ODR_20

#define C6DOFIMU14_GACFG0_AC_UI_BW_ODR_20   0x60

◆ C6DOFIMU14_GACFG0_AC_UI_BW_ODR_4

#define C6DOFIMU14_GACFG0_AC_UI_BW_ODR_4   0x10

◆ C6DOFIMU14_GACFG0_AC_UI_BW_ODR_40

#define C6DOFIMU14_GACFG0_AC_UI_BW_ODR_40   0x70

◆ C6DOFIMU14_GACFG0_AC_UI_BW_ODR_5

#define C6DOFIMU14_GACFG0_AC_UI_BW_ODR_5   0x20

◆ C6DOFIMU14_GACFG0_AC_UI_BW_ODR_8

#define C6DOFIMU14_GACFG0_AC_UI_BW_ODR_8   0x30

◆ C6DOFIMU14_GACFG0_GY_UI_BW_ODR_10

#define C6DOFIMU14_GACFG0_GY_UI_BW_ODR_10   0x04

◆ C6DOFIMU14_GACFG0_GY_UI_BW_ODR_16

#define C6DOFIMU14_GACFG0_GY_UI_BW_ODR_16   0x05

◆ C6DOFIMU14_GACFG0_GY_UI_BW_ODR_2

#define C6DOFIMU14_GACFG0_GY_UI_BW_ODR_2   0x00

◆ C6DOFIMU14_GACFG0_GY_UI_BW_ODR_20

#define C6DOFIMU14_GACFG0_GY_UI_BW_ODR_20   0x06

◆ C6DOFIMU14_GACFG0_GY_UI_BW_ODR_4

#define C6DOFIMU14_GACFG0_GY_UI_BW_ODR_4   0x01

◆ C6DOFIMU14_GACFG0_GY_UI_BW_ODR_40

#define C6DOFIMU14_GACFG0_GY_UI_BW_ODR_40   0x07

◆ C6DOFIMU14_GACFG0_GY_UI_BW_ODR_5

#define C6DOFIMU14_GACFG0_GY_UI_BW_ODR_5   0x02

◆ C6DOFIMU14_GACFG0_GY_UI_BW_ODR_8

#define C6DOFIMU14_GACFG0_GY_UI_BW_ODR_8   0x03

◆ C6DOFIMU14_GCFG0_FS_SEL_1000DPS

#define C6DOFIMU14_GCFG0_FS_SEL_1000DPS   0x20

◆ C6DOFIMU14_GCFG0_FS_SEL_125DPS

#define C6DOFIMU14_GCFG0_FS_SEL_125DPS   0x80

◆ C6DOFIMU14_GCFG0_FS_SEL_15p625DPS

#define C6DOFIMU14_GCFG0_FS_SEL_15p625DPS   0xE0

◆ C6DOFIMU14_GCFG0_FS_SEL_2000DPS

#define C6DOFIMU14_GCFG0_FS_SEL_2000DPS   0x00

6DOF IMU 14 GYRO CONFIG 0 register settings.

GYRO CONFIG 0 register setting flags ( Default - 0x06 ).

◆ C6DOFIMU14_GCFG0_FS_SEL_250DPS

#define C6DOFIMU14_GCFG0_FS_SEL_250DPS   0x60

◆ C6DOFIMU14_GCFG0_FS_SEL_31p25DPS

#define C6DOFIMU14_GCFG0_FS_SEL_31p25DPS   0xC0

◆ C6DOFIMU14_GCFG0_FS_SEL_500DPS

#define C6DOFIMU14_GCFG0_FS_SEL_500DPS   0x40

◆ C6DOFIMU14_GCFG0_FS_SEL_62p5DPS

#define C6DOFIMU14_GCFG0_FS_SEL_62p5DPS   0xA0

◆ C6DOFIMU14_GCFG0_ODR_100HZ

#define C6DOFIMU14_GCFG0_ODR_100HZ   0x08

◆ C6DOFIMU14_GCFG0_ODR_12p5HZ

#define C6DOFIMU14_GCFG0_ODR_12p5HZ   0x0B

◆ C6DOFIMU14_GCFG0_ODR_16KHZ

#define C6DOFIMU14_GCFG0_ODR_16KHZ   0x02

◆ C6DOFIMU14_GCFG0_ODR_1KHZ

#define C6DOFIMU14_GCFG0_ODR_1KHZ   0x06

◆ C6DOFIMU14_GCFG0_ODR_200HZ

#define C6DOFIMU14_GCFG0_ODR_200HZ   0x07

◆ C6DOFIMU14_GCFG0_ODR_25HZ

#define C6DOFIMU14_GCFG0_ODR_25HZ   0x0A

◆ C6DOFIMU14_GCFG0_ODR_2KHZ

#define C6DOFIMU14_GCFG0_ODR_2KHZ   0x05

◆ C6DOFIMU14_GCFG0_ODR_32KHZ

#define C6DOFIMU14_GCFG0_ODR_32KHZ   0x01

◆ C6DOFIMU14_GCFG0_ODR_4KHZ

#define C6DOFIMU14_GCFG0_ODR_4KHZ   0x04

◆ C6DOFIMU14_GCFG0_ODR_500HZ

#define C6DOFIMU14_GCFG0_ODR_500HZ   0x0F

◆ C6DOFIMU14_GCFG0_ODR_50HZ

#define C6DOFIMU14_GCFG0_ODR_50HZ   0x09

◆ C6DOFIMU14_GCFG0_ODR_8KHZ

#define C6DOFIMU14_GCFG0_ODR_8KHZ   0x03

◆ C6DOFIMU14_GCFG1_DEC2_M2_ORD_3RD_OTHER

#define C6DOFIMU14_GCFG1_DEC2_M2_ORD_3RD_OTHER   0x02

◆ C6DOFIMU14_GCFG1_FILT_BW_10HZ

#define C6DOFIMU14_GCFG1_FILT_BW_10HZ   0xA0

◆ C6DOFIMU14_GCFG1_FILT_BW_170HZ

#define C6DOFIMU14_GCFG1_FILT_BW_170HZ   0x20

◆ C6DOFIMU14_GCFG1_FILT_BW_20HZ

#define C6DOFIMU14_GCFG1_FILT_BW_20HZ   0x80

◆ C6DOFIMU14_GCFG1_FILT_BW_4000HZ

#define C6DOFIMU14_GCFG1_FILT_BW_4000HZ   0x00

6DOF IMU 14 GYRO CONFIG 1 register settings.

GYRO CONFIG 1 register setting flags ( Default - 0x16 ).

◆ C6DOFIMU14_GCFG1_FILT_BW_40HZ

#define C6DOFIMU14_GCFG1_FILT_BW_40HZ   0x60

◆ C6DOFIMU14_GCFG1_FILT_BW_5HZ

#define C6DOFIMU14_GCFG1_FILT_BW_5HZ   0xC0

◆ C6DOFIMU14_GCFG1_FILT_BW_82HZ

#define C6DOFIMU14_GCFG1_FILT_BW_82HZ   0x40

◆ C6DOFIMU14_GCFG1_UI_FILT_ORD_1ST_OTHER

#define C6DOFIMU14_GCFG1_UI_FILT_ORD_1ST_OTHER   0x00

◆ C6DOFIMU14_GCFG1_UI_FILT_ORD_2ND_OTHER

#define C6DOFIMU14_GCFG1_UI_FILT_ORD_2ND_OTHER   0x04

◆ C6DOFIMU14_GCFG1_UI_FILT_ORD_3RD_OTHER

#define C6DOFIMU14_GCFG1_UI_FILT_ORD_3RD_OTHER   0x08

◆ C6DOFIMU14_INTF0_FIFO_COUNT_ENDIAN_0

#define C6DOFIMU14_INTF0_FIFO_COUNT_ENDIAN_0   0x00

◆ C6DOFIMU14_INTF0_FIFO_COUNT_ENDIAN_1

#define C6DOFIMU14_INTF0_FIFO_COUNT_ENDIAN_1   0x20

◆ C6DOFIMU14_INTF0_FIFO_COUNT_REC_0

#define C6DOFIMU14_INTF0_FIFO_COUNT_REC_0   0x00

◆ C6DOFIMU14_INTF0_FIFO_COUNT_REC_1

#define C6DOFIMU14_INTF0_FIFO_COUNT_REC_1   0x40

◆ C6DOFIMU14_INTF0_FIFO_HOLD_LAST_DATA_DIS

#define C6DOFIMU14_INTF0_FIFO_HOLD_LAST_DATA_DIS   0x00

◆ C6DOFIMU14_INTF0_FIFO_HOLD_LAST_DATA_EN

#define C6DOFIMU14_INTF0_FIFO_HOLD_LAST_DATA_EN   0x80

6DOF IMU 14 INTF config 0 register settings.

INTF config 0 register setting flags ( Default - 0x30 ).

◆ C6DOFIMU14_INTF0_SENSOR_DATA_ENDIAN_0

#define C6DOFIMU14_INTF0_SENSOR_DATA_ENDIAN_0   0x00

◆ C6DOFIMU14_INTF0_SENSOR_DATA_ENDIAN_1

#define C6DOFIMU14_INTF0_SENSOR_DATA_ENDIAN_1   0x10

◆ C6DOFIMU14_INTF0_UI_SIFS_CFG_DISABLE_I2C

#define C6DOFIMU14_INTF0_UI_SIFS_CFG_DISABLE_I2C   0x01

◆ C6DOFIMU14_INTF0_UI_SIFS_CFG_DISABLE_SPI

#define C6DOFIMU14_INTF0_UI_SIFS_CFG_DISABLE_SPI   0x00

◆ C6DOFIMU14_INTF1_ACLP_CLK_SEL_RC_CLK

#define C6DOFIMU14_INTF1_ACLP_CLK_SEL_RC_CLK   0x08

◆ C6DOFIMU14_INTF1_ACLP_CLK_SEL_WAKEUP_CLK

#define C6DOFIMU14_INTF1_ACLP_CLK_SEL_WAKEUP_CLK   0x00

6DOF IMU 14 INTF config 1 register settings.

INTF config 1 register setting flags ( Default - 0x91 ).

◆ C6DOFIMU14_INTF1_CLKSEL_DISABLE_ALL_OS

#define C6DOFIMU14_INTF1_CLKSEL_DISABLE_ALL_OS   0x11

◆ C6DOFIMU14_INTF1_CLKSEL_PLL_RC_OS

#define C6DOFIMU14_INTF1_CLKSEL_PLL_RC_OS   0x01

◆ C6DOFIMU14_INTF1_CLKSEL_RC_OS

#define C6DOFIMU14_INTF1_CLKSEL_RC_OS   0x00

◆ C6DOFIMU14_INTF1_RTC_MODE_INPUT

#define C6DOFIMU14_INTF1_RTC_MODE_INPUT   0x04

◆ C6DOFIMU14_INTF1_RTC_MODE_NO_INPUT

#define C6DOFIMU14_INTF1_RTC_MODE_NO_INPUT   0x00

◆ C6DOFIMU14_INTSRC6_SLEEP_DET_INT1_DIS

#define C6DOFIMU14_INTSRC6_SLEEP_DET_INT1_DIS   0x00

◆ C6DOFIMU14_INTSRC6_SLEEP_DET_INT1_EN

#define C6DOFIMU14_INTSRC6_SLEEP_DET_INT1_EN   0x02

◆ C6DOFIMU14_INTSRC6_STEP_CNT_OFL_INT1_DIS

#define C6DOFIMU14_INTSRC6_STEP_CNT_OFL_INT1_DIS   0x00

◆ C6DOFIMU14_INTSRC6_STEP_CNT_OFL_INT1_EN

#define C6DOFIMU14_INTSRC6_STEP_CNT_OFL_INT1_EN   0x10

◆ C6DOFIMU14_INTSRC6_STEP_DET_INT1_DIS

#define C6DOFIMU14_INTSRC6_STEP_DET_INT1_DIS   0x00

◆ C6DOFIMU14_INTSRC6_STEP_DET_INT1_EN

#define C6DOFIMU14_INTSRC6_STEP_DET_INT1_EN   0x20

6DOF IMU 14 INT SOURCE 6 register settings.

INT SOURCE 6 register setting flags.

◆ C6DOFIMU14_INTSRC6_TAP_DET_INT1_DIS

#define C6DOFIMU14_INTSRC6_TAP_DET_INT1_DIS   0x00

◆ C6DOFIMU14_INTSRC6_TAP_DET_INT1_EN

#define C6DOFIMU14_INTSRC6_TAP_DET_INT1_EN   0x01

◆ C6DOFIMU14_INTSRC6_TILT_DET_INT1_DIS

#define C6DOFIMU14_INTSRC6_TILT_DET_INT1_DIS   0x00

◆ C6DOFIMU14_INTSRC6_TILT_DET_INT1_EN

#define C6DOFIMU14_INTSRC6_TILT_DET_INT1_EN   0x08

◆ C6DOFIMU14_INTSRC6_WAKE_DET_INT1_DIS

#define C6DOFIMU14_INTSRC6_WAKE_DET_INT1_DIS   0x00

◆ C6DOFIMU14_INTSRC6_WAKE_DET_INT1_EN

#define C6DOFIMU14_INTSRC6_WAKE_DET_INT1_EN   0x04

◆ C6DOFIMU14_INTSRC7_SLEEP_DET_INT2_DIS

#define C6DOFIMU14_INTSRC7_SLEEP_DET_INT2_DIS   0x00

◆ C6DOFIMU14_INTSRC7_SLEEP_DET_INT2_EN

#define C6DOFIMU14_INTSRC7_SLEEP_DET_INT2_EN   0x02

◆ C6DOFIMU14_INTSRC7_STEP_CNT_OFL_INT2_DIS

#define C6DOFIMU14_INTSRC7_STEP_CNT_OFL_INT2_DIS   0x00

◆ C6DOFIMU14_INTSRC7_STEP_CNT_OFL_INT2_EN

#define C6DOFIMU14_INTSRC7_STEP_CNT_OFL_INT2_EN   0x10

◆ C6DOFIMU14_INTSRC7_STEP_DET_INT2_DIS

#define C6DOFIMU14_INTSRC7_STEP_DET_INT2_DIS   0x00

◆ C6DOFIMU14_INTSRC7_STEP_DET_INT2_EN

#define C6DOFIMU14_INTSRC7_STEP_DET_INT2_EN   0x20

6DOF IMU 14 INT SOURCE 7 register settings.

INT SOURCE 7 register setting flags.

◆ C6DOFIMU14_INTSRC7_TAP_DET_INT2_DIS

#define C6DOFIMU14_INTSRC7_TAP_DET_INT2_DIS   0x00

◆ C6DOFIMU14_INTSRC7_TAP_DET_INT2_EN

#define C6DOFIMU14_INTSRC7_TAP_DET_INT2_EN   0x01

◆ C6DOFIMU14_INTSRC7_TILT_DET_INT2_DIS

#define C6DOFIMU14_INTSRC7_TILT_DET_INT2_DIS   0x00

◆ C6DOFIMU14_INTSRC7_TILT_DET_INT2_EN

#define C6DOFIMU14_INTSRC7_TILT_DET_INT2_EN   0x08

◆ C6DOFIMU14_INTSRC7_WAKE_DET_INT2_DIS

#define C6DOFIMU14_INTSRC7_WAKE_DET_INT2_DIS   0x00

◆ C6DOFIMU14_INTSRC7_WAKE_DET_INT2_EN

#define C6DOFIMU14_INTSRC7_WAKE_DET_INT2_EN   0x04

◆ C6DOFIMU14_INTSTATUS_AGC_RDY

#define C6DOFIMU14_INTSTATUS_AGC_RDY   0x01

◆ C6DOFIMU14_INTSTATUS_DATA_RDY

#define C6DOFIMU14_INTSTATUS_DATA_RDY   0x08

◆ C6DOFIMU14_INTSTATUS_FIFO_FULL

#define C6DOFIMU14_INTSTATUS_FIFO_FULL   0x02

◆ C6DOFIMU14_INTSTATUS_FIFO_THS

#define C6DOFIMU14_INTSTATUS_FIFO_THS   0x04

◆ C6DOFIMU14_INTSTATUS_PLL_RDY

#define C6DOFIMU14_INTSTATUS_PLL_RDY   0x20

◆ C6DOFIMU14_INTSTATUS_RESET_DONE

#define C6DOFIMU14_INTSTATUS_RESET_DONE   0x10

◆ C6DOFIMU14_INTSTATUS_UI_FSYNC

#define C6DOFIMU14_INTSTATUS_UI_FSYNC   0x40

6DOF IMU 14 INT STATUS register settings.

INT STATUS register setting flags.

◆ C6DOFIMU14_ISRC0_FIFO_FULL_INT1_DIS

#define C6DOFIMU14_ISRC0_FIFO_FULL_INT1_DIS   0x00

◆ C6DOFIMU14_ISRC0_FIFO_FULL_INT1_EN

#define C6DOFIMU14_ISRC0_FIFO_FULL_INT1_EN   0x02

◆ C6DOFIMU14_ISRC0_FIFO_THS_INT1_DIS

#define C6DOFIMU14_ISRC0_FIFO_THS_INT1_DIS   0x00

◆ C6DOFIMU14_ISRC0_FIFO_THS_INT1_EN

#define C6DOFIMU14_ISRC0_FIFO_THS_INT1_EN   0x04

◆ C6DOFIMU14_ISRC0_PLL_RDY_INT1_DIS

#define C6DOFIMU14_ISRC0_PLL_RDY_INT1_DIS   0x00

◆ C6DOFIMU14_ISRC0_PLL_RDY_INT1_EN

#define C6DOFIMU14_ISRC0_PLL_RDY_INT1_EN   0x20

◆ C6DOFIMU14_ISRC0_RESET_DONE_INT1_DIS

#define C6DOFIMU14_ISRC0_RESET_DONE_INT1_DIS   0x00

◆ C6DOFIMU14_ISRC0_RESET_DONE_INT1_EN

#define C6DOFIMU14_ISRC0_RESET_DONE_INT1_EN   0x10

◆ C6DOFIMU14_ISRC0_UI_AGC_RDY_INT1_DIS

#define C6DOFIMU14_ISRC0_UI_AGC_RDY_INT1_DIS   0x00

◆ C6DOFIMU14_ISRC0_UI_AGC_RDY_INT1_EN

#define C6DOFIMU14_ISRC0_UI_AGC_RDY_INT1_EN   0x01

◆ C6DOFIMU14_ISRC0_UI_DRDY_INT1_DIS

#define C6DOFIMU14_ISRC0_UI_DRDY_INT1_DIS   0x00

◆ C6DOFIMU14_ISRC0_UI_DRDY_INT1_EN

#define C6DOFIMU14_ISRC0_UI_DRDY_INT1_EN   0x08

◆ C6DOFIMU14_ISRC0_UI_FSYNC_INT1_DIS

#define C6DOFIMU14_ISRC0_UI_FSYNC_INT1_DIS   0x00

◆ C6DOFIMU14_ISRC0_UI_FSYNC_INT1_EN

#define C6DOFIMU14_ISRC0_UI_FSYNC_INT1_EN   0x40

6DOF IMU 14 INT SOURCE 0 register settings.

INT SOURCE 0 register setting flags.

◆ C6DOFIMU14_PWR_ACCEL_MODE_LOW_NOISE

#define C6DOFIMU14_PWR_ACCEL_MODE_LOW_NOISE   0x03

◆ C6DOFIMU14_PWR_ACCEL_MODE_LOW_POWER

#define C6DOFIMU14_PWR_ACCEL_MODE_LOW_POWER   0x02

◆ C6DOFIMU14_PWR_ACCEL_MODE_OFF

#define C6DOFIMU14_PWR_ACCEL_MODE_OFF   0x00

◆ C6DOFIMU14_PWR_GYRO_MODE_LOW_NOISE

#define C6DOFIMU14_PWR_GYRO_MODE_LOW_NOISE   0x0C

◆ C6DOFIMU14_PWR_GYRO_MODE_OFF

#define C6DOFIMU14_PWR_GYRO_MODE_OFF   0x00

◆ C6DOFIMU14_PWR_GYRO_MODE_STAND_BY

#define C6DOFIMU14_PWR_GYRO_MODE_STAND_BY   0x04

◆ C6DOFIMU14_PWR_IDLE_0

#define C6DOFIMU14_PWR_IDLE_0   0x00

◆ C6DOFIMU14_PWR_IDLE_1

#define C6DOFIMU14_PWR_IDLE_1   0x10

◆ C6DOFIMU14_PWR_TEMP_DISABLE

#define C6DOFIMU14_PWR_TEMP_DISABLE   0x20

◆ C6DOFIMU14_PWR_TEMP_ENABLE

#define C6DOFIMU14_PWR_TEMP_ENABLE   0x00

6DOF IMU 14 PWR-MEGMT0 register settings.

PWR-MEGMT0 register setting flags ( Default - 0x00 ).

◆ C6DOFIMU14_SENSOR_CFG_ACCEL_X_DIS

#define C6DOFIMU14_SENSOR_CFG_ACCEL_X_DIS   0x01

◆ C6DOFIMU14_SENSOR_CFG_ACCEL_X_EN

#define C6DOFIMU14_SENSOR_CFG_ACCEL_X_EN   0x00

◆ C6DOFIMU14_SENSOR_CFG_ACCEL_Y_DIS

#define C6DOFIMU14_SENSOR_CFG_ACCEL_Y_DIS   0x02

◆ C6DOFIMU14_SENSOR_CFG_ACCEL_Y_EN

#define C6DOFIMU14_SENSOR_CFG_ACCEL_Y_EN   0x00

◆ C6DOFIMU14_SENSOR_CFG_ACCEL_Z_DIS

#define C6DOFIMU14_SENSOR_CFG_ACCEL_Z_DIS   0x04

◆ C6DOFIMU14_SENSOR_CFG_ACCEL_Z_EN

#define C6DOFIMU14_SENSOR_CFG_ACCEL_Z_EN   0x00

◆ C6DOFIMU14_SENSOR_CFG_GYRO_X_DIS

#define C6DOFIMU14_SENSOR_CFG_GYRO_X_DIS   0x08

◆ C6DOFIMU14_SENSOR_CFG_GYRO_X_EN

#define C6DOFIMU14_SENSOR_CFG_GYRO_X_EN   0x00

◆ C6DOFIMU14_SENSOR_CFG_GYRO_Y_DIS

#define C6DOFIMU14_SENSOR_CFG_GYRO_Y_DIS   0x10

◆ C6DOFIMU14_SENSOR_CFG_GYRO_Y_EN

#define C6DOFIMU14_SENSOR_CFG_GYRO_Y_EN   0x00

◆ C6DOFIMU14_SENSOR_CFG_GYRO_Z_DIS

#define C6DOFIMU14_SENSOR_CFG_GYRO_Z_DIS   0x20

◆ C6DOFIMU14_SENSOR_CFG_GYRO_Z_EN

#define C6DOFIMU14_SENSOR_CFG_GYRO_Z_EN   0x00

6DOF IMU 14 SENSOR CONFIG 0 register settings.

SENSOR CONFIG 0 register setting flags.

◆ C6DOFIMU14_SET_DEV_ADDR_GND

#define C6DOFIMU14_SET_DEV_ADDR_GND   0x68

6DOF IMU 14 device address setting.

Specified setting for device slave address selection of 6DOF IMU 14 Click driver.

◆ C6DOFIMU14_SET_DEV_ADDR_VCC

#define C6DOFIMU14_SET_DEV_ADDR_VCC   0x69

◆ C6DOFIMU14_SMDCFG_SMD_MODE_DISABLE

#define C6DOFIMU14_SMDCFG_SMD_MODE_DISABLE   0x00

◆ C6DOFIMU14_SMDCFG_SMD_MODE_LONG

#define C6DOFIMU14_SMDCFG_SMD_MODE_LONG   0x03

◆ C6DOFIMU14_SMDCFG_SMD_MODE_SHORT

#define C6DOFIMU14_SMDCFG_SMD_MODE_SHORT   0x02

◆ C6DOFIMU14_SMDCFG_WOM_INT_MODE_0

#define C6DOFIMU14_SMDCFG_WOM_INT_MODE_0   0x00

6DOF IMU 14 SMD CONFIG register settings.

SMD CONFIG register setting flags.

◆ C6DOFIMU14_SMDCFG_WOM_INT_MODE_1

#define C6DOFIMU14_SMDCFG_WOM_INT_MODE_1   0x08

◆ C6DOFIMU14_SMDCFG_WOM_MODE_0

#define C6DOFIMU14_SMDCFG_WOM_MODE_0   0x00

◆ C6DOFIMU14_SMDCFG_WOM_MODE_1

#define C6DOFIMU14_SMDCFG_WOM_MODE_1   0x04

◆ C6DOFIMU14_SPI_READ_MASK

#define C6DOFIMU14_SPI_READ_MASK   0x80

6DOF IMU 14 SPI read/write bit settings.

SPI read/write bit setting flags.

◆ C6DOFIMU14_SPI_WRITE_MASK

#define C6DOFIMU14_SPI_WRITE_MASK   0x7F

◆ C6DOFIMU14_SPR_ABORT_AND_RESET

#define C6DOFIMU14_SPR_ABORT_AND_RESET   0x08

◆ C6DOFIMU14_SPR_DMP_INIT_EN

#define C6DOFIMU14_SPR_DMP_INIT_EN   0x40

6DOF IMU 14 Signal path reset register settings.

Signal path reset register setting flags.

◆ C6DOFIMU14_SPR_DMP_MEM_RST_EN

#define C6DOFIMU14_SPR_DMP_MEM_RST_EN   0x20

◆ C6DOFIMU14_SPR_FIFO_FLUSH

#define C6DOFIMU14_SPR_FIFO_FLUSH   0x02

◆ C6DOFIMU14_SPR_TMST_STROBE

#define C6DOFIMU14_SPR_TMST_STROBE   0x04

◆ C6DOFIMU14_TMSTCFG_DELTA_DIS

#define C6DOFIMU14_TMSTCFG_DELTA_DIS   0x00

◆ C6DOFIMU14_TMSTCFG_DELTA_EN

#define C6DOFIMU14_TMSTCFG_DELTA_EN   0x04

◆ C6DOFIMU14_TMSTCFG_FSYNC_DIS

#define C6DOFIMU14_TMSTCFG_FSYNC_DIS   0x00

◆ C6DOFIMU14_TMSTCFG_FSYNC_EN

#define C6DOFIMU14_TMSTCFG_FSYNC_EN   0x02

◆ C6DOFIMU14_TMSTCFG_RES_0

#define C6DOFIMU14_TMSTCFG_RES_0   0x00

◆ C6DOFIMU14_TMSTCFG_RES_1

#define C6DOFIMU14_TMSTCFG_RES_1   0x08

◆ C6DOFIMU14_TMSTCFG_TMST_DISABLE

#define C6DOFIMU14_TMSTCFG_TMST_DISABLE   0x00

◆ C6DOFIMU14_TMSTCFG_TMST_ENABLE

#define C6DOFIMU14_TMSTCFG_TMST_ENABLE   0x01

◆ C6DOFIMU14_TMSTCFG_TO_REGS_DIS

#define C6DOFIMU14_TMSTCFG_TO_REGS_DIS   0x00

◆ C6DOFIMU14_TMSTCFG_TO_REGS_EN

#define C6DOFIMU14_TMSTCFG_TO_REGS_EN   0x10

6DOF IMU 14 TMST CONFIG register settings.

TMST CONFIG register setting flags ( Default - 0x23 ).