Settings for registers of 6DOF IMU 18 Click driver. More...

Macros
#define	C6DOFIMU18_BANK0_SEL 0x00
	6DOF IMU 18 description setting.

#define	C6DOFIMU18_BANK1_SEL 0x01

#define	C6DOFIMU18_BANK2_SEL 0x02

#define	C6DOFIMU18_BANK3_SEL 0x03

#define	C6DOFIMU18_BANK4_SEL 0x04

#define	C6DOFIMU18_SLEW_RATE_60nS 0x00
	6DOF IMU 18 communication slew rate.

#define	C6DOFIMU18_SLEW_RATE_36nS 0x01

#define	C6DOFIMU18_SLEW_RATE_18nS 0x02

#define	C6DOFIMU18_SLEW_RATE_12nS 0x03

#define	C6DOFIMU18_SLEW_RATE_6nS 0x04

#define	C6DOFIMU18_SLEW_RATE_2nS 0x05

#define	C6DOFIMU18_SPI_MODE0_MODE3 0x00
	6DOF IMU 18 SPI mode.

#define	C6DOFIMU18_SPI_MODE1_MODE2 0x01

#define	C6DOFIMU18_ENABLE_SW_RESET 0x01

#define	C6DOFIMU18_DMP_IDEL_FLAG 0x04
	6DOF IMU 18 APEX DATA 3 register masks.

#define	C6DOFIMU18_ACTIVITY_UNKNOWN 0x00

#define	C6DOFIMU18_ACTIVITY_WALK 0x01

#define	C6DOFIMU18_ACTIVITY_RUN 0x02

#define	C6DOFIMU18_ACTIVITY_MASK 0x03

#define	C6DOFIMU18_TAP_NUM_MASK 0x18

#define	C6DOFIMU18_TAP_SINGLE 0x08

#define	C6DOFIMU18_TAP_DOUBLE 0x10

#define	C6DOFIMU18_TAP_AXIS_MASK 0x06

#define	C6DOFIMU18_TAP_AXIS_X 0x00

#define	C6DOFIMU18_TAP_AXIS_Y 0x02

#define	C6DOFIMU18_TAP_AXIS_Z 0x04

#define	C6DOFIMU18_TAP_DIR_MASK 0x01

#define	C6DOFIMU18_TAP_DIR_POSITIVE 0x00

#define	C6DOFIMU18_TAP_DIR_NEGATIVE 0x01

#define	C6DOFIMU18_INT_INT2_MODE_PULSED 0x00
	6DOF IMU 18 INT CONFIG register masks.

#define	C6DOFIMU18_INT_INT2_MODE_LATCHED 0x20

#define	C6DOFIMU18_INT_INT2_OPEN_DRAIN 0x00

#define	C6DOFIMU18_INT_INT2_PUSH_PULL 0x10

#define	C6DOFIMU18_INT_INT2_ACTIVE_LOW 0x00

#define	C6DOFIMU18_INT_INT2_ACTIVE_HIGH 0x08

#define	C6DOFIMU18_INT_INT1_MODE_PULSED 0x00

#define	C6DOFIMU18_INT_INT1_MODE_LATCHED 0x04

#define	C6DOFIMU18_INT_INT1_OPEN_DRAIN 0x00

#define	C6DOFIMU18_INT_INT1_PUSH_PULL 0x02

#define	C6DOFIMU18_INT_INT1_ACTIVE_LOW 0x00

#define	C6DOFIMU18_INT_INT1_ACTIVE_HIGH 0x01

#define	C6DOFIMU18_INT_CONFIG_MASK 0x3F

#define	C6DOFIMU18_DRDY_INT_CLR_ON_STATUS_READ 0x00
	6DOF IMU 18 INT CONFIG 0 register masks.

#define	C6DOFIMU18_DRDY_INT_CLR_FIFO_READ 0x20

#define	C6DOFIMU18_DRDY_INT_CLR_STATUS_AND_REG 0x30

#define	C6DOFIMU18_FIFO_INT_CLR_ON_STATUS_READ 0x00

#define	C6DOFIMU18_FIFO_INT_CLR_FIFO_READ 0x80

#define	C6DOFIMU18_FIFO_INT_CLR_STATUS_AND_REG 0xc0

#define	C6DOFIMU18_FIFO_FULL_CLR_ON_STATUS_READ 0x00

#define	C6DOFIMU18_FIFO_FULL_CLR_FIFO_READ 0x02

#define	C6DOFIMU18_FIFO_FULL_CLR_STATUS_AND_REG 0x03

#define	C6DOFIMU18_INT_TPULSE_100uS 0x00
	6DOF IMU 18 INT CONFIG 1 register masks.

#define	C6DOFIMU18_INT_TPULSE_8uS 0x40

#define	C6DOFIMU18_INT_TDEASSERT_DISABLE 0x20

#define	C6DOFIMU18_INT_ASYNC_RESET_DISABLE 0x10

#define	C6DOFIMU18_INT_ASYNC_RESET_ENABLE 0x00

#define	C6DOFIMU18_INT_CONFIG1_MASK 0x70

#define	C6DOFIMU18_INT_UI_FSYNC_INT1_EN 0x40
	6DOF IMU 18 INT SOURCE 0 register masks.

#define	C6DOFIMU18_INT_PLL_RDY_INT1_EN 0x20

#define	C6DOFIMU18_INT_RESET_DONE_INT1_EN 0x10

#define	C6DOFIMU18_INT_UI_DRDY_INT1_EN 0x08

#define	C6DOFIMU18_INT_FIFO_THS_INT1_EN 0x04

#define	C6DOFIMU18_INT_FIFO_FULL_INT1_EN 0x02

#define	C6DOFIMU18_INT_UI_AGC_RDY_INT1_EN 0x01

#define	C6DOFIMU18_INT_SOURCE0_MASK 0x7F

#define	C6DOFIMU18_SMD_INT1_EN 0x08
	6DOF IMU 18 INT SOURCE 1 register masks.

#define	C6DOFIMU18_WOM_Z_INT1_EN 0x04

#define	C6DOFIMU18_WOM_Y_INT1_EN 0x02

#define	C6DOFIMU18_WOM_X_INT1_EN 0x01

#define	C6DOFIMU18_INT_SOURCE1_MASK 0x0F

#define	C6DOFIMU18_INT_UI_FSYNC_INT2_EN 0x40
	6DOF IMU 18 INT SOURCE 3 register masks.

#define	C6DOFIMU18_INT_PLL_RDY_INT2_EN 0x20

#define	C6DOFIMU18_INT_RESET_DONE_INT2_EN 0x10

#define	C6DOFIMU18_INT_UI_DRDY_INT2_EN 0x08

#define	C6DOFIMU18_INT_FIFO_THS_INT2_EN 0x04

#define	C6DOFIMU18_INT_FIFO_FULL_INT2_EN 0x02

#define	C6DOFIMU18_INT_UI_AGC_RDY_INT2_EN 0x01

#define	C6DOFIMU18_INT_SOURCE3_MASK 0x7F

#define	C6DOFIMU18_SMD_INT2_EN 0x08
	6DOF IMU 18 INT SOURCE 4 register masks.

#define	C6DOFIMU18_WOM_Z_INT2_EN 0x04

#define	C6DOFIMU18_WOM_Y_INT2_EN 0x02

#define	C6DOFIMU18_WOM_X_INT2_EN 0x01

#define	C6DOFIMU18_INT_SOURCE4_MASK 0x0F

#define	C6DOFIMU18_INT_SOURCE6_STEP_DET_INT1_EN 0x20
	6DOF IMU 18 INT SOURCE 6 register masks.

#define	C6DOFIMU18_INT_SOURCE6_STEP_CNT_INT1_EN 0x10

#define	C6DOFIMU18_INT_SOURCE6_TILT_DET_INT1_EN 0x08

#define	C6DOFIMU18_INT_SOURCE6_TAP_DET_INT1_EN 0x01

#define	C6DOFIMU18_INT_SOURCE6_MASK 0x39

#define	C6DOFIMU18_INT_SOURCE7_STEP_DET_INT2_EN 0x20
	6DOF IMU 18 INT SOURCE 7 register masks.

#define	C6DOFIMU18_INT_SOURCE7_STEP_CNT_INT2_EN 0x10

#define	C6DOFIMU18_INT_SOURCE7_TILT_DET_INT2_EN 0x08

#define	C6DOFIMU18_INT_SOURCE7_TAP_DET_INT2_EN 0x01

#define	C6DOFIMU18_INT_SOURCE7_MASK 0x39

#define	C6DOFIMU18_UI_FSYNC_INT_FLAG 0x40
	6DOF IMU 18 INT STATUS register masks.

#define	C6DOFIMU18_PLL_DONE_INT_FLAG 0x20

#define	C6DOFIMU18_RESET_DONE_INT_FLAG 0x10

#define	C6DOFIMU18_DATA_RDY_INT_FLAG 0x08

#define	C6DOFIMU18_FIFO_THS_INT_FLAG 0x04

#define	C6DOFIMU18_FIFO_FULL_INT_FLAG 0x02

#define	C6DOFIMU18_AGC_RDY_INT_FLAG 0x01

#define	C6DOFIMU18_SMD_INT_FLAG 0x08
	6DOF IMU 18 INT STATUS 2 register masks.

#define	C6DOFIMU18_WOM_Z_INT_FLAG 0x04

#define	C6DOFIMU18_WOM_Y_INT_FLAG 0x02

#define	C6DOFIMU18_WOM_X_INT_FLAG 0x01

#define	C6DOFIMU18_STEP_DET_INT_FLAG 0x10
	6DOF IMU 18 INT STATUS 3 register masks.

#define	C6DOFIMU18_STEP_CNT_OVF_INT_FLAG 0x08

#define	C6DOFIMU18_TILT_DET_INT_FLAG 0x04

#define	C6DOFIMU18_SLEEP_INT_FLAG 0x02

#define	C6DOFIMU18_TAP_DET_INT_FLAG 0x01

#define	C6DOFIMU18_FIFO_HLD_LAST_DATA_EN 0x80
	6DOF IMU 18 INTF CONFIG 0 register masks.

#define	C6DOFIMU18_FIFO_COUNT_REC 0x40

#define	C6DOFIMU18_FIFO_COUNT_ENDIAN 0x20

#define	C6DOFIMU18_FIFO_DATA_ENDIAN 0x10

#define	C6DOFIMU18_UI_SIFS_CFG_DISABLE_I2C 0x03

#define	C6DOFIMU18_UI_SIFS_CFG_DISABLE_SPI 0x02

#define	C6DOFIMU18_INTF_CONFIG0_MASK 0xF3

#define	C6DOFIMU18_ACCEL_LP_CLK_SEL_WAKE_UP_OSC 0x00
	6DOF IMU 18 INTF CONFIG 1 register masks.

#define	C6DOFIMU18_ACCEL_LP_CLK_SEL_RC_OSC 0x08

#define	C6DOFIMU18_ACCEL_CLKSEL_RC 0x00

#define	C6DOFIMU18_ACCEL_CLKSEL_PLL_OR_RC 0x01

#define	C6DOFIMU18_ACCEL_CLKSEL_DISABLE 0x03

#define	C6DOFIMU18_SPI_3WIRE 0x00
	6DOF IMU 18 INTF CONFIG 4 register masks.

#define	C6DOFIMU18_SPI_4WIRE 0x02

#define	C6DOFIMU18_PIN9_INT2 0x00
	6DOF IMU 18 INTF CONFIG 5 register masks.

#define	C6DOFIMU18_PIN9_FSYNC 0x01

#define	C6DOFIMU18_DMP_INIT_EN 0x40
	6DOF IMU 18 SIGNAL PATH RESET register masks.

#define	C6DOFIMU18_DMP_MEM_RESET_EN 0x20

#define	C6DOFIMU18_ABORT_AND_RESET 0x08

#define	C6DOFIMU18_TMST_STROBE 0x04

#define	C6DOFIMU18_FIFO_FLUSH 0x02

#define	C6DOFIMU18_PWR_TEMP_DIS 0x20
	6DOF IMU 18 PWR MGMT0 register masks.

#define	C6DOFIMU18_PWR_IDLE_OFF 0x10

#define	C6DOFIMU18_PWR_GYRO_MODE_OFF 0x00

#define	C6DOFIMU18_PWR_GYRO_STANDBY 0x04

#define	C6DOFIMU18_PWR_GYRO_LN_MODE 0x0C

#define	C6DOFIMU18_PWR_ACCEL_MODE_OFF 0x00

#define	C6DOFIMU18_PWR_ACCEL_LP_MODE 0x02

#define	C6DOFIMU18_PWR_ACCEL_LN_MODE 0x03

#define	C6DOFIMU18_GYRO_FS_SEL_2000DPS 0x00
	6DOF IMU 18 GYRO CONFIG 0 register masks.

#define	C6DOFIMU18_GYRO_FS_SEL_1000DPS 0x20

#define	C6DOFIMU18_GYRO_FS_SEL_500DPS 0x40

#define	C6DOFIMU18_GYRO_FS_SEL_250DPS 0x60

#define	C6DOFIMU18_GYRO_FS_SEL_125DPS 0x80

#define	C6DOFIMU18_GYRO_FS_SEL_62DPS 0xA0

#define	C6DOFIMU18_GYRO_FS_SEL_32DPS 0xC0

#define	C6DOFIMU18_GYRO_FS_SEL_15DPS 0xE0

#define	C6DOFIMU18_GYRO_FS_SEL_MASK 0xE0

#define	C6DOFIMU18_GYRO_ODR_8kHz 0x03

#define	C6DOFIMU18_GYRO_ODR_4kHz 0x04

#define	C6DOFIMU18_GYRO_ODR_2kHz 0x05

#define	C6DOFIMU18_GYRO_ODR_1kHz 0x06

#define	C6DOFIMU18_GYRO_ODR_200Hz 0x07

#define	C6DOFIMU18_GYRO_ODR_100Hz 0x08

#define	C6DOFIMU18_GYRO_ODR_50Hz 0x09

#define	C6DOFIMU18_GYRO_ODR_25Hz 0x0A

#define	C6DOFIMU18_GYRO_ODR_12Hz 0x0B

#define	C6DOFIMU18_GYRO_ODR_500Hz 0x0F

#define	C6DOFIMU18_GYRO_ODR_MASK 0x0F

#define	C6DOFIMU18_GYRO_ODR_MASK 0x0F

#define	C6DOFIMU18_TEMP_FILT_BW_4kHz 0x00
	6DOF IMU 18 GYRO CONFIG 1 register masks.

#define	C6DOFIMU18_TEMP_FILT_BW_170Hz 0x20

#define	C6DOFIMU18_TEMP_FILT_BW_82Hz 0x40

#define	C6DOFIMU18_TEMP_FILT_BW_40Hz 0x60

#define	C6DOFIMU18_TEMP_FILT_BW_20Hz 0x80

#define	C6DOFIMU18_TEMP_FILT_BW_10Hz 0xA0

#define	C6DOFIMU18_TEMP_FILT_BW_5Hz_0 0xC0

#define	C6DOFIMU18_TEMP_FILT_BW_5Hz_1 0xE0

#define	C6DOFIMU18_GYRO_UI_FILT_ORD_1st 0x00

#define	C6DOFIMU18_GYRO_UI_FILT_ORD_2nd 0x04

#define	C6DOFIMU18_GYRO_UI_FILT_ORD_3rd 0x08

#define	C6DOFIMU18_GYRO_UI_FILT_ORD_MASK 0x0C

#define	C6DOFIMU18_GYRO_DEC2_M2_ORD_3rd 0x02

#define	C6DOFIMU18_GYRO_CONFIG1_MASK 0xEF

#define	C6DOFIMU18_ACCEL_FS_SEL_16G 0x00
	6DOF IMU 18 ACCEL CONFIG 0 register masks.

#define	C6DOFIMU18_ACCEL_FS_SEL_8G 0x20

#define	C6DOFIMU18_ACCEL_FS_SEL_4G 0x40

#define	C6DOFIMU18_ACCEL_FS_SEL_2G 0x60

#define	C6DOFIMU18_ACCEL_FS_SEL_MASK 0x60

#define	C6DOFIMU18_ACCEL_ODR_8kHz_LN 0x03

#define	C6DOFIMU18_ACCEL_ODR_4kHz_LN 0x04

#define	C6DOFIMU18_ACCEL_ODR_2kHz_LN 0x05

#define	C6DOFIMU18_ACCEL_ODR_1kHz_LN 0x06

#define	C6DOFIMU18_ACCEL_ODR_200Hz_LP_LN 0x07

#define	C6DOFIMU18_ACCEL_ODR_100Hz_LP_LN 0x08

#define	C6DOFIMU18_ACCEL_ODR_50Hz_LP_LN 0x09

#define	C6DOFIMU18_ACCEL_ODR_25Hz_LP_LN 0x0A

#define	C6DOFIMU18_ACCEL_ODR_12Hz_LP_LN 0x0B

#define	C6DOFIMU18_ACCEL_ODR_6Hz_LP 0x0C

#define	C6DOFIMU18_ACCEL_ODR_3Hz_LP 0x0D

#define	C6DOFIMU18_ACCEL_ODR_1Hz_LP 0x0E

#define	C6DOFIMU18_ACCEL_ODR_500Hz_LP_LN 0x0F

#define	C6DOFIMU18_ACCEL_ODR_MASK 0x0F

#define	C6DOFIMU18_ACCEL_UI_FILT_ORD_1st 0x00
	6DOF IMU 18 ACCEL CONFIG 1 register masks.

#define	C6DOFIMU18_ACCEL_UI_FILT_ORD_2nd 0x08

#define	C6DOFIMU18_ACCEL_UI_FILT_ORD_3rd 0x10

#define	C6DOFIMU18_ACCEL_UI_FILT_ORD_MASK 0x18

#define	C6DOFIMU18_ACCEL_DEC2_M2_ORD_3rd 0x04

#define	C6DOFIMU18_TMST_TO_REGS_EN 0x10
	6DOF IMU 18 TMST CONFIG register masks.

#define	C6DOFIMU18_TMST_RES 0x08

#define	C6DOFIMU18_TMST_DELTA_EN 0x04

#define	C6DOFIMU18_TMST_FSYNC_EN 0x02

#define	C6DOFIMU18_TMST_EN 0x01

#define	C6DOFIMU18_TMST_MASK 0x1F

#define	C6DOFIMU18_FIFO_BYPASS 0x00
	6DOF IMU 18 FIFO CONFIG register masks.

#define	C6DOFIMU18_FIFO_STREAM_TO_FIFO 0x40

#define	C6DOFIMU18_FIFO_STOP_ON_FULL 0x80

#define	C6DOFIMU18_FIFO_CONFIG_MASK 0xC0

#define	C6DOFIMU18_FIFO_RESUME_PARTIAL_RD 0x40
	6DOF IMU 18 FIFO CONFIG 1 register masks.

#define	C6DOFIMU18_FIFO_WM_GT_TH 0x20

#define	C6DOFIMU18_FIFO_TMST_FSYNC_EN 0x08

#define	C6DOFIMU18_FIFO_TEMP_EN 0x04

#define	C6DOFIMU18_FIFO_GYRO_EN 0x02

#define	C6DOFIMU18_FIFO_ACCEL_EN 0x01

#define	C6DOFIMU18_DO_NOT_TAG_FSYNC 0x00
	6DOF IMU 18 FSYNC CONFIG register masks.

#define	C6DOFIMU18_FSYNC_TAG_TEMP_OUT_LSB 0x10

#define	C6DOFIMU18_FSYNC_GYRO_XOUT_LSB 0x20

#define	C6DOFIMU18_FSYNC_GYRO_YOUT_LSB 0x30

#define	C6DOFIMU18_FSYNC_GYRO_ZOUT_LSB 0x40

#define	C6DOFIMU18_FSYNC_ACCEL_XOUT_LSB 0x50

#define	C6DOFIMU18_FSYNC_ACCEL_YOUT_LSB 0x60

#define	C6DOFIMU18_FSYNC_ACCEL_ZOUT_LSB 0x70

#define	C6DOFIMU18_FSYNC_UI_SEL_MASK 0x70

#define	C6DOFIMU18_FSYNC_UI_FLAG_CLEAR_SEL 0x02

#define	C6DOFIMU18_FSYNC_POLARITY_RISING_EGDE 0x01

#define	C6DOFIMU18_FSYNC_POLARITY_FALLING_EGDE 0x01

#define	C6DOFIMU18_DMP_POVER_SAVE_EN 0x80
	6DOF IMU 18 APEX CONFIG 0 register masks.

#define	C6DOFIMU18_TAP_ENABLE 0x40

#define	C6DOFIMU18_PED_ENABLE 0x20

#define	C6DOFIMU18_TILT_ENABLE 0x10

#define	C6DOFIMU18_R2W_ENABLE 0x08

#define	C6DOFIMU18_DMP_ODR_25Hz 0x00

#define	C6DOFIMU18_DMP_ODR_50Hz 0x02

#define	C6DOFIMU18_LOW_ENERGY_AMP_TH_SEL 0xA0
	6DOF IMU 18 APEX CONFIG 1 register masks.

#define	C6DOFIMU18_DMP_POVER_SAVE_TIME_0S 0x00

#define	C6DOFIMU18_DMP_POVER_SAVE_TIME_4S 0x01

#define	C6DOFIMU18_DMP_POWER_SAVE_TIME_8S 0x02

#define	C6DOFIMU18_DMP_POWER_SAVE_TIME_12S 0x03

#define	C6DOFIMU18_DMP_POWER_SAVE_TIME_16S 0x04

#define	C6DOFIMU18_DMP_POWER_SAVE_TIME_20S 0x05

#define	C6DOFIMU18_DMP_POWER_SAVE_TIME_24S 0x06

#define	C6DOFIMU18_DMP_POWER_SAVE_TIME_28S 0x07

#define	C6DOFIMU18_DMP_POWER_SAVE_TIME_32S 0x08

#define	C6DOFIMU18_DMP_POWER_SAVE_TIME_36S 0x09

#define	C6DOFIMU18_DMP_POWER_SAVE_TIME_40S 0x0A

#define	C6DOFIMU18_DMP_POWER_SAVE_TIME_44S 0x0B

#define	C6DOFIMU18_DMP_POWER_SAVE_TIME_48S 0x0C

#define	C6DOFIMU18_DMP_POWER_SAVE_TIME_52S 0x0D

#define	C6DOFIMU18_DMP_POWER_SAVE_TIME_56S 0x0E

#define	C6DOFIMU18_DMP_POWER_SAVE_TIME_60S 0x0F

#define	C6DOFIMU18_PED_AMP_TH_SEL 0x80
	6DOF IMU 18 APEX CONFIG 2 register masks.

#define	C6DOFIMU18_PED_STEP_CNT_TH_0_STEPS 0x00

#define	C6DOFIMU18_PED_STEP_CNT_TH_1_STEPS 0x01

#define	C6DOFIMU18_PED_STEP_CNT_TH_2_STEPS 0x02

#define	C6DOFIMU18_PED_STEP_CNT_TH_3_STEPS 0x03

#define	C6DOFIMU18_PED_STEP_CNT_TH_4_STEPS 0x04

#define	C6DOFIMU18_PED_STEP_CNT_TH_5_STEPS 0x05

#define	C6DOFIMU18_PED_STEP_CNT_TH_6_STEPS 0x06

#define	C6DOFIMU18_PED_STEP_CNT_TH_7_STEPS 0x07

#define	C6DOFIMU18_PED_STEP_CNT_TH_8_STEPS 0x08

#define	C6DOFIMU18_PED_STEP_CNT_TH_9_STEPS 0x09

#define	C6DOFIMU18_PED_STEP_CNT_TH_10_STEPS 0x0A

#define	C6DOFIMU18_PED_STEP_CNT_TH_11_STEPS 0x0B

#define	C6DOFIMU18_PED_STEP_CNT_TH_12_STEPS 0x0C

#define	C6DOFIMU18_PED_STEP_CNT_TH_13_STEPS 0x0D

#define	C6DOFIMU18_PED_STEP_CNT_TH_14_STEPS 0x0E

#define	C6DOFIMU18_PED_STEP_CNT_TH_15_STEPS 0x0F

#define	C6DOFIMU18_PED_STEP_CNT_TH_MASK 0x0F

#define	C6DOFIMU18_PED_STEP_DET_TH_0_STEPS 0x00
	6DOF IMU 18 APEX CONFIG 3 register masks.

#define	C6DOFIMU18_PED_STEP_DET_TH_1_STEPS 0x20

#define	C6DOFIMU18_PED_STEP_DET_TH_2_STEPS 0x40

#define	C6DOFIMU18_PED_STEP_DET_TH_3_STEPS 0x60

#define	C6DOFIMU18_PED_STEP_DET_TH_4_STEPS 0x80

#define	C6DOFIMU18_PED_STEP_DET_TH_5_STEPS 0xA0

#define	C6DOFIMU18_PED_STEP_DET_TH_6_STEPS 0xC0

#define	C6DOFIMU18_PED_STEP_DET_TH_7_STEPS 0xE0

#define	C6DOFIMU18_PED_SB_TIMER_TH_0_SAMPLES 0x00

#define	C6DOFIMU18_PED_SB_TIMER_TH_1_SAMPLES 0x04

#define	C6DOFIMU18_PED_SB_TIMER_TH_2_SAMPLES 0x08

#define	C6DOFIMU18_PED_SB_TIMER_TH_3_SAMPLES 0x0C

#define	C6DOFIMU18_PED_SB_TIMER_TH_4_SAMPLES 0x10

#define	C6DOFIMU18_PED_SB_TIMER_TH_5_SAMPLES 0x14

#define	C6DOFIMU18_PED_SB_TIMER_TH_6_SAMPLES 0x18

#define	C6DOFIMU18_PED_SB_TIMER_TH_7_SAMPLES 0x1C

#define	C6DOFIMU18_PED_HI_EN_TH_SEL 0x01

#define	C6DOFIMU18_TILT_WAIT_TIME_0S 0x00
	6DOF IMU 18 APEX CONFIG 4 register masks.

#define	C6DOFIMU18_TILT_WAIT_TIME_2S 0x40

#define	C6DOFIMU18_TILT_WAIT_TIME_4S 0x80

#define	C6DOFIMU18_TILT_WAIT_TIME_6S 0xC0

#define	C6DOFIMU18_TILT_WAIT_TIME_MASK 0xC0

#define	C6DOFIMU18_SLEEP_TIME_OUT_1s28 0x00

#define	C6DOFIMU18_SLEEP_TIME_OUT_2s56 0x08

#define	C6DOFIMU18_SLEEP_TIME_OUT_3s84 0x10

#define	C6DOFIMU18_SLEEP_TIME_OUT_5s12 0x18

#define	C6DOFIMU18_SLEEP_TIME_OUT_6s4 0x20

#define	C6DOFIMU18_SLEEP_TIME_OUT_7s68 0x28

#define	C6DOFIMU18_SLEEP_TIME_OUT_8s96 0x30

#define	C6DOFIMU18_SLEEP_TIME_OUT_10s24 0x38

#define	C6DOFIMU18_SLEEP_TIME_OUT_MASK 0x38

#define	C6DOFIMU18_TAP_MIN_JERK_THR 0x44
	6DOF IMU 18 APEX CONFIG 7 register masks.

#define	C6DOFIMU18_TAP_MAX_OEAK_TOL 0x01

#define	C6DOFIMU18_TAP_TMAX 0x20
	6DOF IMU 18 APEX CONFIG 8 register masks.

#define	C6DOFIMU18_TAP_TAVG 0x08

#define	C6DOFIMU18_TAP_TMIN 0x03

#define	C6DOFIMU18_SENSITIVITY_MODE_HIGH_PERF 0x00
	6DOF IMU 18 APEX CONFIG 9 register masks.

#define	C6DOFIMU18_SENSITIVITY_MODE_SLOW_WALK 0x01

#define	C6DOFIMU18_TEMPERATURE_DIV 132.48
	6DOF IMU 18 Temperature calculation values.

#define	C6DOFIMU18_TEMPERATURE_ADD 25

#define	C6DOFIMU18_WHO_AM_I_VALUE 0x42
	6DOF IMU 18 who am i register values.

#define	C6DOFIMU18_DEVICE_ADDRESS_GND 0x68
	6DOF IMU 18 device address setting.

#define	C6DOFIMU18_DEVICE_ADDRESS_VCC 0x69

#define	C6DOFIMU18_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE
	Data sample selection.

#define	C6DOFIMU18_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE

Detailed Description

Settings for registers of 6DOF IMU 18 Click driver.

Macro Definition Documentation

◆ C6DOFIMU18_ABORT_AND_RESET

#define C6DOFIMU18_ABORT_AND_RESET 0x08

◆ C6DOFIMU18_ACCEL_CLKSEL_DISABLE

#define C6DOFIMU18_ACCEL_CLKSEL_DISABLE 0x03

◆ C6DOFIMU18_ACCEL_CLKSEL_PLL_OR_RC

#define C6DOFIMU18_ACCEL_CLKSEL_PLL_OR_RC 0x01

◆ C6DOFIMU18_ACCEL_CLKSEL_RC

#define C6DOFIMU18_ACCEL_CLKSEL_RC 0x00

◆ C6DOFIMU18_ACCEL_DEC2_M2_ORD_3rd

#define C6DOFIMU18_ACCEL_DEC2_M2_ORD_3rd 0x04

◆ C6DOFIMU18_ACCEL_FS_SEL_16G

#define C6DOFIMU18_ACCEL_FS_SEL_16G 0x00

6DOF IMU 18 ACCEL CONFIG 0 register masks.

Specified setting for ACCEL CONFIG 0 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_ACCEL_FS_SEL_2G

#define C6DOFIMU18_ACCEL_FS_SEL_2G 0x60

◆ C6DOFIMU18_ACCEL_FS_SEL_4G

#define C6DOFIMU18_ACCEL_FS_SEL_4G 0x40

◆ C6DOFIMU18_ACCEL_FS_SEL_8G

#define C6DOFIMU18_ACCEL_FS_SEL_8G 0x20

◆ C6DOFIMU18_ACCEL_FS_SEL_MASK

#define C6DOFIMU18_ACCEL_FS_SEL_MASK 0x60

◆ C6DOFIMU18_ACCEL_LP_CLK_SEL_RC_OSC

#define C6DOFIMU18_ACCEL_LP_CLK_SEL_RC_OSC 0x08

◆ C6DOFIMU18_ACCEL_LP_CLK_SEL_WAKE_UP_OSC

#define C6DOFIMU18_ACCEL_LP_CLK_SEL_WAKE_UP_OSC 0x00

6DOF IMU 18 INTF CONFIG 1 register masks.

Specified setting for INTF CONFIG 1 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_ACCEL_ODR_100Hz_LP_LN

#define C6DOFIMU18_ACCEL_ODR_100Hz_LP_LN 0x08

◆ C6DOFIMU18_ACCEL_ODR_12Hz_LP_LN

#define C6DOFIMU18_ACCEL_ODR_12Hz_LP_LN 0x0B

◆ C6DOFIMU18_ACCEL_ODR_1Hz_LP

#define C6DOFIMU18_ACCEL_ODR_1Hz_LP 0x0E

◆ C6DOFIMU18_ACCEL_ODR_1kHz_LN

#define C6DOFIMU18_ACCEL_ODR_1kHz_LN 0x06

◆ C6DOFIMU18_ACCEL_ODR_200Hz_LP_LN

#define C6DOFIMU18_ACCEL_ODR_200Hz_LP_LN 0x07

◆ C6DOFIMU18_ACCEL_ODR_25Hz_LP_LN

#define C6DOFIMU18_ACCEL_ODR_25Hz_LP_LN 0x0A

◆ C6DOFIMU18_ACCEL_ODR_2kHz_LN

#define C6DOFIMU18_ACCEL_ODR_2kHz_LN 0x05

◆ C6DOFIMU18_ACCEL_ODR_3Hz_LP

#define C6DOFIMU18_ACCEL_ODR_3Hz_LP 0x0D

◆ C6DOFIMU18_ACCEL_ODR_4kHz_LN

#define C6DOFIMU18_ACCEL_ODR_4kHz_LN 0x04

◆ C6DOFIMU18_ACCEL_ODR_500Hz_LP_LN

#define C6DOFIMU18_ACCEL_ODR_500Hz_LP_LN 0x0F

◆ C6DOFIMU18_ACCEL_ODR_50Hz_LP_LN

#define C6DOFIMU18_ACCEL_ODR_50Hz_LP_LN 0x09

◆ C6DOFIMU18_ACCEL_ODR_6Hz_LP

#define C6DOFIMU18_ACCEL_ODR_6Hz_LP 0x0C

◆ C6DOFIMU18_ACCEL_ODR_8kHz_LN

#define C6DOFIMU18_ACCEL_ODR_8kHz_LN 0x03

◆ C6DOFIMU18_ACCEL_ODR_MASK

#define C6DOFIMU18_ACCEL_ODR_MASK 0x0F

◆ C6DOFIMU18_ACCEL_UI_FILT_ORD_1st

#define C6DOFIMU18_ACCEL_UI_FILT_ORD_1st 0x00

6DOF IMU 18 ACCEL CONFIG 1 register masks.

Specified setting for ACCEL CONFIG 1 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_ACCEL_UI_FILT_ORD_2nd

#define C6DOFIMU18_ACCEL_UI_FILT_ORD_2nd 0x08

◆ C6DOFIMU18_ACCEL_UI_FILT_ORD_3rd

#define C6DOFIMU18_ACCEL_UI_FILT_ORD_3rd 0x10

◆ C6DOFIMU18_ACCEL_UI_FILT_ORD_MASK

#define C6DOFIMU18_ACCEL_UI_FILT_ORD_MASK 0x18

◆ C6DOFIMU18_ACTIVITY_MASK

#define C6DOFIMU18_ACTIVITY_MASK 0x03

◆ C6DOFIMU18_ACTIVITY_RUN

#define C6DOFIMU18_ACTIVITY_RUN 0x02

◆ C6DOFIMU18_ACTIVITY_UNKNOWN

#define C6DOFIMU18_ACTIVITY_UNKNOWN 0x00

◆ C6DOFIMU18_ACTIVITY_WALK

#define C6DOFIMU18_ACTIVITY_WALK 0x01

◆ C6DOFIMU18_AGC_RDY_INT_FLAG

#define C6DOFIMU18_AGC_RDY_INT_FLAG 0x01

◆ C6DOFIMU18_BANK0_SEL

#define C6DOFIMU18_BANK0_SEL 0x00

6DOF IMU 18 description setting.

Specified setting for description of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_BANK1_SEL

#define C6DOFIMU18_BANK1_SEL 0x01

◆ C6DOFIMU18_BANK2_SEL

#define C6DOFIMU18_BANK2_SEL 0x02

◆ C6DOFIMU18_BANK3_SEL

#define C6DOFIMU18_BANK3_SEL 0x03

◆ C6DOFIMU18_BANK4_SEL

#define C6DOFIMU18_BANK4_SEL 0x04

◆ C6DOFIMU18_DATA_RDY_INT_FLAG

#define C6DOFIMU18_DATA_RDY_INT_FLAG 0x08

◆ C6DOFIMU18_DEVICE_ADDRESS_GND

#define C6DOFIMU18_DEVICE_ADDRESS_GND 0x68

6DOF IMU 18 device address setting.

Specified setting for device slave address selection of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_DEVICE_ADDRESS_VCC

#define C6DOFIMU18_DEVICE_ADDRESS_VCC 0x69

◆ C6DOFIMU18_DMP_IDEL_FLAG

#define C6DOFIMU18_DMP_IDEL_FLAG 0x04

6DOF IMU 18 APEX DATA 3 register masks.

Specified setting for APEX DATA 3 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_DMP_INIT_EN

#define C6DOFIMU18_DMP_INIT_EN 0x40

6DOF IMU 18 SIGNAL PATH RESET register masks.

Specified setting for SIGNAL PATH RESET register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_DMP_MEM_RESET_EN

#define C6DOFIMU18_DMP_MEM_RESET_EN 0x20

◆ C6DOFIMU18_DMP_ODR_25Hz

#define C6DOFIMU18_DMP_ODR_25Hz 0x00

◆ C6DOFIMU18_DMP_ODR_50Hz

#define C6DOFIMU18_DMP_ODR_50Hz 0x02

◆ C6DOFIMU18_DMP_POVER_SAVE_EN

#define C6DOFIMU18_DMP_POVER_SAVE_EN 0x80

6DOF IMU 18 APEX CONFIG 0 register masks.

Specified setting for APEX CONFIG 0 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_DMP_POVER_SAVE_TIME_0S

#define C6DOFIMU18_DMP_POVER_SAVE_TIME_0S 0x00

◆ C6DOFIMU18_DMP_POVER_SAVE_TIME_4S

#define C6DOFIMU18_DMP_POVER_SAVE_TIME_4S 0x01

◆ C6DOFIMU18_DMP_POWER_SAVE_TIME_12S

#define C6DOFIMU18_DMP_POWER_SAVE_TIME_12S 0x03

◆ C6DOFIMU18_DMP_POWER_SAVE_TIME_16S

#define C6DOFIMU18_DMP_POWER_SAVE_TIME_16S 0x04

◆ C6DOFIMU18_DMP_POWER_SAVE_TIME_20S

#define C6DOFIMU18_DMP_POWER_SAVE_TIME_20S 0x05

◆ C6DOFIMU18_DMP_POWER_SAVE_TIME_24S

#define C6DOFIMU18_DMP_POWER_SAVE_TIME_24S 0x06

◆ C6DOFIMU18_DMP_POWER_SAVE_TIME_28S

#define C6DOFIMU18_DMP_POWER_SAVE_TIME_28S 0x07

◆ C6DOFIMU18_DMP_POWER_SAVE_TIME_32S

#define C6DOFIMU18_DMP_POWER_SAVE_TIME_32S 0x08

◆ C6DOFIMU18_DMP_POWER_SAVE_TIME_36S

#define C6DOFIMU18_DMP_POWER_SAVE_TIME_36S 0x09

◆ C6DOFIMU18_DMP_POWER_SAVE_TIME_40S

#define C6DOFIMU18_DMP_POWER_SAVE_TIME_40S 0x0A

◆ C6DOFIMU18_DMP_POWER_SAVE_TIME_44S

#define C6DOFIMU18_DMP_POWER_SAVE_TIME_44S 0x0B

◆ C6DOFIMU18_DMP_POWER_SAVE_TIME_48S

#define C6DOFIMU18_DMP_POWER_SAVE_TIME_48S 0x0C

◆ C6DOFIMU18_DMP_POWER_SAVE_TIME_52S

#define C6DOFIMU18_DMP_POWER_SAVE_TIME_52S 0x0D

◆ C6DOFIMU18_DMP_POWER_SAVE_TIME_56S

#define C6DOFIMU18_DMP_POWER_SAVE_TIME_56S 0x0E

◆ C6DOFIMU18_DMP_POWER_SAVE_TIME_60S

#define C6DOFIMU18_DMP_POWER_SAVE_TIME_60S 0x0F

◆ C6DOFIMU18_DMP_POWER_SAVE_TIME_8S

#define C6DOFIMU18_DMP_POWER_SAVE_TIME_8S 0x02

◆ C6DOFIMU18_DO_NOT_TAG_FSYNC

#define C6DOFIMU18_DO_NOT_TAG_FSYNC 0x00

6DOF IMU 18 FSYNC CONFIG register masks.

Specified setting for FSYNC CONFIG register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_DRDY_INT_CLR_FIFO_READ

#define C6DOFIMU18_DRDY_INT_CLR_FIFO_READ 0x20

◆ C6DOFIMU18_DRDY_INT_CLR_ON_STATUS_READ

#define C6DOFIMU18_DRDY_INT_CLR_ON_STATUS_READ 0x00

6DOF IMU 18 INT CONFIG 0 register masks.

Specified setting for INT CONFIG 0 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_DRDY_INT_CLR_STATUS_AND_REG

#define C6DOFIMU18_DRDY_INT_CLR_STATUS_AND_REG 0x30

◆ C6DOFIMU18_ENABLE_SW_RESET

#define C6DOFIMU18_ENABLE_SW_RESET 0x01

◆ C6DOFIMU18_FIFO_ACCEL_EN

#define C6DOFIMU18_FIFO_ACCEL_EN 0x01

◆ C6DOFIMU18_FIFO_BYPASS

#define C6DOFIMU18_FIFO_BYPASS 0x00

6DOF IMU 18 FIFO CONFIG register masks.

Specified setting for FIFO CONFIG register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_FIFO_CONFIG_MASK

#define C6DOFIMU18_FIFO_CONFIG_MASK 0xC0

◆ C6DOFIMU18_FIFO_COUNT_ENDIAN

#define C6DOFIMU18_FIFO_COUNT_ENDIAN 0x20

◆ C6DOFIMU18_FIFO_COUNT_REC

#define C6DOFIMU18_FIFO_COUNT_REC 0x40

◆ C6DOFIMU18_FIFO_DATA_ENDIAN

#define C6DOFIMU18_FIFO_DATA_ENDIAN 0x10

◆ C6DOFIMU18_FIFO_FLUSH

#define C6DOFIMU18_FIFO_FLUSH 0x02

◆ C6DOFIMU18_FIFO_FULL_CLR_FIFO_READ

#define C6DOFIMU18_FIFO_FULL_CLR_FIFO_READ 0x02

◆ C6DOFIMU18_FIFO_FULL_CLR_ON_STATUS_READ

#define C6DOFIMU18_FIFO_FULL_CLR_ON_STATUS_READ 0x00

◆ C6DOFIMU18_FIFO_FULL_CLR_STATUS_AND_REG

#define C6DOFIMU18_FIFO_FULL_CLR_STATUS_AND_REG 0x03

◆ C6DOFIMU18_FIFO_FULL_INT_FLAG

#define C6DOFIMU18_FIFO_FULL_INT_FLAG 0x02

◆ C6DOFIMU18_FIFO_GYRO_EN

#define C6DOFIMU18_FIFO_GYRO_EN 0x02

◆ C6DOFIMU18_FIFO_HLD_LAST_DATA_EN

#define C6DOFIMU18_FIFO_HLD_LAST_DATA_EN 0x80

6DOF IMU 18 INTF CONFIG 0 register masks.

Specified setting for INTF CONFIG 0 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_FIFO_INT_CLR_FIFO_READ

#define C6DOFIMU18_FIFO_INT_CLR_FIFO_READ 0x80

◆ C6DOFIMU18_FIFO_INT_CLR_ON_STATUS_READ

#define C6DOFIMU18_FIFO_INT_CLR_ON_STATUS_READ 0x00

◆ C6DOFIMU18_FIFO_INT_CLR_STATUS_AND_REG

#define C6DOFIMU18_FIFO_INT_CLR_STATUS_AND_REG 0xc0

◆ C6DOFIMU18_FIFO_RESUME_PARTIAL_RD

#define C6DOFIMU18_FIFO_RESUME_PARTIAL_RD 0x40

6DOF IMU 18 FIFO CONFIG 1 register masks.

Specified setting for FIFO CONFIG 1 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_FIFO_STOP_ON_FULL

#define C6DOFIMU18_FIFO_STOP_ON_FULL 0x80

◆ C6DOFIMU18_FIFO_STREAM_TO_FIFO

#define C6DOFIMU18_FIFO_STREAM_TO_FIFO 0x40

◆ C6DOFIMU18_FIFO_TEMP_EN

#define C6DOFIMU18_FIFO_TEMP_EN 0x04

◆ C6DOFIMU18_FIFO_THS_INT_FLAG

#define C6DOFIMU18_FIFO_THS_INT_FLAG 0x04

◆ C6DOFIMU18_FIFO_TMST_FSYNC_EN

#define C6DOFIMU18_FIFO_TMST_FSYNC_EN 0x08

◆ C6DOFIMU18_FIFO_WM_GT_TH

#define C6DOFIMU18_FIFO_WM_GT_TH 0x20

◆ C6DOFIMU18_FSYNC_ACCEL_XOUT_LSB

#define C6DOFIMU18_FSYNC_ACCEL_XOUT_LSB 0x50

◆ C6DOFIMU18_FSYNC_ACCEL_YOUT_LSB

#define C6DOFIMU18_FSYNC_ACCEL_YOUT_LSB 0x60

◆ C6DOFIMU18_FSYNC_ACCEL_ZOUT_LSB

#define C6DOFIMU18_FSYNC_ACCEL_ZOUT_LSB 0x70

◆ C6DOFIMU18_FSYNC_GYRO_XOUT_LSB

#define C6DOFIMU18_FSYNC_GYRO_XOUT_LSB 0x20

◆ C6DOFIMU18_FSYNC_GYRO_YOUT_LSB

#define C6DOFIMU18_FSYNC_GYRO_YOUT_LSB 0x30

◆ C6DOFIMU18_FSYNC_GYRO_ZOUT_LSB

#define C6DOFIMU18_FSYNC_GYRO_ZOUT_LSB 0x40

◆ C6DOFIMU18_FSYNC_POLARITY_FALLING_EGDE

#define C6DOFIMU18_FSYNC_POLARITY_FALLING_EGDE 0x01

◆ C6DOFIMU18_FSYNC_POLARITY_RISING_EGDE

#define C6DOFIMU18_FSYNC_POLARITY_RISING_EGDE 0x01

◆ C6DOFIMU18_FSYNC_TAG_TEMP_OUT_LSB

#define C6DOFIMU18_FSYNC_TAG_TEMP_OUT_LSB 0x10

◆ C6DOFIMU18_FSYNC_UI_FLAG_CLEAR_SEL

#define C6DOFIMU18_FSYNC_UI_FLAG_CLEAR_SEL 0x02

◆ C6DOFIMU18_FSYNC_UI_SEL_MASK

#define C6DOFIMU18_FSYNC_UI_SEL_MASK 0x70

◆ C6DOFIMU18_GYRO_CONFIG1_MASK

#define C6DOFIMU18_GYRO_CONFIG1_MASK 0xEF

◆ C6DOFIMU18_GYRO_DEC2_M2_ORD_3rd

#define C6DOFIMU18_GYRO_DEC2_M2_ORD_3rd 0x02

◆ C6DOFIMU18_GYRO_FS_SEL_1000DPS

#define C6DOFIMU18_GYRO_FS_SEL_1000DPS 0x20

◆ C6DOFIMU18_GYRO_FS_SEL_125DPS

#define C6DOFIMU18_GYRO_FS_SEL_125DPS 0x80

◆ C6DOFIMU18_GYRO_FS_SEL_15DPS

#define C6DOFIMU18_GYRO_FS_SEL_15DPS 0xE0

◆ C6DOFIMU18_GYRO_FS_SEL_2000DPS

#define C6DOFIMU18_GYRO_FS_SEL_2000DPS 0x00

6DOF IMU 18 GYRO CONFIG 0 register masks.

Specified setting for GYRO CONFIG 0 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_GYRO_FS_SEL_250DPS

#define C6DOFIMU18_GYRO_FS_SEL_250DPS 0x60

◆ C6DOFIMU18_GYRO_FS_SEL_32DPS

#define C6DOFIMU18_GYRO_FS_SEL_32DPS 0xC0

◆ C6DOFIMU18_GYRO_FS_SEL_500DPS

#define C6DOFIMU18_GYRO_FS_SEL_500DPS 0x40

◆ C6DOFIMU18_GYRO_FS_SEL_62DPS

#define C6DOFIMU18_GYRO_FS_SEL_62DPS 0xA0

◆ C6DOFIMU18_GYRO_FS_SEL_MASK

#define C6DOFIMU18_GYRO_FS_SEL_MASK 0xE0

◆ C6DOFIMU18_GYRO_ODR_100Hz

#define C6DOFIMU18_GYRO_ODR_100Hz 0x08

◆ C6DOFIMU18_GYRO_ODR_12Hz

#define C6DOFIMU18_GYRO_ODR_12Hz 0x0B

◆ C6DOFIMU18_GYRO_ODR_1kHz

#define C6DOFIMU18_GYRO_ODR_1kHz 0x06

◆ C6DOFIMU18_GYRO_ODR_200Hz

#define C6DOFIMU18_GYRO_ODR_200Hz 0x07

◆ C6DOFIMU18_GYRO_ODR_25Hz

#define C6DOFIMU18_GYRO_ODR_25Hz 0x0A

◆ C6DOFIMU18_GYRO_ODR_2kHz

#define C6DOFIMU18_GYRO_ODR_2kHz 0x05

◆ C6DOFIMU18_GYRO_ODR_4kHz

#define C6DOFIMU18_GYRO_ODR_4kHz 0x04

◆ C6DOFIMU18_GYRO_ODR_500Hz

#define C6DOFIMU18_GYRO_ODR_500Hz 0x0F

◆ C6DOFIMU18_GYRO_ODR_50Hz

#define C6DOFIMU18_GYRO_ODR_50Hz 0x09

◆ C6DOFIMU18_GYRO_ODR_8kHz

#define C6DOFIMU18_GYRO_ODR_8kHz 0x03

◆ C6DOFIMU18_GYRO_ODR_MASK [1/2]

#define C6DOFIMU18_GYRO_ODR_MASK 0x0F

◆ C6DOFIMU18_GYRO_ODR_MASK [2/2]

#define C6DOFIMU18_GYRO_ODR_MASK 0x0F

◆ C6DOFIMU18_GYRO_UI_FILT_ORD_1st

#define C6DOFIMU18_GYRO_UI_FILT_ORD_1st 0x00

◆ C6DOFIMU18_GYRO_UI_FILT_ORD_2nd

#define C6DOFIMU18_GYRO_UI_FILT_ORD_2nd 0x04

◆ C6DOFIMU18_GYRO_UI_FILT_ORD_3rd

#define C6DOFIMU18_GYRO_UI_FILT_ORD_3rd 0x08

◆ C6DOFIMU18_GYRO_UI_FILT_ORD_MASK

#define C6DOFIMU18_GYRO_UI_FILT_ORD_MASK 0x0C

◆ C6DOFIMU18_INT_ASYNC_RESET_DISABLE

#define C6DOFIMU18_INT_ASYNC_RESET_DISABLE 0x10

◆ C6DOFIMU18_INT_ASYNC_RESET_ENABLE

#define C6DOFIMU18_INT_ASYNC_RESET_ENABLE 0x00

◆ C6DOFIMU18_INT_CONFIG1_MASK

#define C6DOFIMU18_INT_CONFIG1_MASK 0x70

◆ C6DOFIMU18_INT_CONFIG_MASK

#define C6DOFIMU18_INT_CONFIG_MASK 0x3F

◆ C6DOFIMU18_INT_FIFO_FULL_INT1_EN

#define C6DOFIMU18_INT_FIFO_FULL_INT1_EN 0x02

◆ C6DOFIMU18_INT_FIFO_FULL_INT2_EN

#define C6DOFIMU18_INT_FIFO_FULL_INT2_EN 0x02

◆ C6DOFIMU18_INT_FIFO_THS_INT1_EN

#define C6DOFIMU18_INT_FIFO_THS_INT1_EN 0x04

◆ C6DOFIMU18_INT_FIFO_THS_INT2_EN

#define C6DOFIMU18_INT_FIFO_THS_INT2_EN 0x04

◆ C6DOFIMU18_INT_INT1_ACTIVE_HIGH

#define C6DOFIMU18_INT_INT1_ACTIVE_HIGH 0x01

◆ C6DOFIMU18_INT_INT1_ACTIVE_LOW

#define C6DOFIMU18_INT_INT1_ACTIVE_LOW 0x00

◆ C6DOFIMU18_INT_INT1_MODE_LATCHED

#define C6DOFIMU18_INT_INT1_MODE_LATCHED 0x04

◆ C6DOFIMU18_INT_INT1_MODE_PULSED

#define C6DOFIMU18_INT_INT1_MODE_PULSED 0x00

◆ C6DOFIMU18_INT_INT1_OPEN_DRAIN

#define C6DOFIMU18_INT_INT1_OPEN_DRAIN 0x00

◆ C6DOFIMU18_INT_INT1_PUSH_PULL

#define C6DOFIMU18_INT_INT1_PUSH_PULL 0x02

◆ C6DOFIMU18_INT_INT2_ACTIVE_HIGH

#define C6DOFIMU18_INT_INT2_ACTIVE_HIGH 0x08

◆ C6DOFIMU18_INT_INT2_ACTIVE_LOW

#define C6DOFIMU18_INT_INT2_ACTIVE_LOW 0x00

◆ C6DOFIMU18_INT_INT2_MODE_LATCHED

#define C6DOFIMU18_INT_INT2_MODE_LATCHED 0x20

◆ C6DOFIMU18_INT_INT2_MODE_PULSED

#define C6DOFIMU18_INT_INT2_MODE_PULSED 0x00

6DOF IMU 18 INT CONFIG register masks.

Specified setting for INT CONFIG register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_INT_INT2_OPEN_DRAIN

#define C6DOFIMU18_INT_INT2_OPEN_DRAIN 0x00

◆ C6DOFIMU18_INT_INT2_PUSH_PULL

#define C6DOFIMU18_INT_INT2_PUSH_PULL 0x10

◆ C6DOFIMU18_INT_PLL_RDY_INT1_EN

#define C6DOFIMU18_INT_PLL_RDY_INT1_EN 0x20

◆ C6DOFIMU18_INT_PLL_RDY_INT2_EN

#define C6DOFIMU18_INT_PLL_RDY_INT2_EN 0x20

◆ C6DOFIMU18_INT_RESET_DONE_INT1_EN

#define C6DOFIMU18_INT_RESET_DONE_INT1_EN 0x10

◆ C6DOFIMU18_INT_RESET_DONE_INT2_EN

#define C6DOFIMU18_INT_RESET_DONE_INT2_EN 0x10

◆ C6DOFIMU18_INT_SOURCE0_MASK

#define C6DOFIMU18_INT_SOURCE0_MASK 0x7F

◆ C6DOFIMU18_INT_SOURCE1_MASK

#define C6DOFIMU18_INT_SOURCE1_MASK 0x0F

◆ C6DOFIMU18_INT_SOURCE3_MASK

#define C6DOFIMU18_INT_SOURCE3_MASK 0x7F

◆ C6DOFIMU18_INT_SOURCE4_MASK

#define C6DOFIMU18_INT_SOURCE4_MASK 0x0F

◆ C6DOFIMU18_INT_SOURCE6_MASK

#define C6DOFIMU18_INT_SOURCE6_MASK 0x39

◆ C6DOFIMU18_INT_SOURCE6_STEP_CNT_INT1_EN

#define C6DOFIMU18_INT_SOURCE6_STEP_CNT_INT1_EN 0x10

◆ C6DOFIMU18_INT_SOURCE6_STEP_DET_INT1_EN

#define C6DOFIMU18_INT_SOURCE6_STEP_DET_INT1_EN 0x20

6DOF IMU 18 INT SOURCE 6 register masks.

Specified setting for INT SOURCE 6 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_INT_SOURCE6_TAP_DET_INT1_EN

#define C6DOFIMU18_INT_SOURCE6_TAP_DET_INT1_EN 0x01

◆ C6DOFIMU18_INT_SOURCE6_TILT_DET_INT1_EN

#define C6DOFIMU18_INT_SOURCE6_TILT_DET_INT1_EN 0x08

◆ C6DOFIMU18_INT_SOURCE7_MASK

#define C6DOFIMU18_INT_SOURCE7_MASK 0x39

◆ C6DOFIMU18_INT_SOURCE7_STEP_CNT_INT2_EN

#define C6DOFIMU18_INT_SOURCE7_STEP_CNT_INT2_EN 0x10

◆ C6DOFIMU18_INT_SOURCE7_STEP_DET_INT2_EN

#define C6DOFIMU18_INT_SOURCE7_STEP_DET_INT2_EN 0x20

6DOF IMU 18 INT SOURCE 7 register masks.

Specified setting for INT SOURCE 7 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_INT_SOURCE7_TAP_DET_INT2_EN

#define C6DOFIMU18_INT_SOURCE7_TAP_DET_INT2_EN 0x01

◆ C6DOFIMU18_INT_SOURCE7_TILT_DET_INT2_EN

#define C6DOFIMU18_INT_SOURCE7_TILT_DET_INT2_EN 0x08

◆ C6DOFIMU18_INT_TDEASSERT_DISABLE

#define C6DOFIMU18_INT_TDEASSERT_DISABLE 0x20

◆ C6DOFIMU18_INT_TPULSE_100uS

#define C6DOFIMU18_INT_TPULSE_100uS 0x00

6DOF IMU 18 INT CONFIG 1 register masks.

Specified setting for INT CONFIG 1 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_INT_TPULSE_8uS

#define C6DOFIMU18_INT_TPULSE_8uS 0x40

◆ C6DOFIMU18_INT_UI_AGC_RDY_INT1_EN

#define C6DOFIMU18_INT_UI_AGC_RDY_INT1_EN 0x01

◆ C6DOFIMU18_INT_UI_AGC_RDY_INT2_EN

#define C6DOFIMU18_INT_UI_AGC_RDY_INT2_EN 0x01

◆ C6DOFIMU18_INT_UI_DRDY_INT1_EN

#define C6DOFIMU18_INT_UI_DRDY_INT1_EN 0x08

◆ C6DOFIMU18_INT_UI_DRDY_INT2_EN

#define C6DOFIMU18_INT_UI_DRDY_INT2_EN 0x08

◆ C6DOFIMU18_INT_UI_FSYNC_INT1_EN

#define C6DOFIMU18_INT_UI_FSYNC_INT1_EN 0x40

6DOF IMU 18 INT SOURCE 0 register masks.

Specified setting for INT SOURCE 0 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_INT_UI_FSYNC_INT2_EN

#define C6DOFIMU18_INT_UI_FSYNC_INT2_EN 0x40

6DOF IMU 18 INT SOURCE 3 register masks.

Specified setting for INT SOURCE 3 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_INTF_CONFIG0_MASK

#define C6DOFIMU18_INTF_CONFIG0_MASK 0xF3

◆ C6DOFIMU18_LOW_ENERGY_AMP_TH_SEL

#define C6DOFIMU18_LOW_ENERGY_AMP_TH_SEL 0xA0

6DOF IMU 18 APEX CONFIG 1 register masks.

Specified setting for APEX CONFIG 1 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_PED_AMP_TH_SEL

#define C6DOFIMU18_PED_AMP_TH_SEL 0x80

6DOF IMU 18 APEX CONFIG 2 register masks.

Specified setting for APEX CONFIG 2 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_PED_ENABLE

#define C6DOFIMU18_PED_ENABLE 0x20

◆ C6DOFIMU18_PED_HI_EN_TH_SEL

#define C6DOFIMU18_PED_HI_EN_TH_SEL 0x01

◆ C6DOFIMU18_PED_SB_TIMER_TH_0_SAMPLES

#define C6DOFIMU18_PED_SB_TIMER_TH_0_SAMPLES 0x00

◆ C6DOFIMU18_PED_SB_TIMER_TH_1_SAMPLES

#define C6DOFIMU18_PED_SB_TIMER_TH_1_SAMPLES 0x04

◆ C6DOFIMU18_PED_SB_TIMER_TH_2_SAMPLES

#define C6DOFIMU18_PED_SB_TIMER_TH_2_SAMPLES 0x08

◆ C6DOFIMU18_PED_SB_TIMER_TH_3_SAMPLES

#define C6DOFIMU18_PED_SB_TIMER_TH_3_SAMPLES 0x0C

◆ C6DOFIMU18_PED_SB_TIMER_TH_4_SAMPLES

#define C6DOFIMU18_PED_SB_TIMER_TH_4_SAMPLES 0x10

◆ C6DOFIMU18_PED_SB_TIMER_TH_5_SAMPLES

#define C6DOFIMU18_PED_SB_TIMER_TH_5_SAMPLES 0x14

◆ C6DOFIMU18_PED_SB_TIMER_TH_6_SAMPLES

#define C6DOFIMU18_PED_SB_TIMER_TH_6_SAMPLES 0x18

◆ C6DOFIMU18_PED_SB_TIMER_TH_7_SAMPLES

#define C6DOFIMU18_PED_SB_TIMER_TH_7_SAMPLES 0x1C

◆ C6DOFIMU18_PED_STEP_CNT_TH_0_STEPS

#define C6DOFIMU18_PED_STEP_CNT_TH_0_STEPS 0x00

◆ C6DOFIMU18_PED_STEP_CNT_TH_10_STEPS

#define C6DOFIMU18_PED_STEP_CNT_TH_10_STEPS 0x0A

◆ C6DOFIMU18_PED_STEP_CNT_TH_11_STEPS

#define C6DOFIMU18_PED_STEP_CNT_TH_11_STEPS 0x0B

◆ C6DOFIMU18_PED_STEP_CNT_TH_12_STEPS

#define C6DOFIMU18_PED_STEP_CNT_TH_12_STEPS 0x0C

◆ C6DOFIMU18_PED_STEP_CNT_TH_13_STEPS

#define C6DOFIMU18_PED_STEP_CNT_TH_13_STEPS 0x0D

◆ C6DOFIMU18_PED_STEP_CNT_TH_14_STEPS

#define C6DOFIMU18_PED_STEP_CNT_TH_14_STEPS 0x0E

◆ C6DOFIMU18_PED_STEP_CNT_TH_15_STEPS

#define C6DOFIMU18_PED_STEP_CNT_TH_15_STEPS 0x0F

◆ C6DOFIMU18_PED_STEP_CNT_TH_1_STEPS

#define C6DOFIMU18_PED_STEP_CNT_TH_1_STEPS 0x01

◆ C6DOFIMU18_PED_STEP_CNT_TH_2_STEPS

#define C6DOFIMU18_PED_STEP_CNT_TH_2_STEPS 0x02

◆ C6DOFIMU18_PED_STEP_CNT_TH_3_STEPS

#define C6DOFIMU18_PED_STEP_CNT_TH_3_STEPS 0x03

◆ C6DOFIMU18_PED_STEP_CNT_TH_4_STEPS

#define C6DOFIMU18_PED_STEP_CNT_TH_4_STEPS 0x04

◆ C6DOFIMU18_PED_STEP_CNT_TH_5_STEPS

#define C6DOFIMU18_PED_STEP_CNT_TH_5_STEPS 0x05

◆ C6DOFIMU18_PED_STEP_CNT_TH_6_STEPS

#define C6DOFIMU18_PED_STEP_CNT_TH_6_STEPS 0x06

◆ C6DOFIMU18_PED_STEP_CNT_TH_7_STEPS

#define C6DOFIMU18_PED_STEP_CNT_TH_7_STEPS 0x07

◆ C6DOFIMU18_PED_STEP_CNT_TH_8_STEPS

#define C6DOFIMU18_PED_STEP_CNT_TH_8_STEPS 0x08

◆ C6DOFIMU18_PED_STEP_CNT_TH_9_STEPS

#define C6DOFIMU18_PED_STEP_CNT_TH_9_STEPS 0x09

◆ C6DOFIMU18_PED_STEP_CNT_TH_MASK

#define C6DOFIMU18_PED_STEP_CNT_TH_MASK 0x0F

◆ C6DOFIMU18_PED_STEP_DET_TH_0_STEPS

#define C6DOFIMU18_PED_STEP_DET_TH_0_STEPS 0x00

6DOF IMU 18 APEX CONFIG 3 register masks.

Specified setting for APEX CONFIG 3 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_PED_STEP_DET_TH_1_STEPS

#define C6DOFIMU18_PED_STEP_DET_TH_1_STEPS 0x20

◆ C6DOFIMU18_PED_STEP_DET_TH_2_STEPS

#define C6DOFIMU18_PED_STEP_DET_TH_2_STEPS 0x40

◆ C6DOFIMU18_PED_STEP_DET_TH_3_STEPS

#define C6DOFIMU18_PED_STEP_DET_TH_3_STEPS 0x60

◆ C6DOFIMU18_PED_STEP_DET_TH_4_STEPS

#define C6DOFIMU18_PED_STEP_DET_TH_4_STEPS 0x80

◆ C6DOFIMU18_PED_STEP_DET_TH_5_STEPS

#define C6DOFIMU18_PED_STEP_DET_TH_5_STEPS 0xA0

◆ C6DOFIMU18_PED_STEP_DET_TH_6_STEPS

#define C6DOFIMU18_PED_STEP_DET_TH_6_STEPS 0xC0

◆ C6DOFIMU18_PED_STEP_DET_TH_7_STEPS

#define C6DOFIMU18_PED_STEP_DET_TH_7_STEPS 0xE0

◆ C6DOFIMU18_PIN9_FSYNC

#define C6DOFIMU18_PIN9_FSYNC 0x01

◆ C6DOFIMU18_PIN9_INT2

#define C6DOFIMU18_PIN9_INT2 0x00

6DOF IMU 18 INTF CONFIG 5 register masks.

Specified setting for INTF CONFIG 5 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_PLL_DONE_INT_FLAG

#define C6DOFIMU18_PLL_DONE_INT_FLAG 0x20

◆ C6DOFIMU18_PWR_ACCEL_LN_MODE

#define C6DOFIMU18_PWR_ACCEL_LN_MODE 0x03

◆ C6DOFIMU18_PWR_ACCEL_LP_MODE

#define C6DOFIMU18_PWR_ACCEL_LP_MODE 0x02

◆ C6DOFIMU18_PWR_ACCEL_MODE_OFF

#define C6DOFIMU18_PWR_ACCEL_MODE_OFF 0x00

◆ C6DOFIMU18_PWR_GYRO_LN_MODE

#define C6DOFIMU18_PWR_GYRO_LN_MODE 0x0C

◆ C6DOFIMU18_PWR_GYRO_MODE_OFF

#define C6DOFIMU18_PWR_GYRO_MODE_OFF 0x00

◆ C6DOFIMU18_PWR_GYRO_STANDBY

#define C6DOFIMU18_PWR_GYRO_STANDBY 0x04

◆ C6DOFIMU18_PWR_IDLE_OFF

#define C6DOFIMU18_PWR_IDLE_OFF 0x10

◆ C6DOFIMU18_PWR_TEMP_DIS

#define C6DOFIMU18_PWR_TEMP_DIS 0x20

6DOF IMU 18 PWR MGMT0 register masks.

Specified setting for PWR MGMT0 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_R2W_ENABLE

#define C6DOFIMU18_R2W_ENABLE 0x08

◆ C6DOFIMU18_RESET_DONE_INT_FLAG

#define C6DOFIMU18_RESET_DONE_INT_FLAG 0x10

◆ C6DOFIMU18_SENSITIVITY_MODE_HIGH_PERF

#define C6DOFIMU18_SENSITIVITY_MODE_HIGH_PERF 0x00

6DOF IMU 18 APEX CONFIG 9 register masks.

Specified setting for APEX CONFIG 9 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_SENSITIVITY_MODE_SLOW_WALK

#define C6DOFIMU18_SENSITIVITY_MODE_SLOW_WALK 0x01

◆ C6DOFIMU18_SET_DATA_SAMPLE_EDGE

#define C6DOFIMU18_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE

Data sample selection.

This macro sets data samples for SPI modules.

Note: Available only on Microchip PIC family devices. This macro will set data sampling for all SPI modules on MCU. Can be overwritten with c6dofimu18_init which will set SET_SPI_DATA_SAMPLE_MIDDLE by default on the mapped mikrobus.

◆ C6DOFIMU18_SET_DATA_SAMPLE_MIDDLE

#define C6DOFIMU18_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE

◆ C6DOFIMU18_SLEEP_INT_FLAG

#define C6DOFIMU18_SLEEP_INT_FLAG 0x02

◆ C6DOFIMU18_SLEEP_TIME_OUT_10s24

#define C6DOFIMU18_SLEEP_TIME_OUT_10s24 0x38

◆ C6DOFIMU18_SLEEP_TIME_OUT_1s28

#define C6DOFIMU18_SLEEP_TIME_OUT_1s28 0x00

◆ C6DOFIMU18_SLEEP_TIME_OUT_2s56

#define C6DOFIMU18_SLEEP_TIME_OUT_2s56 0x08

◆ C6DOFIMU18_SLEEP_TIME_OUT_3s84

#define C6DOFIMU18_SLEEP_TIME_OUT_3s84 0x10

◆ C6DOFIMU18_SLEEP_TIME_OUT_5s12

#define C6DOFIMU18_SLEEP_TIME_OUT_5s12 0x18

◆ C6DOFIMU18_SLEEP_TIME_OUT_6s4

#define C6DOFIMU18_SLEEP_TIME_OUT_6s4 0x20

◆ C6DOFIMU18_SLEEP_TIME_OUT_7s68

#define C6DOFIMU18_SLEEP_TIME_OUT_7s68 0x28

◆ C6DOFIMU18_SLEEP_TIME_OUT_8s96

#define C6DOFIMU18_SLEEP_TIME_OUT_8s96 0x30

◆ C6DOFIMU18_SLEEP_TIME_OUT_MASK

#define C6DOFIMU18_SLEEP_TIME_OUT_MASK 0x38

◆ C6DOFIMU18_SLEW_RATE_12nS

#define C6DOFIMU18_SLEW_RATE_12nS 0x03

◆ C6DOFIMU18_SLEW_RATE_18nS

#define C6DOFIMU18_SLEW_RATE_18nS 0x02

◆ C6DOFIMU18_SLEW_RATE_2nS

#define C6DOFIMU18_SLEW_RATE_2nS 0x05

◆ C6DOFIMU18_SLEW_RATE_36nS

#define C6DOFIMU18_SLEW_RATE_36nS 0x01

◆ C6DOFIMU18_SLEW_RATE_60nS

#define C6DOFIMU18_SLEW_RATE_60nS 0x00

6DOF IMU 18 communication slew rate.

Specified setting for communication slew rate of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_SLEW_RATE_6nS

#define C6DOFIMU18_SLEW_RATE_6nS 0x04

◆ C6DOFIMU18_SMD_INT1_EN

#define C6DOFIMU18_SMD_INT1_EN 0x08

6DOF IMU 18 INT SOURCE 1 register masks.

Specified setting for INT SOURCE 1 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_SMD_INT2_EN

#define C6DOFIMU18_SMD_INT2_EN 0x08

6DOF IMU 18 INT SOURCE 4 register masks.

Specified setting for INT SOURCE 4 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_SMD_INT_FLAG

#define C6DOFIMU18_SMD_INT_FLAG 0x08

6DOF IMU 18 INT STATUS 2 register masks.

Specified setting for INT STATUS 2 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_SPI_3WIRE

#define C6DOFIMU18_SPI_3WIRE 0x00

6DOF IMU 18 INTF CONFIG 4 register masks.

Specified setting for INTF CONFIG 4 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_SPI_4WIRE

#define C6DOFIMU18_SPI_4WIRE 0x02

◆ C6DOFIMU18_SPI_MODE0_MODE3

#define C6DOFIMU18_SPI_MODE0_MODE3 0x00

6DOF IMU 18 SPI mode.

Specified setting for SPI mode of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_SPI_MODE1_MODE2

#define C6DOFIMU18_SPI_MODE1_MODE2 0x01

◆ C6DOFIMU18_STEP_CNT_OVF_INT_FLAG

#define C6DOFIMU18_STEP_CNT_OVF_INT_FLAG 0x08

◆ C6DOFIMU18_STEP_DET_INT_FLAG

#define C6DOFIMU18_STEP_DET_INT_FLAG 0x10

6DOF IMU 18 INT STATUS 3 register masks.

Specified setting for INT STATUS 3 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_TAP_AXIS_MASK

#define C6DOFIMU18_TAP_AXIS_MASK 0x06

◆ C6DOFIMU18_TAP_AXIS_X

#define C6DOFIMU18_TAP_AXIS_X 0x00

◆ C6DOFIMU18_TAP_AXIS_Y

#define C6DOFIMU18_TAP_AXIS_Y 0x02

◆ C6DOFIMU18_TAP_AXIS_Z

#define C6DOFIMU18_TAP_AXIS_Z 0x04

◆ C6DOFIMU18_TAP_DET_INT_FLAG

#define C6DOFIMU18_TAP_DET_INT_FLAG 0x01

◆ C6DOFIMU18_TAP_DIR_MASK

#define C6DOFIMU18_TAP_DIR_MASK 0x01

◆ C6DOFIMU18_TAP_DIR_NEGATIVE

#define C6DOFIMU18_TAP_DIR_NEGATIVE 0x01

◆ C6DOFIMU18_TAP_DIR_POSITIVE

#define C6DOFIMU18_TAP_DIR_POSITIVE 0x00

◆ C6DOFIMU18_TAP_DOUBLE

#define C6DOFIMU18_TAP_DOUBLE 0x10

◆ C6DOFIMU18_TAP_ENABLE

#define C6DOFIMU18_TAP_ENABLE 0x40

◆ C6DOFIMU18_TAP_MAX_OEAK_TOL

#define C6DOFIMU18_TAP_MAX_OEAK_TOL 0x01

◆ C6DOFIMU18_TAP_MIN_JERK_THR

#define C6DOFIMU18_TAP_MIN_JERK_THR 0x44

6DOF IMU 18 APEX CONFIG 7 register masks.

Specified setting for APEX CONFIG 7 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_TAP_NUM_MASK

#define C6DOFIMU18_TAP_NUM_MASK 0x18

◆ C6DOFIMU18_TAP_SINGLE

#define C6DOFIMU18_TAP_SINGLE 0x08

◆ C6DOFIMU18_TAP_TAVG

#define C6DOFIMU18_TAP_TAVG 0x08

◆ C6DOFIMU18_TAP_TMAX

#define C6DOFIMU18_TAP_TMAX 0x20

6DOF IMU 18 APEX CONFIG 8 register masks.

Specified setting for APEX CONFIG 8 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_TAP_TMIN

#define C6DOFIMU18_TAP_TMIN 0x03

◆ C6DOFIMU18_TEMP_FILT_BW_10Hz

#define C6DOFIMU18_TEMP_FILT_BW_10Hz 0xA0

◆ C6DOFIMU18_TEMP_FILT_BW_170Hz

#define C6DOFIMU18_TEMP_FILT_BW_170Hz 0x20

◆ C6DOFIMU18_TEMP_FILT_BW_20Hz

#define C6DOFIMU18_TEMP_FILT_BW_20Hz 0x80

◆ C6DOFIMU18_TEMP_FILT_BW_40Hz

#define C6DOFIMU18_TEMP_FILT_BW_40Hz 0x60

◆ C6DOFIMU18_TEMP_FILT_BW_4kHz

#define C6DOFIMU18_TEMP_FILT_BW_4kHz 0x00

6DOF IMU 18 GYRO CONFIG 1 register masks.

Specified setting for GYRO CONFIG 1 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_TEMP_FILT_BW_5Hz_0

#define C6DOFIMU18_TEMP_FILT_BW_5Hz_0 0xC0

◆ C6DOFIMU18_TEMP_FILT_BW_5Hz_1

#define C6DOFIMU18_TEMP_FILT_BW_5Hz_1 0xE0

◆ C6DOFIMU18_TEMP_FILT_BW_82Hz

#define C6DOFIMU18_TEMP_FILT_BW_82Hz 0x40

◆ C6DOFIMU18_TEMPERATURE_ADD

#define C6DOFIMU18_TEMPERATURE_ADD 25

◆ C6DOFIMU18_TEMPERATURE_DIV

#define C6DOFIMU18_TEMPERATURE_DIV 132.48

6DOF IMU 18 Temperature calculation values.

Specified setting for temperature calculation of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_TILT_DET_INT_FLAG

#define C6DOFIMU18_TILT_DET_INT_FLAG 0x04

◆ C6DOFIMU18_TILT_ENABLE

#define C6DOFIMU18_TILT_ENABLE 0x10

◆ C6DOFIMU18_TILT_WAIT_TIME_0S

#define C6DOFIMU18_TILT_WAIT_TIME_0S 0x00

6DOF IMU 18 APEX CONFIG 4 register masks.

Specified setting for APEX CONFIG 4 register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_TILT_WAIT_TIME_2S

#define C6DOFIMU18_TILT_WAIT_TIME_2S 0x40

◆ C6DOFIMU18_TILT_WAIT_TIME_4S

#define C6DOFIMU18_TILT_WAIT_TIME_4S 0x80

◆ C6DOFIMU18_TILT_WAIT_TIME_6S

#define C6DOFIMU18_TILT_WAIT_TIME_6S 0xC0

◆ C6DOFIMU18_TILT_WAIT_TIME_MASK

#define C6DOFIMU18_TILT_WAIT_TIME_MASK 0xC0

◆ C6DOFIMU18_TMST_DELTA_EN

#define C6DOFIMU18_TMST_DELTA_EN 0x04

◆ C6DOFIMU18_TMST_EN

#define C6DOFIMU18_TMST_EN 0x01

◆ C6DOFIMU18_TMST_FSYNC_EN

#define C6DOFIMU18_TMST_FSYNC_EN 0x02

◆ C6DOFIMU18_TMST_MASK

#define C6DOFIMU18_TMST_MASK 0x1F

◆ C6DOFIMU18_TMST_RES

#define C6DOFIMU18_TMST_RES 0x08

◆ C6DOFIMU18_TMST_STROBE

#define C6DOFIMU18_TMST_STROBE 0x04

◆ C6DOFIMU18_TMST_TO_REGS_EN

#define C6DOFIMU18_TMST_TO_REGS_EN 0x10

6DOF IMU 18 TMST CONFIG register masks.

Specified setting for TMST CONFIG register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_UI_FSYNC_INT_FLAG

#define C6DOFIMU18_UI_FSYNC_INT_FLAG 0x40

6DOF IMU 18 INT STATUS register masks.

Specified setting for INT STATUS register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_UI_SIFS_CFG_DISABLE_I2C

#define C6DOFIMU18_UI_SIFS_CFG_DISABLE_I2C 0x03

◆ C6DOFIMU18_UI_SIFS_CFG_DISABLE_SPI

#define C6DOFIMU18_UI_SIFS_CFG_DISABLE_SPI 0x02

◆ C6DOFIMU18_WHO_AM_I_VALUE

#define C6DOFIMU18_WHO_AM_I_VALUE 0x42

6DOF IMU 18 who am i register values.

Specified value for who am i register of 6DOF IMU 18 Click driver.

◆ C6DOFIMU18_WOM_X_INT1_EN

#define C6DOFIMU18_WOM_X_INT1_EN 0x01

◆ C6DOFIMU18_WOM_X_INT2_EN

#define C6DOFIMU18_WOM_X_INT2_EN 0x01

◆ C6DOFIMU18_WOM_X_INT_FLAG

#define C6DOFIMU18_WOM_X_INT_FLAG 0x01

◆ C6DOFIMU18_WOM_Y_INT1_EN

#define C6DOFIMU18_WOM_Y_INT1_EN 0x02

◆ C6DOFIMU18_WOM_Y_INT2_EN

#define C6DOFIMU18_WOM_Y_INT2_EN 0x02

◆ C6DOFIMU18_WOM_Y_INT_FLAG

#define C6DOFIMU18_WOM_Y_INT_FLAG 0x02

◆ C6DOFIMU18_WOM_Z_INT1_EN

#define C6DOFIMU18_WOM_Z_INT1_EN 0x04

◆ C6DOFIMU18_WOM_Z_INT2_EN

#define C6DOFIMU18_WOM_Z_INT2_EN 0x04

◆ C6DOFIMU18_WOM_Z_INT_FLAG

#define C6DOFIMU18_WOM_Z_INT_FLAG 0x04

Macros