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c6dofimu4 2.0.0.0
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| #define C6DOFIMU4_A_DLPF_CFG_10_HZ 0x05 |
| #define C6DOFIMU4_A_DLPF_CFG_218_HZ 0x01 |
| #define C6DOFIMU4_A_DLPF_CFG_21_HZ 0x04 |
| #define C6DOFIMU4_A_DLPF_CFG_420_HZ 0x07 |
| #define C6DOFIMU4_A_DLPF_CFG_44_HZ 0x03 |
| #define C6DOFIMU4_A_DLPF_CFG_5_HZ 0x06 |
| #define C6DOFIMU4_A_DLPF_CFG_99_HZ 0x02 |
| #define C6DOFIMU4_ACCEL_AVRG_CFG_16_SAMPLES 0x20 |
| #define C6DOFIMU4_ACCEL_AVRG_CFG_32_SAMPLES 0x30 |
| #define C6DOFIMU4_ACCEL_AVRG_CFG_4_SAMPLES 0x00 |
| #define C6DOFIMU4_ACCEL_AVRG_CFG_8_SAMPLES 0x10 |
| #define C6DOFIMU4_ACCEL_FCHOICE_1046_HZ 0x08 |
| #define C6DOFIMU4_ACCEL_FIFO_EN 0x08 |
| #define C6DOFIMU4_ACCEL_FS_SEL_16_G 0x03 |
| #define C6DOFIMU4_ACCEL_FS_SEL_2_G 0x00 |
| #define C6DOFIMU4_ACCEL_FS_SEL_4_G 0x01 |
| #define C6DOFIMU4_ACCEL_FS_SEL_8_G 0x02 |
| #define C6DOFIMU4_ACCEL_INTEL_MODE_COMPARE 0x40 |
| #define C6DOFIMU4_ACCEL_INTEL_MODE_NOT_USE 0x00 |
| #define C6DOFIMU4_ACCEL_INTEL_WOM_DET_LOGIC_EN 0x80 |
| #define C6DOFIMU4_ACCEL_RST 0x02 |
| #define C6DOFIMU4_ALL_AXIS_EN 0x00 |
| #define C6DOFIMU4_ALL_DIG_SIG_PATH_RST 0x01 |
| #define C6DOFIMU4_CLKSEL_AUTO_SELECT 0x05 |
| #define C6DOFIMU4_CLKSEL_INTERNAL_20_MHZ 0x06 |
| #define C6DOFIMU4_CLKSEL_STOP_CLOCK 0x07 |
| #define C6DOFIMU4_CYCLE 0x20 |
| #define C6DOFIMU4_DATA_RDY_INT_MASK 0x01 |
| #define C6DOFIMU4_DATA_RDY_INT_OCCURED 0x01 |
| #define C6DOFIMU4_DEVICE_RST 0x80 |
| #define C6DOFIMU4_EXT_SYNC_ACCEL_XOUT_L 0x28 |
| #define C6DOFIMU4_EXT_SYNC_ACCEL_YOUT_L 0x30 |
| #define C6DOFIMU4_EXT_SYNC_ACCEL_ZOUT_L 0x38 |
| #define C6DOFIMU4_EXT_SYNC_FUNC_DIS 0x00 |
| #define C6DOFIMU4_EXT_SYNC_GYRO_XOUT_L 0x10 |
| #define C6DOFIMU4_EXT_SYNC_GYRO_YOUT_L 0x18 |
| #define C6DOFIMU4_EXT_SYNC_GYRO_ZOUT_L 0x20 |
| #define C6DOFIMU4_EXT_SYNC_TEMP_OUT_L 0x08 |
| #define C6DOFIMU4_FCHOICE_8173_HZ 0x01 |
| #define C6DOFIMU4_FIFO_EN 0x40 |
| #define C6DOFIMU4_FIFO_OFLOW_INT_MASK 0x10 |
| #define C6DOFIMU4_FIFO_OFLOW_INT_OCCURED 0x10 |
| #define C6DOFIMU4_FIFO_REPLACING_DIS 0x40 |
| #define C6DOFIMU4_FIFO_RST 0x04 |
| #define C6DOFIMU4_FIFO_WM_INT_MASK 0x40 |
| #define C6DOFIMU4_FIFO_WM_INT_NOT_OCCURED 0x00 |
| #define C6DOFIMU4_FIFO_WM_INT_OCCURED 0x40 |
| #define C6DOFIMU4_FSYNC_INT_MASK 0x80 |
| #define C6DOFIMU4_FSYNC_INT_MODE_EN 0x04 |
| #define C6DOFIMU4_FSYNC_INT_NOT_OCCURED 0x00 |
| #define C6DOFIMU4_FSYNC_INT_OCCURED 0x80 |
| #define C6DOFIMU4_FSYNC_PIN_INT_ACT_HIGH 0x00 |
| #define C6DOFIMU4_FSYNC_PIN_INT_ACT_LOW 0x08 |
| #define C6DOFIMU4_G_AVGCFG_128X_7HZ 0x70 |
| #define C6DOFIMU4_G_AVGCFG_16X_54HZ 0x40 |
| #define C6DOFIMU4_G_AVGCFG_1X_622HZ 0x00 |
| #define C6DOFIMU4_G_AVGCFG_2X_391HZ 0x10 |
| #define C6DOFIMU4_G_AVGCFG_32X_27HZ 0x50 |
| #define C6DOFIMU4_G_AVGCFG_4X_211HZ 0x20 |
| #define C6DOFIMU4_G_AVGCFG_64X_14HZ 0x60 |
| #define C6DOFIMU4_G_AVGCFG_8X_108HZ 0x30 |
| #define C6DOFIMU4_G_DLPF_CFG_10_HZ 0x05 |
| #define C6DOFIMU4_G_DLPF_CFG_176_HZ 0x01 |
| #define C6DOFIMU4_G_DLPF_CFG_20_HZ 0x04 |
| #define C6DOFIMU4_G_DLPF_CFG_250_HZ 0x00 |
| #define C6DOFIMU4_G_DLPF_CFG_3281_HZ 0x07 |
| #define C6DOFIMU4_G_DLPF_CFG_41_HZ 0x03 |
| #define C6DOFIMU4_G_DLPF_CFG_5_HZ 0x06 |
| #define C6DOFIMU4_G_DLPF_CFG_92_HZ 0x02 |
| #define C6DOFIMU4_GDRIVE_INT_MASK 0x04 |
| #define C6DOFIMU4_GDRIVE_INT_OCCURED 0x04 |
| #define C6DOFIMU4_GYRO_FCHOICE_3281_HZ 0x02 |
| #define C6DOFIMU4_GYRO_FIFO_EN 0x10 |
| #define C6DOFIMU4_GYRO_FS_SEL_1000_DPS 0x02 |
| #define C6DOFIMU4_GYRO_FS_SEL_2000_DPS 0x03 |
| #define C6DOFIMU4_GYRO_FS_SEL_250_DPS 0x00 |
| #define C6DOFIMU4_GYRO_FS_SEL_500_DPS 0x01 |
| #define C6DOFIMU4_GYRO_LP_MODE_EN 0x80 |
| #define C6DOFIMU4_GYRO_STANDBY 0x10 |
| #define C6DOFIMU4_I2C_IF_DIS 0x40 |
| #define C6DOFIMU4_I2C_IF_EN 0x00 |
| #define C6DOFIMU4_INT_DRDY_PIN_ACT_HIGH 0x00 |
| #define C6DOFIMU4_INT_DRDY_PIN_ACT_LOW 0x80 |
| #define C6DOFIMU4_INT_DRDY_PIN_OPEN_DRAIN 0x40 |
| #define C6DOFIMU4_INT_DRDY_PIN_PULSE 0x00 |
| #define C6DOFIMU4_INT_DRDY_PIN_PUSH_PULL 0x00 |
| #define C6DOFIMU4_INT_DRDY_PIN_STAT_CLEARED 0x20 |
| #define C6DOFIMU4_INT_STAT_CLEARED_ANY_READ 0x10 |
| #define C6DOFIMU4_INT_STAT_CLEARED_STAT_REG_READ 0x00 |
| #define C6DOFIMU4_INT_STATUS_NOT_OCCURED 0x00 |
| #define C6DOFIMU4_OUTPUT_LIMIT_EN 0x02 |
| #define C6DOFIMU4_SLEEP 0x40 |
| #define C6DOFIMU4_STBY_XA 0x20 |
| #define C6DOFIMU4_STBY_XG 0x04 |
| #define C6DOFIMU4_STBY_YA 0x10 |
| #define C6DOFIMU4_STBY_YG 0x02 |
| #define C6DOFIMU4_STBY_ZA 0x08 |
| #define C6DOFIMU4_STBY_ZG 0x01 |
| #define C6DOFIMU4_TEMP_DIS 0x08 |
| #define C6DOFIMU4_TEMP_RST 0x01 |
| #define C6DOFIMU4_WOM_TH_MODE_AND 0x01 |
| #define C6DOFIMU4_WOM_TH_MODE_OR 0x00 |
| #define C6DOFIMU4_WOM_X_INT_MASK 0x80 |
| #define C6DOFIMU4_WOM_X_INT_OCCURED 0x80 |
| #define C6DOFIMU4_WOM_Y_INT_MASK 0x40 |
| #define C6DOFIMU4_WOM_Y_INT_OCCURED 0x40 |
| #define C6DOFIMU4_WOM_Z_INT_MASK 0x20 |
| #define C6DOFIMU4_WOM_Z_INT_OCCURED 0x20 |
| #define C6DOFIMU4_XA_ST 0x80 |
| #define C6DOFIMU4_XG_ST 0x80 |
| #define C6DOFIMU4_YA_ST 0x40 |
| #define C6DOFIMU4_YG_ST 0x40 |
| #define C6DOFIMU4_ZA_ST 0x20 |
| #define C6DOFIMU4_ZG_ST 0x20 |