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c6dofimu4 2.0.0.0
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| #define C6DOFIMU4_ACCEL_CONFIG2_REG 0x1D |
| #define C6DOFIMU4_ACCEL_CONFIG_REG 0x1C |
| #define C6DOFIMU4_ACCEL_INTEL_CTRL_REG 0x69 |
| #define C6DOFIMU4_ACCEL_WOM_X_THR_REG 0x20 |
| #define C6DOFIMU4_ACCEL_WOM_Y_THR_REG 0x21 |
| #define C6DOFIMU4_ACCEL_WOM_Z_THR_REG 0x22 |
| #define C6DOFIMU4_ACCEL_XOUT_REG 0x3B |
| #define C6DOFIMU4_ACCEL_YOUT_REG 0x3D |
| #define C6DOFIMU4_ACCEL_ZOUT_REG 0x3F |
| #define C6DOFIMU4_CONFIG_REG 0x1A |
| #define C6DOFIMU4_FIFO_COUNT_REG 0x72 |
| #define C6DOFIMU4_FIFO_EN_REG 0x23 |
| #define C6DOFIMU4_FIFO_R_W_REG 0x74 |
| #define C6DOFIMU4_FIFO_WM_INT_STATUS_REG 0x39 |
| #define C6DOFIMU4_FIFO_WM_TH_REG 0x60 |
| #define C6DOFIMU4_FSYNC_INT_REG 0x36 |
| #define C6DOFIMU4_GYRO_CONFIG_REG 0x1B |
| #define C6DOFIMU4_GYRO_XOUT_REG 0x43 |
| #define C6DOFIMU4_GYRO_YOUT_REG 0x45 |
| #define C6DOFIMU4_GYRO_ZOUT_REG 0x47 |
| #define C6DOFIMU4_I2C_IF_REG 0x70 |
| #define C6DOFIMU4_INT_ENABLE_REG 0x38 |
| #define C6DOFIMU4_INT_PIN_CFG_REG 0x37 |
| #define C6DOFIMU4_INT_STATUS_REG 0x3A |
| #define C6DOFIMU4_LP_MODE_CFG_REG 0x1E |
| #define C6DOFIMU4_PWR_MGMT_1_REG 0x6B |
| #define C6DOFIMU4_PWR_MGMT_2_REG 0x6C |
| #define C6DOFIMU4_SELF_TEST_X_GYRO_REG 0x50 |
| #define C6DOFIMU4_SELF_TEST_X_REG 0x0D |
| #define C6DOFIMU4_SELF_TEST_Y_GYRO_REG 0x51 |
| #define C6DOFIMU4_SELF_TEST_Y_REG 0x0E |
| #define C6DOFIMU4_SELF_TEST_Z_GYRO_REG 0x52 |
| #define C6DOFIMU4_SELF_TEST_Z_REG 0x0F |
| #define C6DOFIMU4_SIGNAL_PATH_RESET_REG 0x68 |
| #define C6DOFIMU4_SMPLRT_DIV_REG 0x19 |
| #define C6DOFIMU4_TEMP_OUT_REG 0x41 |
| #define C6DOFIMU4_USER_CTRL_REG 0x6A |
| #define C6DOFIMU4_WHO_AM_I_REG 0x75 |
| #define C6DOFIMU4_XA_OFFSET_REG 0x77 |
| #define C6DOFIMU4_XG_OFFS_TC_REG 0x04 |
| #define C6DOFIMU4_XG_OFFS_USR_REG 0x13 |
| #define C6DOFIMU4_YA_OFFSET_REG 0x7A |
| #define C6DOFIMU4_YG_OFFS_TC_REG 0x07 |
| #define C6DOFIMU4_YG_OFFS_USR_REG 0x15 |
| #define C6DOFIMU4_ZA_OFFSET_REG 0x7D |
| #define C6DOFIMU4_ZG_OFFS_TC_REG 0x0A |
| #define C6DOFIMU4_ZG_OFFS_USR_REG 0x17 |