ccrf2 2.0.0.0
ccrf2.h
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1/*
2 * MikroSDK - MikroE Software Development Kit
3 * Copyright© 2020 MikroElektronika d.o.o.
4 *
5 * Permission is hereby granted, free of charge, to any person
6 * obtaining a copy of this software and associated documentation
7 * files (the "Software"), to deal in the Software without restriction,
8 * including without limitation the rights to use, copy, modify, merge,
9 * publish, distribute, sublicense, and/or sell copies of the Software,
10 * and to permit persons to whom the Software is furnished to do so,
11 * subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be
14 * included in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
22 * OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
33// ----------------------------------------------------------------------------
34
35#ifndef CCRF2_H
36#define CCRF2_H
37
42#ifdef PREINIT_SUPPORTED
43#include "preinit.h"
44#endif
45
46#ifdef MikroCCoreVersion
47 #if MikroCCoreVersion >= 1
48 #include "delays.h"
49 #endif
50#endif
51
52#include "drv_digital_out.h"
53#include "drv_digital_in.h"
54#include "drv_spi_master.h"
55
56// -------------------------------------------------------------- PUBLIC MACROS
67#define CCRF2_MAP_MIKROBUS( cfg, mikrobus ) \
68 cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
69 cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
70 cfg.sck = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
71 cfg.cs = MIKROBUS( mikrobus, MIKROBUS_CS ); \
72 cfg.gp0 = MIKROBUS( mikrobus, MIKROBUS_AN ); \
73 cfg.rst = MIKROBUS( mikrobus, MIKROBUS_RST ); \
74 cfg.gp2 = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
75 cfg.gp3 = MIKROBUS( mikrobus, MIKROBUS_INT )
82#define CCRF2_RETVAL uint8_t
83
84#define CCRF2_OK 0x00
85#define CCRF2_INIT_ERROR 0xFF
92#define CCRF2_STATUS_T uint8_t
99#define CCRF2_IOCFG3 0x0000
100#define CCRF2_IOCFG2 0x0001
101#define CCRF2_IOCFG1 0x0002
102#define CCRF2_IOCFG0 0x0003
103#define CCRF2_SYNC3 0x0004
104#define CCRF2_SYNC2 0x0005
105#define CCRF2_SYNC1 0x0006
106#define CCRF2_SYNC0 0x0007
107#define CCRF2_SYNC_CFG1 0x0008
108#define CCRF2_SYNC_CFG0 0x0009
109#define CCRF2_DEVIATION_M 0x000A
110#define CCRF2_MODCFG_DEV_E 0x000B
111#define CCRF2_DCFILT_CFG 0x000C
112#define CCRF2_PREAMBLE_CFG1 0x000D
113#define CCRF2_PREAMBLE_CFG0 0x000E
114#define CCRF2_FREQ_IF_CFG 0x000F
115#define CCRF2_IQIC 0x0010
116#define CCRF2_CHAN_BW 0x0011
117#define CCRF2_MDMCFG1 0x0012
118#define CCRF2_MDMCFG0 0x0013
119#define CCRF2_SYMBOL_RATE2 0x0014
120#define CCRF2_SYMBOL_RATE1 0x0015
121#define CCRF2_SYMBOL_RATE0 0x0016
122#define CCRF2_AGC_REF 0x0017
123#define CCRF2_AGC_CS_THR 0x0018
124#define CCRF2_AGC_GAIN_ADJUST 0x0019
125#define CCRF2_AGC_CFG3 0x001A
126#define CCRF2_AGC_CFG2 0x001B
127#define CCRF2_AGC_CFG1 0x001C
128#define CCRF2_AGC_CFG0 0x001D
129#define CCRF2_FIFO_CFG 0x001E
130#define CCRF2_DEV_ADDR 0x001F
131#define CCRF2_SETTLING_CFG 0x0020
132#define CCRF2_FS_CFG 0x0021
133#define CCRF2_WOR_CFG1 0x0022
134#define CCRF2_WOR_CFG0 0x0023
135#define CCRF2_WOR_EVENT0_MSB 0x0024
136#define CCRF2_WOR_EVENT0_LSB 0x0025
137#define CCRF2_PKT_CFG2 0x0026
138#define CCRF2_PKT_CFG1 0x0027
139#define CCRF2_PKT_CFG0 0x0028
140#define CCRF2_RFEND_CFG1 0x0029
141#define CCRF2_RFEND_CFG0 0x002A
142#define CCRF2_PA_CFG2 0x002B
143#define CCRF2_PA_CFG1 0x002C
144#define CCRF2_PA_CFG0 0x002D
145#define CCRF2_PKT_LEN 0x002E
152#define CCRF2_IF_MIX_CFG 0x2F00
153#define CCRF2_FREQOFF_CFG 0x2F01
154#define CCRF2_TOC_CFG 0x2F02
155#define CCRF2_MARC_SPARE 0x2F03
156#define CCRF2_ECG_CFG 0x2F04
157#define CCRF2_CFM_DATA_CFG 0x2F05
158#define CCRF2_EXT_CTRL 0x2F06
159#define CCRF2_RCCAL_FINE 0x2F07
160#define CCRF2_RCCAL_COARSE 0x2F08
161#define CCRF2_RCCAL_OFFSET 0x2F09
162#define CCRF2_FREQOFF1 0x2F0A
163#define CCRF2_FREQOFF0 0x2F0B
164#define CCRF2_FREQ2 0x2F0C
165#define CCRF2_FREQ1 0x2F0D
166#define CCRF2_FREQ0 0x2F0E
167#define CCRF2_IF_ADC2 0x2F0F
168#define CCRF2_IF_ADC1 0x2F10
169#define CCRF2_IF_ADC0 0x2F11
170#define CCRF2_FS_DIG1 0x2F12
171#define CCRF2_FS_DIG0 0x2F13
172#define CCRF2_FS_CAL3 0x2F14
173#define CCRF2_FS_CAL2 0x2F15
174#define CCRF2_FS_CAL1 0x2F16
175#define CCRF2_FS_CAL0 0x2F17
176#define CCRF2_FS_CHP 0x2F18
177#define CCRF2_FS_DIVTWO 0x2F19
178#define CCRF2_FS_DSM1 0x2F1A
179#define CCRF2_FS_DSM0 0x2F1B
180#define CCRF2_FS_DVC1 0x2F1C
181#define CCRF2_FS_DVC0 0x2F1D
182#define CCRF2_FS_LBI 0x2F1E
183#define CCRF2_FS_PFD 0x2F1F
184#define CCRF2_FS_PRE 0x2F20
185#define CCRF2_FS_REG_DIV_CML 0x2F21
186#define CCRF2_FS_SPARE 0x2F22
187#define CCRF2_FS_VCO4 0x2F23
188#define CCRF2_FS_VCO3 0x2F24
189#define CCRF2_FS_VCO2 0x2F25
190#define CCRF2_FS_VCO1 0x2F26
191#define CCRF2_FS_VCO0 0x2F27
192#define CCRF2_GBIAS6 0x2F28
193#define CCRF2_GBIAS5 0x2F29
194#define CCRF2_GBIAS4 0x2F2A
195#define CCRF2_GBIAS3 0x2F2B
196#define CCRF2_GBIAS2 0x2F2C
197#define CCRF2_GBIAS1 0x2F2D
198#define CCRF2_GBIAS0 0x2F2E
199#define CCRF2_IFAMP 0x2F2F
200#define CCRF2_LNA 0x2F30
201#define CCRF2_RXMIX 0x2F31
202#define CCRF2_XOSC5 0x2F32
203#define CCRF2_XOSC4 0x2F33
204#define CCRF2_XOSC3 0x2F34
205#define CCRF2_XOSC2 0x2F35
206#define CCRF2_XOSC1 0x2F36
207#define CCRF2_XOSC0 0x2F37
208#define CCRF2_ANALOG_SPARE 0x2F38
209#define CCRF2_PA_CFG3 0x2F39
210#define CCRF2_IRQ0M 0x2F3F
211#define CCRF2_IRQ0F 0x2F40
218#define CCRF2_WOR_TIME1 0x2F64
219#define CCRF2_WOR_TIME0 0x2F65
220#define CCRF2_WOR_CAPTURE1 0x2F66
221#define CCRF2_WOR_CAPTURE0 0x2F67
222#define CCRF2_BIST 0x2F68
223#define CCRF2_DCFILTOFFSET_I1 0x2F69
224#define CCRF2_DCFILTOFFSET_I0 0x2F6A
225#define CCRF2_DCFILTOFFSET_Q1 0x2F6B
226#define CCRF2_DCFILTOFFSET_Q0 0x2F6C
227#define CCRF2_IQIE_I1 0x2F6D
228#define CCRF2_IQIE_I0 0x2F6E
229#define CCRF2_IQIE_Q1 0x2F6F
230#define CCRF2_IQIE_Q0 0x2F70
231#define CCRF2_RSSI1 0x2F71
232#define CCRF2_RSSI0 0x2F72
233#define CCRF2_MARCSTATE 0x2F73
234#define CCRF2_LQI_VAL 0x2F74
235#define CCRF2_PQT_SYNC_ERR 0x2F75
236#define CCRF2_DEM_STATUS 0x2F76
237#define CCRF2_FREQOFF_EST1 0x2F77
238#define CCRF2_FREQOFF_EST0 0x2F78
239#define CCRF2_AGC_GAIN3 0x2F79
240#define CCRF2_AGC_GAIN2 0x2F7A
241#define CCRF2_AGC_GAIN1 0x2F7B
242#define CCRF2_AGC_GAIN0 0x2F7C
243#define CCRF2_CFM_RX_DATA_OUT 0x2F7D
244#define CCRF2_CFM_TX_DATA_IN 0x2F7E
245#define CCRF2_ASK_SOFT_RX_DATA 0x2F7F
246#define CCRF2_RNDGEN 0x2F80
247#define CCRF2_MAGN2 0x2F81
248#define CCRF2_MAGN1 0x2F82
249#define CCRF2_MAGN0 0x2F83
250#define CCRF2_ANG1 0x2F84
251#define CCRF2_ANG0 0x2F85
252#define CCRF2_CHFILT_I2 0x2F86
253#define CCRF2_CHFILT_I1 0x2F87
254#define CCRF2_CHFILT_I0 0x2F88
255#define CCRF2_CHFILT_Q2 0x2F89
256#define CCRF2_CHFILT_Q1 0x2F8A
257#define CCRF2_CHFILT_Q0 0x2F8B
258#define CCRF2_GPIO_STATUS 0x2F8C
259#define CCRF2_FSCAL_CTRL 0x2F8D
260#define CCRF2_PHASE_ADJUST 0x2F8E
261#define CCRF2_PARTNUMBER 0x2F8F
262#define CCRF2_PARTVERSION 0x2F90
263#define CCRF2_SERIAL_STATUS 0x2F91
264#define CCRF2_MODEM_STATUS1 0x2F92
265#define CCRF2_MODEM_STATUS0 0x2F93
266#define CCRF2_MARC_STATUS1 0x2F94
267#define CCRF2_MARC_STATUS0 0x2F95
268#define CCRF2_PA_IFAMP_TEST 0x2F96
269#define CCRF2_FSRF_TEST 0x2F97
270#define CCRF2_PRE_TEST 0x2F98
271#define CCRF2_PRE_OVR 0x2F99
272#define CCRF2_ADC_TEST 0x2F9A
273#define CCRF2_DVC_TEST 0x2F9B
274#define CCRF2_ATEST 0x2F9C
275#define CCRF2_ATEST_LVDS 0x2F9D
276#define CCRF2_ATEST_MODE 0x2F9E
277#define CCRF2_XOSC_TEST1 0x2F9F
278#define CCRF2_XOSC_TEST0 0x2FA0
279
280#define CCRF2_RXFIRST 0x2FD2
281#define CCRF2_TXFIRST 0x2FD3
282#define CCRF2_RXLAST 0x2FD4
283#define CCRF2_TXLAST 0x2FD5
284#define CCRF2_NUM_TXBYTES 0x2FD6
285#define CCRF2_NUM_RXBYTES 0x2FD7
286#define CCRF2_FIFO_NUM_TXBYTES 0x2FD8
287#define CCRF2_FIFO_NUM_RXBYTES 0x2FD9
294#define CCRF2_SINGLE_TXFIFO 0x003F
295#define CCRF2_BURST_TXFIFO 0x007F
296#define CCRF2_SINGLE_RXFIFO 0x00BF
297#define CCRF2_BURST_RXFIFO 0x00FF
298
299#define CCRF2_LQI_CRC_OK_BM 0x80
300#define CCRF2_LQI_EST_BM 0x7F
307#define CCRF2_SRES 0x30
308#define CCRF2_SFSTXON 0x31
309#define CCRF2_SXOFF 0x32
310#define CCRF2_SCAL 0x33
311#define CCRF2_SRX 0x34
312#define CCRF2_STX 0x35
313#define CCRF2_SIDLE 0x36
314#define CCRF2_SWOR 0x38
315#define CCRF2_SPWD 0x39
316#define CCRF2_SFRX 0x3A
317#define CCRF2_SFTX 0x3B
318#define CCRF2_SWORRST 0x3C
319#define CCRF2_SNOP 0x3D
320#define CCRF2_AFC 0x37
327#define CCRF2_STATE_IDLE 0x00
328#define CCRF2_STATE_RX 0x10
329#define CCRF2_STATE_TX 0x20
330#define CCRF2_STATE_FSTXON 0x30
331#define CCRF2_STATE_CALIBRATE 0x40
332#define CCRF2_STATE_SETTLING 0x50
333#define CCRF2_STATE_RXFIFO_ERROR 0x60
334#define CCRF2_STATE_TXFIFO_ERROR 0x70
335
336#define CCRF2_RADIO_BURST_ACCESS 0x40
337#define CCRF2_RADIO_SINGLE_ACCESS 0x00
338#define CCRF2_RADIO_READ_ACCESS 0x80
339#define CCRF2_RADIO_WRITE_ACCESS 0x00
346#define CCRF2_STATUS_CHIP_RDYn_BM 0x80
347#define CCRF2_STATUS_STATE_BM 0x70
348#define CCRF2_STATUS_FIFO_BYTES_AVA_BM 0x0F
349
350#define CCRF2_STATUS_ERROR 0x00
351#define CCRF2_STATUS_OK 0x01
352
353#define CCRF2_IDLE_MODE 0x01
354#define CCRF2_TX_MODE 0x02
355#define CCRF2_RX_MODE 0x03
357 // End group macro
358// --------------------------------------------------------------- PUBLIC TYPES
367typedef struct
368{
369 // Output pins
370
371 digital_out_t cs;
372 digital_out_t rst;
373
374 // Input pins
375
376 digital_in_t gp0;
377 digital_in_t gp2;
378 digital_in_t gp3;
379 digital_in_t miso;
380
381 // Modules
382
383 spi_master_t spi;
384 pin_name_t chip_select;
385
387} ccrf2_t;
388
392typedef struct
393{
394 // Communication gpio pins
395
396 pin_name_t miso;
397 pin_name_t mosi;
398 pin_name_t sck;
399 pin_name_t cs;
400
401 // Additional gpio pins
402
403 pin_name_t gp0;
404 pin_name_t rst;
405 pin_name_t gp2;
406 pin_name_t gp3;
407
408 // static variable
409
410 uint32_t spi_speed;
411 spi_master_mode_t spi_mode;
412 spi_master_chip_select_polarity_t cs_polarity;
414
415 // End types group
416// ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS
417
422#ifdef __cplusplus
423extern "C"{
424#endif
425
435
445
454
466
478uint8_t ccrf2_cmd_strobe ( ccrf2_t *ctx, uint8_t cmd );
479
491void ccrf2_read_write_burst_single ( ccrf2_t *ctx, uint8_t reg_address, uint8_t *rw_data, uint16_t n_bytes );
492
507uint8_t ccrf2_8bit_reg_access ( ccrf2_t *ctx, char access_type, uint8_t reg_address, uint8_t *rw_data,
508 uint16_t n_bytes );
509
525uint8_t ccrf2_16bit_reg_access ( ccrf2_t *ctx, uint8_t access_type, uint8_t ext_address,
526 uint8_t reg_address, uint8_t *rw_data, uint8_t n_bytes );
527
541uint8_t ccrf2_read_reg ( ccrf2_t *ctx, uint16_t reg_address, uint8_t *read_data, uint8_t n_bytes );
542
556uint8_t ccrf2_write_reg ( ccrf2_t *ctx, uint16_t reg_address, uint8_t *write_data, uint8_t n_bytes );
557
570uint8_t ccrf2_write_reg_single( ccrf2_t *ctx, uint16_t reg_address, uint8_t write_data );
571
584uint8_t ccrf2_write_tx_fifo ( ccrf2_t *ctx, uint8_t *write_data, uint8_t n_bytes );
585
599uint8_t ccrf2_read_rx_fifo ( ccrf2_t *ctx, uint8_t *read_data, uint8_t n_bytes );
600
610
620
631
640uint8_t ccrf2_read_gp0 ( ccrf2_t *ctx );
641
650uint8_t ccrf2_read_gp2 ( ccrf2_t *ctx );
651
660uint8_t ccrf2_read_gp3 ( ccrf2_t *ctx );
661
672void ccrf2_send_tx_data ( ccrf2_t *ctx, uint8_t *tx_data, uint8_t n_bytes );
673
686uint8_t ccrf2_receive_rx_data ( ccrf2_t *ctx, uint8_t *rx_data );
687
688#ifdef __cplusplus
689}
690#endif
691#endif // _CCRF2_H_
692
693 // End public_function group
695
696// ------------------------------------------------------------------------- END
#define CCRF2_RETVAL
Definition ccrf2.h:82
uint8_t ccrf2_write_reg(ccrf2_t *ctx, uint16_t reg_address, uint8_t *write_data, uint8_t n_bytes)
Write sequential data function.
void ccrf2_read_write_burst_single(ccrf2_t *ctx, uint8_t reg_address, uint8_t *rw_data, uint16_t n_bytes)
Read or write burst single function.
uint8_t ccrf2_read_gp3(ccrf2_t *ctx)
Read state of GP3 pin function.
uint8_t ccrf2_16bit_reg_access(ccrf2_t *ctx, uint8_t access_type, uint8_t ext_address, uint8_t reg_address, uint8_t *rw_data, uint8_t n_bytes)
Access 16-bit register function.
void ccrf2_set_rx_mode(ccrf2_t *ctx)
Set RX mode function.
void ccrf2_default_cfg(ccrf2_t *ctx)
Click Default Configuration function.
uint8_t ccrf2_read_gp2(ccrf2_t *ctx)
Read state of GP2 pin function.
uint8_t ccrf2_receive_rx_data(ccrf2_t *ctx, uint8_t *rx_data)
Receive RX data function.
CCRF2_RETVAL ccrf2_init(ccrf2_t *ctx, ccrf2_cfg_t *cfg)
Initialization function.
void ccrf2_set_tx_mode(ccrf2_t *ctx)
Set TX mode function.
uint8_t ccrf2_read_rx_fifo(ccrf2_t *ctx, uint8_t *read_data, uint8_t n_bytes)
Read RX FIFO register function.
uint8_t ccrf2_write_reg_single(ccrf2_t *ctx, uint16_t reg_address, uint8_t write_data)
Write one byte data function.
uint8_t ccrf2_write_tx_fifo(ccrf2_t *ctx, uint8_t *write_data, uint8_t n_bytes)
Write TX FIFO register function.
uint8_t ccrf2_cmd_strobe(ccrf2_t *ctx, uint8_t cmd)
Set command strobe function.
void ccrf2_hw_reset(ccrf2_t *ctx)
Hardware reset function.
uint8_t ccrf2_read_reg(ccrf2_t *ctx, uint16_t reg_address, uint8_t *read_data, uint8_t n_bytes)
Read the byte of data function.
void ccrf2_manual_calibration(ccrf2_t *ctx)
Manual calibration function.
uint8_t ccrf2_read_gp0(ccrf2_t *ctx)
Read state of GP0 pin function.
uint8_t ccrf2_8bit_reg_access(ccrf2_t *ctx, char access_type, uint8_t reg_address, uint8_t *rw_data, uint16_t n_bytes)
Access 8-bit register function.
void ccrf2_send_tx_data(ccrf2_t *ctx, uint8_t *tx_data, uint8_t n_bytes)
Send TX data function.
void ccrf2_cfg_setup(ccrf2_cfg_t *cfg)
Config Object Initialization function.
Click configuration structure definition.
Definition ccrf2.h:393
pin_name_t gp0
Definition ccrf2.h:403
pin_name_t gp2
Definition ccrf2.h:405
pin_name_t gp3
Definition ccrf2.h:406
spi_master_chip_select_polarity_t cs_polarity
Definition ccrf2.h:412
pin_name_t sck
Definition ccrf2.h:398
spi_master_mode_t spi_mode
Definition ccrf2.h:411
pin_name_t mosi
Definition ccrf2.h:397
uint32_t spi_speed
Definition ccrf2.h:410
pin_name_t miso
Definition ccrf2.h:396
pin_name_t rst
Definition ccrf2.h:404
pin_name_t cs
Definition ccrf2.h:399
Click ctx object definition.
Definition ccrf2.h:368
digital_out_t cs
Definition ccrf2.h:371
spi_master_t spi
Definition ccrf2.h:383
digital_in_t miso
Definition ccrf2.h:379
uint16_t packet_counter
Definition ccrf2.h:386
digital_in_t gp2
Definition ccrf2.h:377
digital_in_t gp0
Definition ccrf2.h:376
digital_in_t gp3
Definition ccrf2.h:378
digital_out_t rst
Definition ccrf2.h:372
pin_name_t chip_select
Definition ccrf2.h:384