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#define | CLOCKGEN_MAP_MIKROBUS(cfg, mikrobus) |
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#define | CLOCKGEN_RETVAL uint8_t |
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#define | CLOCKGEN_OK 0x00 |
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#define | CLOCKGEN_INIT_ERROR 0xFF |
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#define | CLOCKGEN_SLAVE_ADDRESS 0x60 |
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#define | CLOCKGEN_REG_DEV_STATUS 0 |
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#define | CLOCKGEN_REG_INT_STATUS_STICKY 1 |
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#define | CLOCKGEN_REG_INT_STATUS_MASK 2 |
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#define | CLOCKGEN_REG_OUTPUT_ENABLE_CTRL 3 |
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#define | CLOCKGEN_REG_OEB_EN_CTRL_MASK 9 |
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#define | CLOCKGEN_REG_PLL_IN_SRC 15 |
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#define | CLOCKGEN_REG_CLK0_CTRL 16 |
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#define | CLOCKGEN_REG_CLK1_CTRL 17 |
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#define | CLOCKGEN_REG_CLK2_CTRL 18 |
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#define | CLOCKGEN_REG_CLK3_CTRL 19 |
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#define | CLOCKGEN_REG_CLK4_CTRL 20 |
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#define | CLOCKGEN_REG_CLK5_CTRL 21 |
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#define | CLOCKGEN_REG_CLK6_CTRL 22 |
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#define | CLOCKGEN_REG_CLK7_CTRL 23 |
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#define | CLOCKGEN_REG_CLK3_0_DIS_STATE 24 |
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#define | CLOCKGEN_REG_CLK7_4_DIS_STATE 25 |
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#define | CLOCKGEN_REG_MULTI_NA_PARAM3_B15_8 26 |
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#define | CLOCKGEN_REG_MULTI_NA_PARAM3_B7_0 27 |
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#define | CLOCKGEN_REG_MULTI_NA_PARAM1_B17_16 28 |
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#define | CLOCKGEN_REG_MULTI_NA_PARAM1_B15_8 29 |
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#define | CLOCKGEN_REG_MULTI_NA_PARAM1_B7_0 30 |
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#define | CLOCKGEN_REG_MULTI_NA_PARAM3_2_B19_16 31 |
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#define | CLOCKGEN_REG_MULTI_NA_PARAM2_B15_8 32 |
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#define | CLOCKGEN_REG_MULTI_NA_PARAM2_B7_0 33 |
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#define | CLOCKGEN_REG_MULTI_NB_PARAM3_B15_8 34 |
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#define | CLOCKGEN_REG_MULTI_NB_PARAM3_B7_0 35 |
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#define | CLOCKGEN_REG_MULTI_NB_PARAM1_B17_16 36 |
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#define | CLOCKGEN_REG_MULTI_NB_PARAM1_B15_8 37 |
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#define | CLOCKGEN_REG_MULTI_NB_PARAM1_B7_0 38 |
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#define | CLOCKGEN_REG_MULTI_NB_PARAM3_2_B19_16 39 |
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#define | CLOCKGEN_REG_MULTI_NB_PARAM2_B15_8 40 |
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#define | CLOCKGEN_REG_MULTI_NB_PARAM2_B7_0 41 |
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#define | CLOCKGEN_REG_MULTI_0_PARAM3_B15_8 42 |
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#define | CLOCKGEN_REG_MULTI_0_PARAM3_B7_0 43 |
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#define | CLOCKGEN_REG_MULTI_0_PARAM1_B17_16_DIVS 44 |
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#define | CLOCKGEN_REG_MULTI_0_PARAM1_B15_8 45 |
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#define | CLOCKGEN_REG_MULTI_0_PARAM1_B7_0 46 |
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#define | CLOCKGEN_REG_MULTI_0_PARAM3_2_B19_16 47 |
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#define | CLOCKGEN_REG_MULTI_0_PARAM2_B15_8 48 |
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#define | CLOCKGEN_REG_MULTI_0_PARAM2_B7_0 49 |
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#define | CLOCKGEN_REG_MULTI_1_PARAM3_B15_8 50 |
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#define | CLOCKGEN_REG_MULTI_1_PARAM3_B7_0 51 |
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#define | CLOCKGEN_REG_MULTI_1_PARAM1_B17_16_DIVS 52 |
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#define | CLOCKGEN_REG_MULTI_1_PARAM1_B15_8 53 |
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#define | CLOCKGEN_REG_MULTI_1_PARAM1_B7_0 54 |
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#define | CLOCKGEN_REG_MULTI_1_PARAM3_2_B19_16 55 |
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#define | CLOCKGEN_REG_MULTI_1_PARAM2_B15_8 56 |
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#define | CLOCKGEN_REG_MULTI_1_PARAM2_B7_0 57 |
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#define | CLOCKGEN_REG_MULTI_2_PARAM3_B15_8 58 |
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#define | CLOCKGEN_REG_MULTI_2_PARAM3_B7_0 59 |
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#define | CLOCKGEN_REG_MULTI_2_PARAM1_B17_16_DIVS 60 |
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#define | CLOCKGEN_REG_MULTI_2_PARAM1_B15_8 61 |
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#define | CLOCKGEN_REG_MULTI_2_PARAM1_B7_0 62 |
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#define | CLOCKGEN_REG_MULTI_2_PARAM3_2_B19_16 63 |
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#define | CLOCKGEN_REG_MULTI_2_PARAM2_B15_8 64 |
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#define | CLOCKGEN_REG_MULTI_2_PARAM2_B7_0 65 |
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#define | CLOCKGEN_REG_MULTI_3_PARAM3_B15_8 66 |
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#define | CLOCKGEN_REG_MULTI_3_PARAM3_B7_0 67 |
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#define | CLOCKGEN_REG_MULTI_3_PARAM1_B17_16_DIVS 68 |
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#define | CLOCKGEN_REG_MULTI_3_PARAM1_B15_8 69 |
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#define | CLOCKGEN_REG_MULTI_3_PARAM1_B7_0 70 |
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#define | CLOCKGEN_REG_MULTI_3_PARAM3_2_B19_16 71 |
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#define | CLOCKGEN_REG_MULTI_3_PARAM2_B15_8 72 |
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#define | CLOCKGEN_REG_MULTI_3_PARAM2_B7_0 73 |
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#define | CLOCKGEN_REG_MULTI_4_PARAM3_B15_8 74 |
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#define | CLOCKGEN_REG_MULTI_4_PARAM3_B7_0 75 |
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#define | CLOCKGEN_REG_MULTI_4_PARAM1_B17_16_DIVS 76 |
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#define | CLOCKGEN_REG_MULTI_4_PARAM1_B15_8 77 |
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#define | CLOCKGEN_REG_MULTI_4_PARAM1_B7_0 78 |
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#define | CLOCKGEN_REG_MULTI_4_PARAM3_2_B19_16 79 |
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#define | CLOCKGEN_REG_MULTI_4_PARAM2_B15_8 80 |
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#define | CLOCKGEN_REG_MULTI_4_PARAM2_B7_0 81 |
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#define | CLOCKGEN_REG_MULTI_5_PARAM3_B15_8 82 |
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#define | CLOCKGEN_REG_MULTI_5_PARAM3_B7_0 83 |
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#define | CLOCKGEN_REG_MULTI_5_PARAM1_B17_16_DIVS 84 |
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#define | CLOCKGEN_REG_MULTI_5_PARAM1_B15_8 85 |
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#define | CLOCKGEN_REG_MULTI_5_PARAM1_B7_0 86 |
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#define | CLOCKGEN_REG_MULTI_5_PARAM3_2_B19_16 87 |
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#define | CLOCKGEN_REG_MULTI_5_PARAM2_B15_8 88 |
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#define | CLOCKGEN_REG_MULTI_5_PARAM2_B7_0 89 |
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#define | CLOCKGEN_REG_MULTI_6_PARAM3_B15_8 90 |
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#define | CLOCKGEN_REG_MULTI_6_PARAM3_B7_0 91 |
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#define | CLOCKGEN_REG_MULTI_6_PARAM1_B17_16_DIVS 92 |
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#define | CLOCKGEN_REG_MULTI_6_PARAM1_B15_8 93 |
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#define | CLOCKGEN_REG_MULTI_6_PARAM1_B7_0 94 |
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#define | CLOCKGEN_REG_MULTI_6_PARAM3_2_B19_16 95 |
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#define | CLOCKGEN_REG_MULTI_6_PARAM2_B15_8 96 |
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#define | CLOCKGEN_REG_MULTI_6_PARAM2_B7_0 97 |
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#define | CLOCKGEN_REG_MULTI_7_PARAM3_B15_8 98 |
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#define | CLOCKGEN_REG_MULTI_7_PARAM3_B7_0 99 |
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#define | CLOCKGEN_REG_MULTI_7_PARAM1_B17_16_DIVS 100 |
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#define | CLOCKGEN_REG_MULTI_7_PARAM1_B15_8 101 |
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#define | CLOCKGEN_REG_MULTI_7_PARAM1_B7_0 102 |
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#define | CLOCKGEN_REG_MULTI_7_PARAM3_2_B19_16 103 |
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#define | CLOCKGEN_REG_MULTI_7_PARAM2_B15_8 104 |
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#define | CLOCKGEN_REG_MULTI_7_PARAM2_B7_0 105 |
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#define | CLOCKGEN_REG_SPREAD_SPECTRUM_DOWN_PARAM2_EN_B14_8 149 |
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#define | CLOCKGEN_REG_SPREAD_SPECTRUM_DOWN_PARAM2_B7_0 150 |
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#define | CLOCKGEN_REG_SPREAD_SPECTRUM_DOWN_PARAM3_MODE_B14_8 151 |
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#define | CLOCKGEN_REG_SPREAD_SPECTRUM_DOWN_PARAM3_B7_0 152 |
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#define | CLOCKGEN_REG_SPREAD_SPECTRUM_DOWN_PARAM1_B7_0 153 |
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#define | CLOCKGEN_REG_SPREAD_SPECTRUM_DOWN_PARAM3_B11_8_UP_DWN 154 |
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#define | CLOCKGEN_REG_SPREAD_SPECTRUM_UP_DOWN_PLL_A 155 |
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#define | CLOCKGEN_REG_SPREAD_SPECTRUM_UP_PARAM2_B14_8 156 |
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#define | CLOCKGEN_REG_SPREAD_SPECTRUM_UP_PARAM2_B7_0 157 |
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#define | CLOCKGEN_REG_SPREAD_SPECTRUM_UP_PARAM3_B14_8 158 |
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#define | CLOCKGEN_REG_SPREAD_SPECTRUM_UP_PARAM3_B7_0 159 |
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#define | CLOCKGEN_REG_SPREAD_SPECTRUM_UP_PARAM1_B7_0 160 |
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#define | CLOCKGEN_REG_SPREAD_SPECTRUM_UP_PARAM1_B11_8 161 |
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#define | CLOCKGEN_REG_VCXO_PARAM_B7_0 162 |
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#define | CLOCKGEN_REG_VCXO_PARAM_B15_8 163 |
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#define | CLOCKGEN_REG_VCXO_PARAM_B21_16 164 |
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#define | CLOCKGEN_REG_CLK0_INIT_OFFSET 165 |
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#define | CLOCKGEN_REG_CLK1_INIT_OFFSET 166 |
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#define | CLOCKGEN_REG_CLK2_INIT_OFFSET 167 |
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#define | CLOCKGEN_REG_PLL_RST 177 |
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#define | CLOCKGEN_REG_CRYSTAL_INTERNAL_CL 183 |
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#define | CLOCKGEN_REG_FANOUT_EN 187 |
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#define | CLOCKGEN_CLOCK_0 0 |
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#define | CLOCKGEN_CLOCK_1 1 |
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#define | CLOCKGEN_CLOCK_2 2 |
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#define | CLOCKGEN_CLOCK_3 3 |
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#define | CLOCKGEN_CLOCK_4 4 |
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#define | CLOCKGEN_CLOCK_5 5 |
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#define | CLOCKGEN_CLOCK_6 6 |
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#define | CLOCKGEN_CLOCK_7 7 |
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#define | CLOCKGEN_DISABLE_ALL_CLK 8 |
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#define | CLOCKGEN_CLK_CTRL 16 |
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#define | CLOCKGEN_PLLA 0xFF |
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#define | CLOCKGEN_PLLB 0xDF |
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#define | CLOCKGEN_RESET_PLLA 0x20 |
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#define | CLOCKGEN_RESET_PLLB 0x80 |
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#define | CLOCKGEN_PLL_PARAMS 0xFA |
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#define | CLOCKGEN_CLK_PARAMS 0xFB |
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#define | CLOCKGEN_PARAM_DIV_4_EN 0x3 |
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#define | CLOCKGEN_PARAM_DIV_OTHER 0x0 |
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#define | CLOCKGEN_PARAM_DIV_1 0x0 |
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#define | CLOCKGEN_PARAM_DIV_2 0x1 |
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#define | CLOCKGEN_PARAM_DIV_4 0x2 |
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#define | CLOCKGEN_PARAM_DIV_8 0x3 |
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#define | CLOCKGEN_PARAM_DIV_16 0x4 |
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#define | CLOCKGEN_PARAM_DIV_32 0x5 |
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#define | CLOCKGEN_PARAM_DIV_64 0x6 |
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#define | CLOCKGEN_PARAM_DIV_128 0x7 |
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#define | CLOCKGEN_PLL_INPUT_XO 0 |
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#define | CLOCKGEN_PLL_INPUT_CLKIN 1 |
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#define | CLOCKGEN_FREQ_MULTY 100 |
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#define | CLOCKGEN_DIS_STATE_LOW 0 |
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#define | CLOCKGEN_DIS_STATE_HIGH 1 |
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#define | CLOCKGEN_DIS_STATE_HIGH_IMP 2 |
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#define | CLOCKGEN_DIS_STATE_NEVER_DIS 3 |
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#define | CLOCKGEN_PARAMS_MACRO 8 |
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#define | CLOCKGEN 0 |
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#define | CLOCKGEN_DISIABLE_STATE_SHIFT 2 |
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#define | CLOCKGEN_XTAL 25000000 |
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#define | CLOCKGEN_MAX_FREQ CLOCKGEN_XTAL * 32 |
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