Clock Gen 4 Registers Settings

Settings for registers of Clock Gen 4 Click driver. More...

Macros
#define	CLOCKGEN4_INCR_ENABLE   0x80
	Clock Gen 4 description setting.
#define	CLOCKGEN4_INCR_DISABLE   0x00
#define	CLOCKGEN4_PLL_UNLOCKED   0x00
	Clock Gen 4 device control.
#define	CLOCKGEN4_PLL_LOCKED   0x80
#define	CLOCKGEN4_AUX_OUT_EN   0x00
#define	CLOCKGEN4_AUX_OUT_DIS   0x02
#define	CLOCKGEN4_CLK_OUT_EN   0x00
#define	CLOCKGEN4_CLK_OUT_DIS   0x01
#define	CLOCKGEN4_R_MOD_SEL_L_0   0x00
	Clock Gen 4 device configuration 1.
#define	CLOCKGEN4_R_MOD_SEL_L_1   0x20
#define	CLOCKGEN4_R_MOD_SEL_L_2   0x40
#define	CLOCKGEN4_R_MOD_SEL_L_3   0x60
#define	CLOCKGEN4_R_MOD_SEL_R_1   0x80
#define	CLOCKGEN4_R_MOD_SEL_R_2   0xA0
#define	CLOCKGEN4_R_MOD_SEL_R_3   0xC0
#define	CLOCKGEN4_R_MOD_SEL_R_4   0xE0
#define	CLOCKGEN4_REG_CLK   0x00
#define	CLOCKGEN4_CLK_OUT   0x04
#define	CLOCKGEN4_PLL_STAT_IND   0x06
#define	CLOCKGEN4_DEV_CFG_1_EN   0x01
#define	CLOCKGEN4_DEV_CFG_1_DIS   0x00
#define	CLOCKGEN4_DEV_CFG_FRZ   0x00
	Clock Gen 4 global configuration.
#define	CLOCKGEN4_DEV_CFG_UNFRZ   0x08
#define	CLOCKGEN4_DEV_CFG_2_EN   0x01
#define	CLOCKGEN4_DEV_CFG_2_DIS   0x00
#define	CLOCKGEN4_AUX_OUT_ACT_H   0x00
	Clock Gen 4 function configuration 1.
#define	CLOCKGEN4_AUX_OUT_ACT_L   0x40
#define	CLOCKGEN4_REF_CLK_DIV_4   0x00
#define	CLOCKGEN4_REF_CLK_DIV_2   0x08
#define	CLOCKGEN4_REF_CLK_DIV_1   0x10
#define	CLOCKGEN4_CLK_OUT_UNL_L   0x00
	Clock Gen 4 function configuration 2.
#define	CLOCKGEN4_CLK_OUT_UNL_U   0x10
#define	CLOCKGEN4_REF_CLK_25_MHZ   25.0
	Clock Gen 4 input clock.
#define	CLOCKGEN4_I2C_ADR_GND   0x4E
	Clock Gen 4 device address setting.
#define	CLOCKGEN4_I2C_ADR_VCC   0x4F
#define	CLOCKGEN4_SPI_CHIP_ADR   0x9E
#define	CLOCKGEN4_SET_DATA_SAMPLE_EDGE   SET_SPI_DATA_SAMPLE_EDGE
	Data sample selection.
#define	CLOCKGEN4_SET_DATA_SAMPLE_MIDDLE   SET_SPI_DATA_SAMPLE_MIDDLE

Detailed Description

Settings for registers of Clock Gen 4 Click driver.

Macro Definition Documentation

CLOCKGEN4_AUX_OUT_ACT_H

#define CLOCKGEN4_AUX_OUT_ACT_H   0x00

Clock Gen 4 function configuration 1.

Function configuration 1 of Clock Gen 4 Click driver.

CLOCKGEN4_AUX_OUT_ACT_L

#define CLOCKGEN4_AUX_OUT_ACT_L   0x40

CLOCKGEN4_AUX_OUT_DIS

#define CLOCKGEN4_AUX_OUT_DIS   0x02

CLOCKGEN4_AUX_OUT_EN

#define CLOCKGEN4_AUX_OUT_EN   0x00

CLOCKGEN4_CLK_OUT

#define CLOCKGEN4_CLK_OUT   0x04

CLOCKGEN4_CLK_OUT_DIS

#define CLOCKGEN4_CLK_OUT_DIS   0x01

CLOCKGEN4_CLK_OUT_EN

#define CLOCKGEN4_CLK_OUT_EN   0x00

CLOCKGEN4_CLK_OUT_UNL_L

#define CLOCKGEN4_CLK_OUT_UNL_L   0x00

Clock Gen 4 function configuration 2.

Function configuration 2 of Clock Gen 4 Click driver.

CLOCKGEN4_CLK_OUT_UNL_U

#define CLOCKGEN4_CLK_OUT_UNL_U   0x10

CLOCKGEN4_DEV_CFG_1_DIS

#define CLOCKGEN4_DEV_CFG_1_DIS   0x00

CLOCKGEN4_DEV_CFG_1_EN

#define CLOCKGEN4_DEV_CFG_1_EN   0x01

CLOCKGEN4_DEV_CFG_2_DIS

#define CLOCKGEN4_DEV_CFG_2_DIS   0x00

CLOCKGEN4_DEV_CFG_2_EN

#define CLOCKGEN4_DEV_CFG_2_EN   0x01

CLOCKGEN4_DEV_CFG_FRZ

#define CLOCKGEN4_DEV_CFG_FRZ   0x00

Clock Gen 4 global configuration.

Global configuration of Clock Gen 4 Click driver.

CLOCKGEN4_DEV_CFG_UNFRZ

#define CLOCKGEN4_DEV_CFG_UNFRZ   0x08

CLOCKGEN4_I2C_ADR_GND

#define CLOCKGEN4_I2C_ADR_GND   0x4E

Clock Gen 4 device address setting.

Specified setting for device slave address selection of Clock Gen 4 Click driver.

CLOCKGEN4_I2C_ADR_VCC

#define CLOCKGEN4_I2C_ADR_VCC   0x4F

CLOCKGEN4_INCR_DISABLE

#define CLOCKGEN4_INCR_DISABLE   0x00

CLOCKGEN4_INCR_ENABLE

#define CLOCKGEN4_INCR_ENABLE   0x80

Clock Gen 4 description setting.

Specified setting for description of Clock Gen 4 Click driver.

Clock Gen 4 Increment Bit.

Increment Bit of Clock Gen 4 Click driver.

CLOCKGEN4_PLL_LOCKED

#define CLOCKGEN4_PLL_LOCKED   0x80

CLOCKGEN4_PLL_STAT_IND

#define CLOCKGEN4_PLL_STAT_IND   0x06

CLOCKGEN4_PLL_UNLOCKED

#define CLOCKGEN4_PLL_UNLOCKED   0x00

Clock Gen 4 device control.

Device control of Clock Gen 4 Click driver.

CLOCKGEN4_R_MOD_SEL_L_0

#define CLOCKGEN4_R_MOD_SEL_L_0   0x00

Clock Gen 4 device configuration 1.

Device configuration 1 of Clock Gen 4 Click driver.

CLOCKGEN4_R_MOD_SEL_L_1

#define CLOCKGEN4_R_MOD_SEL_L_1   0x20

CLOCKGEN4_R_MOD_SEL_L_2

#define CLOCKGEN4_R_MOD_SEL_L_2   0x40

CLOCKGEN4_R_MOD_SEL_L_3

#define CLOCKGEN4_R_MOD_SEL_L_3   0x60

CLOCKGEN4_R_MOD_SEL_R_1

#define CLOCKGEN4_R_MOD_SEL_R_1   0x80

CLOCKGEN4_R_MOD_SEL_R_2

#define CLOCKGEN4_R_MOD_SEL_R_2   0xA0

CLOCKGEN4_R_MOD_SEL_R_3

#define CLOCKGEN4_R_MOD_SEL_R_3   0xC0

CLOCKGEN4_R_MOD_SEL_R_4

#define CLOCKGEN4_R_MOD_SEL_R_4   0xE0

CLOCKGEN4_REF_CLK_25_MHZ

#define CLOCKGEN4_REF_CLK_25_MHZ   25.0

Clock Gen 4 input clock.

Input clock of Clock Gen 4 Click driver.

CLOCKGEN4_REF_CLK_DIV_1

#define CLOCKGEN4_REF_CLK_DIV_1   0x10

CLOCKGEN4_REF_CLK_DIV_2

#define CLOCKGEN4_REF_CLK_DIV_2   0x08

CLOCKGEN4_REF_CLK_DIV_4

#define CLOCKGEN4_REF_CLK_DIV_4   0x00

CLOCKGEN4_REG_CLK

#define CLOCKGEN4_REG_CLK   0x00

CLOCKGEN4_SET_DATA_SAMPLE_EDGE

#define CLOCKGEN4_SET_DATA_SAMPLE_EDGE   SET_SPI_DATA_SAMPLE_EDGE

Data sample selection.

This macro sets data samples for SPI modules.

Note

Available only on Microchip PIC family devices. This macro will set data sampling for all SPI modules on MCU. Can be overwritten with clockgen4_init which will set SET_SPI_DATA_SAMPLE_MIDDLE by default on the mapped mikrobus.

CLOCKGEN4_SET_DATA_SAMPLE_MIDDLE

#define CLOCKGEN4_SET_DATA_SAMPLE_MIDDLE   SET_SPI_DATA_SAMPLE_MIDDLE

CLOCKGEN4_SPI_CHIP_ADR

#define CLOCKGEN4_SPI_CHIP_ADR   0x9E