Clock Gen 5 Registers Settings

Settings for registers of Clock Gen 5 Click driver. More...

Macros
#define	CLOCKGEN5_OCT_0   0
	Clock Gen 5 description setting.
#define	CLOCKGEN5_OCT_1   1
#define	CLOCKGEN5_OCT_2   2
#define	CLOCKGEN5_OCT_3   3
#define	CLOCKGEN5_OCT_4   4
#define	CLOCKGEN5_OCT_5   5
#define	CLOCKGEN5_OCT_6   6
#define	CLOCKGEN5_OCT_7   7
#define	CLOCKGEN5_OCT_8   8
#define	CLOCKGEN5_OCT_9   9
#define	CLOCKGEN5_OCT_10   10
#define	CLOCKGEN5_OCT_11   11
#define	CLOCKGEN5_OCT_12   12
#define	CLOCKGEN5_OCT_13   13
#define	CLOCKGEN5_OCT_14   14
#define	CLOCKGEN5_OCT_15   15
#define	CLOCKGEN5_OUTPUT_DISABLE   0x00
	Clock Gen 5 output enable or fisable.
#define	CLOCKGEN5_OUTPUT_ENABLE   0x01
#define	CLOCKGEN5_CFG_ON_CLK_180   0x00
	Clock Gen 5 config settings.
#define	CLOCKGEN5_CFG_OFF_ON   0x01
#define	CLOCKGEN5_CFG_ON_OFF   0x02
#define	CLOCKGEN5_CFG_POWER_DOWN   0x03
#define	CLOCKGEN5_SET_DATA_SAMPLE_EDGE   SET_SPI_DATA_SAMPLE_EDGE
	Data sample selection.
#define	CLOCKGEN5_SET_DATA_SAMPLE_MIDDLE   SET_SPI_DATA_SAMPLE_MIDDLE

Detailed Description

Settings for registers of Clock Gen 5 Click driver.

Macro Definition Documentation

CLOCKGEN5_CFG_OFF_ON

#define CLOCKGEN5_CFG_OFF_ON   0x01

CLOCKGEN5_CFG_ON_CLK_180

#define CLOCKGEN5_CFG_ON_CLK_180   0x00

Clock Gen 5 config settings.

Specified setting for configuring Clock Gen 5 Click driver.

CLOCKGEN5_CFG_ON_OFF

#define CLOCKGEN5_CFG_ON_OFF   0x02

CLOCKGEN5_CFG_POWER_DOWN

#define CLOCKGEN5_CFG_POWER_DOWN   0x03

CLOCKGEN5_OCT_0

#define CLOCKGEN5_OCT_0   0

Clock Gen 5 description setting.

Specified setting for description of Clock Gen 5 Click driver.

CLOCKGEN5_OCT_1

#define CLOCKGEN5_OCT_1   1

CLOCKGEN5_OCT_10

#define CLOCKGEN5_OCT_10   10

CLOCKGEN5_OCT_11

#define CLOCKGEN5_OCT_11   11

CLOCKGEN5_OCT_12

#define CLOCKGEN5_OCT_12   12

CLOCKGEN5_OCT_13

#define CLOCKGEN5_OCT_13   13

CLOCKGEN5_OCT_14

#define CLOCKGEN5_OCT_14   14

CLOCKGEN5_OCT_15

#define CLOCKGEN5_OCT_15   15

CLOCKGEN5_OCT_2

#define CLOCKGEN5_OCT_2   2

CLOCKGEN5_OCT_3

#define CLOCKGEN5_OCT_3   3

CLOCKGEN5_OCT_4

#define CLOCKGEN5_OCT_4   4

CLOCKGEN5_OCT_5

#define CLOCKGEN5_OCT_5   5

CLOCKGEN5_OCT_6

#define CLOCKGEN5_OCT_6   6

CLOCKGEN5_OCT_7

#define CLOCKGEN5_OCT_7   7

CLOCKGEN5_OCT_8

#define CLOCKGEN5_OCT_8   8

CLOCKGEN5_OCT_9

#define CLOCKGEN5_OCT_9   9

CLOCKGEN5_OUTPUT_DISABLE

#define CLOCKGEN5_OUTPUT_DISABLE   0x00

Clock Gen 5 output enable or fisable.

Specified setting for enabling or disabling output of Clock Gen 5 Click driver.

CLOCKGEN5_OUTPUT_ENABLE

#define CLOCKGEN5_OUTPUT_ENABLE   0x01

CLOCKGEN5_SET_DATA_SAMPLE_EDGE

#define CLOCKGEN5_SET_DATA_SAMPLE_EDGE   SET_SPI_DATA_SAMPLE_EDGE

Data sample selection.

This macro sets data samples for SPI modules.

Note

Available only on Microchip PIC family devices. This macro will set data sampling for all SPI modules on MCU. Can be overwritten with clockgen5_init which will set SET_SPI_DATA_SAMPLE_MIDDLE by default on the mapped mikrobus.

CLOCKGEN5_SET_DATA_SAMPLE_MIDDLE

#define CLOCKGEN5_SET_DATA_SAMPLE_MIDDLE   SET_SPI_DATA_SAMPLE_MIDDLE