daq 2.0.0.0
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Settings for registers of DAQ Click driver. More...
Macros | |
#define | DAQ_INTERFACE_CRC_EN_MSK (0x1 << 6) |
DAQ inteface format settings. | |
#define | DAQ_INTERFACE_CRC_EN(x) (((x) & 0x1) << 6) |
#define | DAQ_INTERFACE_CRC_TYPE_MSK (0x1 << 5) |
#define | DAQ_INTERFACE_CRC_TYPE(x) (((x) & 0x1) << 5) |
#define | DAQ_INTERFACE_STATUS_EN_MSK (0x1 << 4) |
#define | DAQ_INTERFACE_STATUS_EN(x) (((x) & 0x1) << 4) |
#define | DAQ_INTERFACE_CONVLEN_MSK (0x1 << 3) |
#define | DAQ_INTERFACE_CONVLEN(x) (((x) & 0x1) << 3) |
#define | DAQ_INTERFACE_RDY_EN_MSK (0x1 << 2) |
#define | DAQ_INTERFACE_RDY_EN(x) (((x) & 0x1) << 3) |
#define | DAQ_INTERFACE_CONT_READ_MSK (0x1 << 0) |
#define | DAQ_INTERFACE_CONT_READ_EN(x) (((x) & 0x1) << 0) |
#define | DAQ_POWER_CLK_PWRMODE_MSK 0x3 |
DAQ power clock settings. | |
#define | DAQ_POWER_CLK_PWRMODE(x) (((x) & 0x3) << 0) |
#define | DAQ_POWER_CLK_MOD_OUT_MSK (0x1 << 2) |
#define | DAQ_POWER_CLK_MOD_OUT(x) (((x) & 0x1) << 2) |
#define | DAQ_POWER_CLK_POWER_DOWN 0x08 |
#define | DAQ_POWER_CLK_MCLK_DIV_MSK (0x3 << 4) |
#define | DAQ_POWER_CLK_MCLK_DIV(x) (((x) & 0x3) << 4) |
#define | DAQ_POWER_CLK_CLOCK_SEL_MSK (0x3 << 6) |
#define | DAQ_POWER_CLK_CLOCK_SEL(x) (((x) & 0x3) << 6) |
#define | DAQ_CONVERSION_DIAG_MUX_MSK (0xF << 4) |
DAQ conversion settings. | |
#define | DAQ_CONVERSION_DIAG_MUX_SEL(x) (((x) & 0xF) << 4) |
#define | DAQ_CONVERSION_DIAG_SEL_MSK (0x1 << 3) |
#define | DAQ_CONVERSION_DIAG_SEL(x) (((x) & 0x1) << 3) |
#define | DAQ_CONVERSION_MODE_MSK (0x7 << 0) |
#define | DAQ_CONVERSION_MODE(x) (((x) & 0x7) << 0) |
#define | DAQ_ANALOG_REF_BUF_POS_MSK (0x3 << 6) |
DAQ analog settings. | |
#define | DAQ_ANALOG_REF_BUF_POS(x) (((x) & 0x3) << 6) |
#define | DAQ_ANALOG_REF_BUF_NEG_MSK (0x3 << 4) |
#define | DAQ_ANALOG_REF_BUF_NEG(x) (((x) & 0x3) << 4) |
#define | DAQ_ANALOG_AIN_BUF_POS_OFF_MSK (0x1 << 1) |
#define | DAQ_ANALOG_AIN_BUF_POS_OFF(x) (((x) & 0x1) << 1) |
#define | DAQ_ANALOG_AIN_BUF_NEG_OFF_MSK (0x1 << 0) |
#define | DAQ_ANALOG_AIN_BUF_NEG_OFF(x) (((x) & 0x1) << 0) |
#define | DAQ_ANALOG2_VCM_MSK (0x7 << 0) |
#define | DAQ_ANALOG2_VCM(x) (((x) & 0x7) << 0) |
#define | DAQ_DIGI_FILTER_60HZ_REJ_EN_MSK (0x1 << 7) |
DAQ digital filter settings. | |
#define | DAQ_DIGI_FILTER_60HZ_REJ_EN(x) (((x) & 0x1) << 7) |
#define | DAQ_DIGI_FILTER_FILTER_MSK (0x7 << 4) |
#define | DAQ_DIGI_FILTER_FILTER(x) (((x) & 0x7) << 4) |
#define | DAQ_DIGI_FILTER_DEC_RATE_MSK (0x7 << 0) |
#define | DAQ_DIGI_FILTER_DEC_RATE(x) (((x) & 0x7) << 0) |
#define | DAQ_SINC3_DEC_RATE_MSB_MSK (0x0F << 0) |
DAQ sinc3 decimal rate settings. | |
#define | DAQ_SINC3_DEC_RATE_MSB(x) (((x) & 0x0F) << 0) |
#define | DAQ_SINC3_DEC_RATE_LSB_MSK (0xFF << 0) |
#define | DAQ_SINC3_DEC_RATE_LSB(x) (((x) & 0xFF) << 0) |
#define | DAQ_DC_RATIO_IDLE_TIME_MSK (0xFF << 0) |
DAQ duty cycle ratio settings. | |
#define | DAQ_DC_RATIO_IDLE_TIME(x) (((x) & 0xFF) << 0) |
#define | DAQ_SYNC_RST_SPI_STARTB_MSK (0x1 << 7) |
DAQ sync reset settings. | |
#define | DAQ_SYNC_RST_SPI_STARTB(x) (((x) & 0x1) << 7) |
#define | DAQ_SYNC_RST_SYNCOUT_EDGE_MSK (0x1 << 6) |
#define | DAQ_SYNC_RST_SYNCOUT_EDGE(x) (((x) & 0x1) << 6) |
#define | DAQ_SYNC_RST_GPIO_START_EN_MSK (0x1 << 3) |
#define | DAQ_SYNC_RST_GPIO_START_EN(x) (((x) & 0x1) << 3) |
#define | DAQ_SYNC_RST_SPI_RESET_MSK (0x3 << 0) |
#define | DAQ_SYNC_RST_SPI_RESET(x) (((x) & 0x3) << 0) |
#define | DAQ_GPIO_CNTRL_UGPIO_EN_MSK (0x1 << 7) |
DAQ gpio control settings. | |
#define | DAQ_GPIO_CNTRL_UGPIO_EN(x) (((x) & 0x1) << 7) |
#define | DAQ_GPIO_CNTRL_GPIO2_OD_EN_MSK (0x1 << 6) |
#define | DAQ_GPIO_CNTRL_GPIO2_OD_EN(x) (((x) & 0x1) << 6) |
#define | DAQ_GPIO_CNTRL_GPIO1_OD_EN_MSK (0x1 << 5) |
#define | DAQ_GPIO_CNTRL_GPIO1_OD_EN(x) (((x) & 0x1) << 5) |
#define | DAQ_GPIO_CNTRL_GPIO0_OD_EN_MSK (0x1 << 4) |
#define | DAQ_GPIO_CNTRL_GPIO0_OD_EN(x) (((x) & 0x1) << 4) |
#define | DAQ_GPIO_CNTRL_ALL_GPIOS_OD_EN_MSK (0x7 << 4) |
#define | DAQ_GPIO_CNTRL_ALL_GPIOS_OD_EN(x) (((x) & 0x7) << 4) |
#define | DAQ_GPIO_CNTRL_GPIO3_OP_EN_MSK (0x1 << 3) |
#define | DAQ_GPIO_CNTRL_GPIO3_OP_EN(x) (((x) & 0x1) << 3) |
#define | DAQ_GPIO_CNTRL_GPIO2_OP_EN_MSK (0x1 << 2) |
#define | DAQ_GPIO_CNTRL_GPIO2_OP_EN(x) (((x) & 0x1) << 2) |
#define | DAQ_GPIO_CNTRL_GPIO1_OP_EN_MSK (0x1 << 1) |
#define | DAQ_GPIO_CNTRL_GPIO1_OP_EN(x) (((x) & 0x1) << 1) |
#define | DAQ_GPIO_CNTRL_GPIO0_OP_EN_MSK (0x1 << 0) |
#define | DAQ_GPIO_CNTRL_GPIO0_OP_EN(x) (((x) & 0x1) << 0) |
#define | DAQ_GPIO_CNTRL_ALL_GPIOS_OP_EN_MSK (0xF << 0) |
#define | DAQ_GPIO_CNTRL_ALL_GPIOS_OP_EN(x) (((x) & 0xF) << 0) |
#define | DAQ_GPIO_WRITE_3_MSK (0x1 << 3) |
#define | DAQ_GPIO_WRITE_3(x) (((x) & 0x1) << 3) |
#define | DAQ_GPIO_WRITE_2_MSK (0x1 << 2) |
#define | DAQ_GPIO_WRITE_2(x) (((x) & 0x1) << 2) |
#define | DAQ_GPIO_WRITE_1_MSK (0x1 << 1) |
#define | DAQ_GPIO_WRITE_1(x) (((x) & 0x1) << 1) |
#define | DAQ_GPIO_WRITE_0_MSK (0x1 << 0) |
#define | DAQ_GPIO_WRITE_0(x) (((x) & 0x1) << 0) |
#define | DAQ_GPIO_WRITE_ALL_MSK (0xF << 0) |
#define | DAQ_GPIO_WRITE_ALL(x) (((x) & 0xF)) |
#define | DAQ_GPIO_READ_3_MSK (0x1 << 3) |
#define | DAQ_GPIO_READ_2_MSK (0x1 << 2) |
#define | DAQ_GPIO_READ_1_MSK (0x1 << 1) |
#define | DAQ_GPIO_READ_0_MSK (0x1 << 0) |
#define | DAQ_GPIO_READ_ALL_MSK (0xF << 0) |
#define | DAQ_OFFSET_HI_MSK (0xFF << 0) |
DAQ offset settings. | |
#define | DAQ_OFFSET_HI(x) (((x) & 0xFF) << 0) |
#define | DAQ_OFFSET_MID_MSK (0xFF << 0) |
#define | DAQ_OFFSET_MID(x) (((x) & 0xFF) << 0) |
#define | DAQ_OFFSET_LO_MSK (0xFF << 0) |
#define | DAQ_OFFSET_LO(x) (((x) & 0xFF) << 0) |
#define | DAQ_GAIN_HI_MSK (0xFF << 0) |
DAQ gain settings. | |
#define | DAQ_GAIN_HI(x) (((x) & 0xFF) << 0) |
#define | DAQ_GAIN_MID_MSK (0xFF << 0) |
#define | DAQ_GAIN_MID(x) (((x) & 0xFF) << 0) |
#define | DAQ_GAIN_LOW_MSK (0xFF << 0) |
#define | DAQ_GAIN_LOW(x) (((x) & 0xFF) << 0) |
#define | DAQ_SPI_DIAG_ERR_SPI_IGNORE_MSK (0x1 << 4) |
DAQ spi diagnostic enable settings. | |
#define | DAQ_SPI_DIAG_ERR_SPI_IGNORE(x) (((x) & 0x1) << 4) |
#define | DAQ_SPI_DIAG_ERR_SPI_CLK_CNT_MSK (0x1 << 3) |
#define | DAQ_SPI_DIAG_ERR_SPI_CLK_CNT(x) (((x) & 0x1) << 3) |
#define | DAQ_SPI_DIAG_ERR_SPI_RD_MSK (0x1 << 2) |
#define | DAQ_SPI_DIAG_ERR_SPI_RD(x) (((x) & 0x1) << 2) |
#define | DAQ_SPI_DIAG_ERR_SPI_WR_MSK (0x1 << 1) |
#define | DAQ_SPI_DIAG_ERR_SPI_WR(x) (((x) & 0x1) << 1) |
#define | DAQ_ADC_DIAG_ERR_DLDO_PSM_MSK (0x1 << 5) |
DAQ adc diagnostic enable settings. | |
#define | DAQ_ADC_DIAG_ERR_DLDO_PSM(x) (((x) & 0x1) << 5) |
#define | DAQ_ADC_DIAG_ERR_ALDO_PSM_MSK (0x1 << 4) |
#define | DAQ_ADC_DIAG_ERR_ALDO_PSM(x) (((x) & 0x1) << 4) |
#define | DAQ_ADC_DIAG_ERR_FILT_SAT_MSK (0x1 << 2) |
#define | DAQ_ADC_DIAG_ERR_FILT_SAT(x) (((x) & 0x1) << 2) |
#define | DAQ_ADC_DIAG_ERR_FILT_NOT_SET_MSK (0x1 << 1) |
#define | DAQ_ADC_DIAG_ERR_FILT_NOT_SET(x) (((x) & 0x1) << 1) |
#define | DAQ_ADC_DIAG_ERR_EXT_CLK_QUAL_MSK (0x1 << 0) |
#define | DAQ_ADC_DIAG_ERR_EXT_CLK_QUAL(x) (((x) & 0x1) << 0) |
#define | DAQ_DIG_DIAG_ERR_MEMMAP_CRC_MSK (0x1 << 4) |
DAQ diagnostic enable settings. | |
#define | DAQ_DIG_DIAG_ERR_MEMMAP_CRC(x) (((x) & 0x1) << 4) |
#define | DAQ_DIG_DIAG_ERR_RAM_CRC_MSK (0x1 << 3) |
#define | DAQ_DIG_DIAG_ERR_RAM_CRC(x) (((x) & 0x1) << 3) |
#define | DAQ_DIG_DIAG_ERR_FUSE_CRC_MSK (0x1 << 2) |
#define | DAQ_DIG_DIAG_ERR_FUSE_CRC(x) (((x) & 0x1) << 2) |
#define | DAQ_DIG_DIAG_FREQ_COUNT_EN_MSK (0x1 << 0) |
#define | DAQ_DIG_DIAG_FREQ_COUNT_EN(x) (((x) & 0x1) << 0) |
#define | DAQ_MASTER_ERROR_MSK (0x1 << 7) |
DAQ master status. | |
#define | DAQ_MASTER_ADC_ERROR_MSK (0x1 << 6) |
#define | DAQ_MASTER_DIG_ERROR_MSK (0x1 << 5) |
#define | DAQ_MASTER_DIG_ERR_EXT_CLK_MSK (0x1 << 4) |
#define | DAQ_MASTER_FILT_SAT_MSK (0x1 << 3) |
#define | DAQ_MASTER_FILT_NOT_SET_MSK (0x1 << 2) |
#define | DAQ_MASTER_SPI_ERROR_MSK (0x1 << 1) |
#define | DAQ_MASTER_POR_FLAG_MSK (0x1 << 0) |
#define | DAQ_SPI_IGNORE_ERROR_MSK (0x1 << 4) |
DAQ spi status. | |
#define | DAQ_SPI_IGNORE_ERROR_CLR(x) (((x) & 0x1) << 4) |
#define | DAQ_SPI_CLK_CNT_ERROR_MSK (0x1 << 3) |
#define | DAQ_SPI_READ_ERROR_MSK (0x1 << 2) |
#define | DAQ_SPI_READ_ERROR_CLR(x) (((x) & 0x1) << 2) |
#define | DAQ_SPI_WRITE_ERROR_MSK (0x1 << 1) |
#define | DAQ_SPI_WRITE_ERROR_CLR(x) (((x) & 0x1) << 1) |
#define | DAQ_SPI_CRC_ERROR_MSK (0x1 << 0) |
#define | DAQ_SPI_CRC_ERROR_CLR(x) (((x) & 0x1) << 0) |
#define | DAQ_ADC_DLDO_PSM_ERROR_MSK (0x1 << 5) |
DAQ adc status. | |
#define | DAQ_ADC_ALDO_PSM_ERROR_MSK (0x1 << 4) |
#define | DAQ_ADC_REF_DET_ERROR_MSK (0x1 << 3) |
#define | DAQ_ADC_FILT_SAT_MSK (0x1 << 2) |
#define | DAQ_ADC_FILT_NOT_SET_MSK (0x1 << 1) |
#define | DAQ_ADC_DIG_ERR_EXT_CLK_MSK (0x1 << 0) |
#define | DAQ_DIG_MEMMAP_CRC_ERROR_MSK (0x1 << 4) |
DAQ diagnostic status. | |
#define | DAQ_DIG_RAM_CRC_ERROR_MSK (0x1 << 3) |
#define | DAQ_DIG_FUS_CRC_ERROR_MSK (0x1 << 2) |
#define | DAQ_MCLK_COUNTER_MSK (0xFF << 0) |
DAQ mclk counter settings. | |
#define | DAQ_MCLK_COUNTER(x) (((x) & 0xFF) << 0) |
#define | DAQ_COEF_CONTROL_COEFFACCESSEN_MSK (0x1 << 7) |
DAQ coefficient control settings. | |
#define | DAQ_COEF_CONTROL_COEFFACCESSEN(x) (((x) & 0x1) << 7) |
#define | DAQ_COEF_CONTROL_COEFFWRITEEN_MSK (0x1 << 6) |
#define | DAQ_COEF_CONTROL_COEFFWRITEEN(x) (((x) & 0x1) << 6) |
#define | DAQ_COEF_CONTROL_COEFFADDR_MSK (0x3F << 5) |
#define | DAQ_COEF_CONTROL_COEFFADDR(x) (((x) & 0x3F) << 5) |
#define | DAQ_COEFF_DATA_USERCOEFFEN_MSK (0x1 << 23) |
DAQ coefficient data settings. | |
#define | DAQ_COEFF_DATA_USERCOEFFEN(x) (((x) & 0x1) << 23) |
#define | DAQ_COEFF_DATA_COEFFDATA_MSK (0x7FFFFF << 22) |
#define | DAQ_COEFF_DATA_COEFFDATA(x) (((x) & 0x7FFFFF) << 22) |
#define | DAQ_ACCESS_KEY_MSK (0xFF << 0) |
DAQ access settings. | |
#define | DAQ_ACCESS_KEY(x) (((x) & 0xFF) << 0) |
#define | DAQ_ACCESS_KEY_CHECK_MSK (0x1 << 0) |
#define | DAQ_RESOLUTION 8388608 |
DAQ resolution settings. | |
Settings for registers of DAQ Click driver.
#define DAQ_ACCESS_KEY | ( | x | ) | (((x) & 0xFF) << 0) |
#define DAQ_ACCESS_KEY_CHECK_MSK (0x1 << 0) |
#define DAQ_ACCESS_KEY_MSK (0xFF << 0) |
DAQ access settings.
Specified settings for access of DAQ Click driver.
#define DAQ_ADC_ALDO_PSM_ERROR_MSK (0x1 << 4) |
#define DAQ_ADC_DIAG_ERR_ALDO_PSM | ( | x | ) | (((x) & 0x1) << 4) |
#define DAQ_ADC_DIAG_ERR_ALDO_PSM_MSK (0x1 << 4) |
#define DAQ_ADC_DIAG_ERR_DLDO_PSM | ( | x | ) | (((x) & 0x1) << 5) |
#define DAQ_ADC_DIAG_ERR_DLDO_PSM_MSK (0x1 << 5) |
DAQ adc diagnostic enable settings.
Specified settings for adc diagnostic enable of DAQ Click driver.
#define DAQ_ADC_DIAG_ERR_EXT_CLK_QUAL | ( | x | ) | (((x) & 0x1) << 0) |
#define DAQ_ADC_DIAG_ERR_EXT_CLK_QUAL_MSK (0x1 << 0) |
#define DAQ_ADC_DIAG_ERR_FILT_NOT_SET | ( | x | ) | (((x) & 0x1) << 1) |
#define DAQ_ADC_DIAG_ERR_FILT_NOT_SET_MSK (0x1 << 1) |
#define DAQ_ADC_DIAG_ERR_FILT_SAT | ( | x | ) | (((x) & 0x1) << 2) |
#define DAQ_ADC_DIAG_ERR_FILT_SAT_MSK (0x1 << 2) |
#define DAQ_ADC_DIG_ERR_EXT_CLK_MSK (0x1 << 0) |
#define DAQ_ADC_DLDO_PSM_ERROR_MSK (0x1 << 5) |
DAQ adc status.
Specified adc status of DAQ Click driver.
#define DAQ_ADC_FILT_NOT_SET_MSK (0x1 << 1) |
#define DAQ_ADC_FILT_SAT_MSK (0x1 << 2) |
#define DAQ_ADC_REF_DET_ERROR_MSK (0x1 << 3) |
#define DAQ_ANALOG2_VCM | ( | x | ) | (((x) & 0x7) << 0) |
#define DAQ_ANALOG2_VCM_MSK (0x7 << 0) |
#define DAQ_ANALOG_AIN_BUF_NEG_OFF | ( | x | ) | (((x) & 0x1) << 0) |
#define DAQ_ANALOG_AIN_BUF_NEG_OFF_MSK (0x1 << 0) |
#define DAQ_ANALOG_AIN_BUF_POS_OFF | ( | x | ) | (((x) & 0x1) << 1) |
#define DAQ_ANALOG_AIN_BUF_POS_OFF_MSK (0x1 << 1) |
#define DAQ_ANALOG_REF_BUF_NEG | ( | x | ) | (((x) & 0x3) << 4) |
#define DAQ_ANALOG_REF_BUF_NEG_MSK (0x3 << 4) |
#define DAQ_ANALOG_REF_BUF_POS | ( | x | ) | (((x) & 0x3) << 6) |
#define DAQ_ANALOG_REF_BUF_POS_MSK (0x3 << 6) |
DAQ analog settings.
Specified settings for analog of DAQ Click driver.
#define DAQ_COEF_CONTROL_COEFFACCESSEN | ( | x | ) | (((x) & 0x1) << 7) |
#define DAQ_COEF_CONTROL_COEFFACCESSEN_MSK (0x1 << 7) |
DAQ coefficient control settings.
Specified settings for coefficient control of DAQ Click driver.
#define DAQ_COEF_CONTROL_COEFFADDR | ( | x | ) | (((x) & 0x3F) << 5) |
#define DAQ_COEF_CONTROL_COEFFADDR_MSK (0x3F << 5) |
#define DAQ_COEF_CONTROL_COEFFWRITEEN | ( | x | ) | (((x) & 0x1) << 6) |
#define DAQ_COEF_CONTROL_COEFFWRITEEN_MSK (0x1 << 6) |
#define DAQ_COEFF_DATA_COEFFDATA | ( | x | ) | (((x) & 0x7FFFFF) << 22) |
#define DAQ_COEFF_DATA_COEFFDATA_MSK (0x7FFFFF << 22) |
#define DAQ_COEFF_DATA_USERCOEFFEN | ( | x | ) | (((x) & 0x1) << 23) |
#define DAQ_COEFF_DATA_USERCOEFFEN_MSK (0x1 << 23) |
DAQ coefficient data settings.
Specified settings for coefficient data of DAQ Click driver.
#define DAQ_CONVERSION_DIAG_MUX_MSK (0xF << 4) |
DAQ conversion settings.
Specified settings for conversion of DAQ Click driver.
#define DAQ_CONVERSION_DIAG_MUX_SEL | ( | x | ) | (((x) & 0xF) << 4) |
#define DAQ_CONVERSION_DIAG_SEL | ( | x | ) | (((x) & 0x1) << 3) |
#define DAQ_CONVERSION_DIAG_SEL_MSK (0x1 << 3) |
#define DAQ_CONVERSION_MODE | ( | x | ) | (((x) & 0x7) << 0) |
#define DAQ_CONVERSION_MODE_MSK (0x7 << 0) |
#define DAQ_DC_RATIO_IDLE_TIME | ( | x | ) | (((x) & 0xFF) << 0) |
#define DAQ_DC_RATIO_IDLE_TIME_MSK (0xFF << 0) |
DAQ duty cycle ratio settings.
Specified settings for duty cycle ratio of DAQ Click driver.
#define DAQ_DIG_DIAG_ERR_FUSE_CRC | ( | x | ) | (((x) & 0x1) << 2) |
#define DAQ_DIG_DIAG_ERR_FUSE_CRC_MSK (0x1 << 2) |
#define DAQ_DIG_DIAG_ERR_MEMMAP_CRC | ( | x | ) | (((x) & 0x1) << 4) |
#define DAQ_DIG_DIAG_ERR_MEMMAP_CRC_MSK (0x1 << 4) |
DAQ diagnostic enable settings.
Specified settings for diagnostic enable of DAQ Click driver.
#define DAQ_DIG_DIAG_ERR_RAM_CRC | ( | x | ) | (((x) & 0x1) << 3) |
#define DAQ_DIG_DIAG_ERR_RAM_CRC_MSK (0x1 << 3) |
#define DAQ_DIG_DIAG_FREQ_COUNT_EN | ( | x | ) | (((x) & 0x1) << 0) |
#define DAQ_DIG_DIAG_FREQ_COUNT_EN_MSK (0x1 << 0) |
#define DAQ_DIG_FUS_CRC_ERROR_MSK (0x1 << 2) |
#define DAQ_DIG_MEMMAP_CRC_ERROR_MSK (0x1 << 4) |
DAQ diagnostic status.
Specified diagnostic status of DAQ Click driver.
#define DAQ_DIG_RAM_CRC_ERROR_MSK (0x1 << 3) |
#define DAQ_DIGI_FILTER_60HZ_REJ_EN | ( | x | ) | (((x) & 0x1) << 7) |
#define DAQ_DIGI_FILTER_60HZ_REJ_EN_MSK (0x1 << 7) |
DAQ digital filter settings.
Specified settings for digital filter of DAQ Click driver.
#define DAQ_DIGI_FILTER_DEC_RATE | ( | x | ) | (((x) & 0x7) << 0) |
#define DAQ_DIGI_FILTER_DEC_RATE_MSK (0x7 << 0) |
#define DAQ_DIGI_FILTER_FILTER | ( | x | ) | (((x) & 0x7) << 4) |
#define DAQ_DIGI_FILTER_FILTER_MSK (0x7 << 4) |
#define DAQ_GAIN_HI | ( | x | ) | (((x) & 0xFF) << 0) |
#define DAQ_GAIN_HI_MSK (0xFF << 0) |
DAQ gain settings.
Specified settings for gain of DAQ Click driver.
#define DAQ_GAIN_LOW | ( | x | ) | (((x) & 0xFF) << 0) |
#define DAQ_GAIN_LOW_MSK (0xFF << 0) |
#define DAQ_GAIN_MID | ( | x | ) | (((x) & 0xFF) << 0) |
#define DAQ_GAIN_MID_MSK (0xFF << 0) |
#define DAQ_GPIO_CNTRL_ALL_GPIOS_OD_EN | ( | x | ) | (((x) & 0x7) << 4) |
#define DAQ_GPIO_CNTRL_ALL_GPIOS_OD_EN_MSK (0x7 << 4) |
#define DAQ_GPIO_CNTRL_ALL_GPIOS_OP_EN | ( | x | ) | (((x) & 0xF) << 0) |
#define DAQ_GPIO_CNTRL_ALL_GPIOS_OP_EN_MSK (0xF << 0) |
#define DAQ_GPIO_CNTRL_GPIO0_OD_EN | ( | x | ) | (((x) & 0x1) << 4) |
#define DAQ_GPIO_CNTRL_GPIO0_OD_EN_MSK (0x1 << 4) |
#define DAQ_GPIO_CNTRL_GPIO0_OP_EN | ( | x | ) | (((x) & 0x1) << 0) |
#define DAQ_GPIO_CNTRL_GPIO0_OP_EN_MSK (0x1 << 0) |
#define DAQ_GPIO_CNTRL_GPIO1_OD_EN | ( | x | ) | (((x) & 0x1) << 5) |
#define DAQ_GPIO_CNTRL_GPIO1_OD_EN_MSK (0x1 << 5) |
#define DAQ_GPIO_CNTRL_GPIO1_OP_EN | ( | x | ) | (((x) & 0x1) << 1) |
#define DAQ_GPIO_CNTRL_GPIO1_OP_EN_MSK (0x1 << 1) |
#define DAQ_GPIO_CNTRL_GPIO2_OD_EN | ( | x | ) | (((x) & 0x1) << 6) |
#define DAQ_GPIO_CNTRL_GPIO2_OD_EN_MSK (0x1 << 6) |
#define DAQ_GPIO_CNTRL_GPIO2_OP_EN | ( | x | ) | (((x) & 0x1) << 2) |
#define DAQ_GPIO_CNTRL_GPIO2_OP_EN_MSK (0x1 << 2) |
#define DAQ_GPIO_CNTRL_GPIO3_OP_EN | ( | x | ) | (((x) & 0x1) << 3) |
#define DAQ_GPIO_CNTRL_GPIO3_OP_EN_MSK (0x1 << 3) |
#define DAQ_GPIO_CNTRL_UGPIO_EN | ( | x | ) | (((x) & 0x1) << 7) |
#define DAQ_GPIO_CNTRL_UGPIO_EN_MSK (0x1 << 7) |
DAQ gpio control settings.
Specified settings for gpio control of DAQ Click driver.
#define DAQ_GPIO_READ_0_MSK (0x1 << 0) |
#define DAQ_GPIO_READ_1_MSK (0x1 << 1) |
#define DAQ_GPIO_READ_2_MSK (0x1 << 2) |
#define DAQ_GPIO_READ_3_MSK (0x1 << 3) |
#define DAQ_GPIO_READ_ALL_MSK (0xF << 0) |
#define DAQ_GPIO_WRITE_0 | ( | x | ) | (((x) & 0x1) << 0) |
#define DAQ_GPIO_WRITE_0_MSK (0x1 << 0) |
#define DAQ_GPIO_WRITE_1 | ( | x | ) | (((x) & 0x1) << 1) |
#define DAQ_GPIO_WRITE_1_MSK (0x1 << 1) |
#define DAQ_GPIO_WRITE_2 | ( | x | ) | (((x) & 0x1) << 2) |
#define DAQ_GPIO_WRITE_2_MSK (0x1 << 2) |
#define DAQ_GPIO_WRITE_3 | ( | x | ) | (((x) & 0x1) << 3) |
#define DAQ_GPIO_WRITE_3_MSK (0x1 << 3) |
#define DAQ_GPIO_WRITE_ALL | ( | x | ) | (((x) & 0xF)) |
#define DAQ_GPIO_WRITE_ALL_MSK (0xF << 0) |
#define DAQ_INTERFACE_CONT_READ_EN | ( | x | ) | (((x) & 0x1) << 0) |
#define DAQ_INTERFACE_CONT_READ_MSK (0x1 << 0) |
#define DAQ_INTERFACE_CONVLEN | ( | x | ) | (((x) & 0x1) << 3) |
#define DAQ_INTERFACE_CONVLEN_MSK (0x1 << 3) |
#define DAQ_INTERFACE_CRC_EN | ( | x | ) | (((x) & 0x1) << 6) |
#define DAQ_INTERFACE_CRC_EN_MSK (0x1 << 6) |
DAQ inteface format settings.
Specified settings for inteface format of DAQ Click driver.
#define DAQ_INTERFACE_CRC_TYPE | ( | x | ) | (((x) & 0x1) << 5) |
#define DAQ_INTERFACE_CRC_TYPE_MSK (0x1 << 5) |
#define DAQ_INTERFACE_RDY_EN | ( | x | ) | (((x) & 0x1) << 3) |
#define DAQ_INTERFACE_RDY_EN_MSK (0x1 << 2) |
#define DAQ_INTERFACE_STATUS_EN | ( | x | ) | (((x) & 0x1) << 4) |
#define DAQ_INTERFACE_STATUS_EN_MSK (0x1 << 4) |
#define DAQ_MASTER_ADC_ERROR_MSK (0x1 << 6) |
#define DAQ_MASTER_DIG_ERR_EXT_CLK_MSK (0x1 << 4) |
#define DAQ_MASTER_DIG_ERROR_MSK (0x1 << 5) |
#define DAQ_MASTER_ERROR_MSK (0x1 << 7) |
DAQ master status.
Specified master status of DAQ Click driver.
#define DAQ_MASTER_FILT_NOT_SET_MSK (0x1 << 2) |
#define DAQ_MASTER_FILT_SAT_MSK (0x1 << 3) |
#define DAQ_MASTER_POR_FLAG_MSK (0x1 << 0) |
#define DAQ_MASTER_SPI_ERROR_MSK (0x1 << 1) |
#define DAQ_MCLK_COUNTER | ( | x | ) | (((x) & 0xFF) << 0) |
#define DAQ_MCLK_COUNTER_MSK (0xFF << 0) |
DAQ mclk counter settings.
Specified settings for mclk counter of DAQ Click driver.
#define DAQ_OFFSET_HI | ( | x | ) | (((x) & 0xFF) << 0) |
#define DAQ_OFFSET_HI_MSK (0xFF << 0) |
DAQ offset settings.
Specified settings for offset of DAQ Click driver.
#define DAQ_OFFSET_LO | ( | x | ) | (((x) & 0xFF) << 0) |
#define DAQ_OFFSET_LO_MSK (0xFF << 0) |
#define DAQ_OFFSET_MID | ( | x | ) | (((x) & 0xFF) << 0) |
#define DAQ_OFFSET_MID_MSK (0xFF << 0) |
#define DAQ_POWER_CLK_CLOCK_SEL | ( | x | ) | (((x) & 0x3) << 6) |
#define DAQ_POWER_CLK_CLOCK_SEL_MSK (0x3 << 6) |
#define DAQ_POWER_CLK_MCLK_DIV | ( | x | ) | (((x) & 0x3) << 4) |
#define DAQ_POWER_CLK_MCLK_DIV_MSK (0x3 << 4) |
#define DAQ_POWER_CLK_MOD_OUT | ( | x | ) | (((x) & 0x1) << 2) |
#define DAQ_POWER_CLK_MOD_OUT_MSK (0x1 << 2) |
#define DAQ_POWER_CLK_POWER_DOWN 0x08 |
#define DAQ_POWER_CLK_PWRMODE | ( | x | ) | (((x) & 0x3) << 0) |
#define DAQ_POWER_CLK_PWRMODE_MSK 0x3 |
DAQ power clock settings.
Specified settings for power clock of DAQ Click driver.
#define DAQ_RESOLUTION 8388608 |
DAQ resolution settings.
Specified settings for resolution of DAQ Click driver.
#define DAQ_SINC3_DEC_RATE_LSB | ( | x | ) | (((x) & 0xFF) << 0) |
#define DAQ_SINC3_DEC_RATE_LSB_MSK (0xFF << 0) |
#define DAQ_SINC3_DEC_RATE_MSB | ( | x | ) | (((x) & 0x0F) << 0) |
#define DAQ_SINC3_DEC_RATE_MSB_MSK (0x0F << 0) |
DAQ sinc3 decimal rate settings.
Specified settings for digital filter of DAQ Click driver.
#define DAQ_SPI_CLK_CNT_ERROR_MSK (0x1 << 3) |
#define DAQ_SPI_CRC_ERROR_CLR | ( | x | ) | (((x) & 0x1) << 0) |
#define DAQ_SPI_CRC_ERROR_MSK (0x1 << 0) |
#define DAQ_SPI_DIAG_ERR_SPI_CLK_CNT | ( | x | ) | (((x) & 0x1) << 3) |
#define DAQ_SPI_DIAG_ERR_SPI_CLK_CNT_MSK (0x1 << 3) |
#define DAQ_SPI_DIAG_ERR_SPI_IGNORE | ( | x | ) | (((x) & 0x1) << 4) |
#define DAQ_SPI_DIAG_ERR_SPI_IGNORE_MSK (0x1 << 4) |
DAQ spi diagnostic enable settings.
Specified settings for spi diagnostic enable of DAQ Click driver.
#define DAQ_SPI_DIAG_ERR_SPI_RD | ( | x | ) | (((x) & 0x1) << 2) |
#define DAQ_SPI_DIAG_ERR_SPI_RD_MSK (0x1 << 2) |
#define DAQ_SPI_DIAG_ERR_SPI_WR | ( | x | ) | (((x) & 0x1) << 1) |
#define DAQ_SPI_DIAG_ERR_SPI_WR_MSK (0x1 << 1) |
#define DAQ_SPI_IGNORE_ERROR_CLR | ( | x | ) | (((x) & 0x1) << 4) |
#define DAQ_SPI_IGNORE_ERROR_MSK (0x1 << 4) |
DAQ spi status.
Specified spi status of DAQ Click driver.
#define DAQ_SPI_READ_ERROR_CLR | ( | x | ) | (((x) & 0x1) << 2) |
#define DAQ_SPI_READ_ERROR_MSK (0x1 << 2) |
#define DAQ_SPI_WRITE_ERROR_CLR | ( | x | ) | (((x) & 0x1) << 1) |
#define DAQ_SPI_WRITE_ERROR_MSK (0x1 << 1) |
#define DAQ_SYNC_RST_GPIO_START_EN | ( | x | ) | (((x) & 0x1) << 3) |
#define DAQ_SYNC_RST_GPIO_START_EN_MSK (0x1 << 3) |
#define DAQ_SYNC_RST_SPI_RESET | ( | x | ) | (((x) & 0x3) << 0) |
#define DAQ_SYNC_RST_SPI_RESET_MSK (0x3 << 0) |
#define DAQ_SYNC_RST_SPI_STARTB | ( | x | ) | (((x) & 0x1) << 7) |
#define DAQ_SYNC_RST_SPI_STARTB_MSK (0x1 << 7) |
DAQ sync reset settings.
Specified settings for sync reset of DAQ Click driver.
#define DAQ_SYNC_RST_SYNCOUT_EDGE | ( | x | ) | (((x) & 0x1) << 6) |
#define DAQ_SYNC_RST_SYNCOUT_EDGE_MSK (0x1 << 6) |
enum daq_ain_precharge |
enum daq_continuous_read |
enum daq_conv_diag_mux |
enum daq_conv_len |
enum daq_conv_mode |
enum daq_crc_sel |
enum daq_filter_type |
enum daq_gain |
enum daq_gpio_output_type |
enum daq_gpio_write |
enum daq_gpios |
enum daq_mclk_div |
enum daq_power_mode |
enum daq_rdy_dout |
enum daq_ref_buffer |
enum daq_sleep_wake |
enum daq_vcm_out |