Macros
#define	DIGIPOT12_ADDR_BIT_READ_INPUT_REG 0x00
	DIGI POT 12 description mask data bits.

#define	DIGIPOT12_ADDR_BIT_READ_EEPROM 0x01

#define	DIGIPOT12_ADDR_BIT_READ_CTRL_REG 0x02

#define	DIGIPOT12_ADDR_BIT_READ_RDAC 0x03

#define	DIGIPOT12_ADDR_BIT_RDAC_DECR 0x00

#define	DIGIPOT12_ADDR_BIT_RDAC_INCR 0x01

#define	DIGIPOT12_ADDR_BIT_COPY_TO_RDAC 0x00

#define	DIGIPOT12_ADDR_BIT_COPY_TO_EEPROM 0x01

#define	DIGIPOT12_ADDR_BIT_SCALE_MODE_NORMAL 0x80

#define	DIGIPOT12_ADDR_BIT_SCALE_MODE_SHDN 0x81

#define	DIGIPOT12_ADDR_BIT_SCALE_EXIT 0x00

#define	DIGIPOT12_ADDR_BIT_SCALE_ENTER 0x01

#define	DIGIPOT12_ADDR_BIT_SW_SHDN_MODE_NORMAL 0x00

#define	DIGIPOT12_ADDR_BIT_SW_SHDN_MODE_SHDN 0x01

Detailed Description

Macro Definition Documentation

◆ DIGIPOT12_ADDR_BIT_COPY_TO_EEPROM

#define DIGIPOT12_ADDR_BIT_COPY_TO_EEPROM 0x01

◆ DIGIPOT12_ADDR_BIT_COPY_TO_RDAC

#define DIGIPOT12_ADDR_BIT_COPY_TO_RDAC 0x00

◆ DIGIPOT12_ADDR_BIT_RDAC_DECR

#define DIGIPOT12_ADDR_BIT_RDAC_DECR 0x00

◆ DIGIPOT12_ADDR_BIT_RDAC_INCR

#define DIGIPOT12_ADDR_BIT_RDAC_INCR 0x01

◆ DIGIPOT12_ADDR_BIT_READ_CTRL_REG

#define DIGIPOT12_ADDR_BIT_READ_CTRL_REG 0x02

◆ DIGIPOT12_ADDR_BIT_READ_EEPROM

#define DIGIPOT12_ADDR_BIT_READ_EEPROM 0x01

◆ DIGIPOT12_ADDR_BIT_READ_INPUT_REG

#define DIGIPOT12_ADDR_BIT_READ_INPUT_REG 0x00

DIGI POT 12 description mask data bits.

Specified mask data bits for description of DIGI POT 12 Click driver.

◆ DIGIPOT12_ADDR_BIT_READ_RDAC

#define DIGIPOT12_ADDR_BIT_READ_RDAC 0x03

◆ DIGIPOT12_ADDR_BIT_SCALE_ENTER

#define DIGIPOT12_ADDR_BIT_SCALE_ENTER 0x01

◆ DIGIPOT12_ADDR_BIT_SCALE_EXIT

#define DIGIPOT12_ADDR_BIT_SCALE_EXIT 0x00

◆ DIGIPOT12_ADDR_BIT_SCALE_MODE_NORMAL

#define DIGIPOT12_ADDR_BIT_SCALE_MODE_NORMAL 0x80

◆ DIGIPOT12_ADDR_BIT_SCALE_MODE_SHDN

#define DIGIPOT12_ADDR_BIT_SCALE_MODE_SHDN 0x81

◆ DIGIPOT12_ADDR_BIT_SW_SHDN_MODE_NORMAL

#define DIGIPOT12_ADDR_BIT_SW_SHDN_MODE_NORMAL 0x00

◆ DIGIPOT12_ADDR_BIT_SW_SHDN_MODE_SHDN

#define DIGIPOT12_ADDR_BIT_SW_SHDN_MODE_SHDN 0x01

Macros