ecg2.h

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/****************************************************************************
** Copyright (C) 2020 MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and associated documentation files (the "Software"), to deal
** in the Software without restriction, including without limitation the rights
** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
** copies of the Software, and to permit persons to whom the Software is
** furnished to do so, subject to the following conditions:
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
**  USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/
 
#ifndef ECG2_H
#define ECG2_H
 
#ifdef __cplusplus
extern "C"{
#endif
 
#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_spi_master.h"
#include "spi_specifics.h"
#include "drv_analog_in.h"
 
#define ECG2_ID_REG                                                0x00
#define ECG2_CONFIG1_REG                                           0x01
#define ECG2_CONFIG2_REG                                           0x02
#define ECG2_CONFIG3_REG                                           0x03
#define ECG2_LOFF_REG                                              0x04
#define ECG2_CH1SET_REG                                            0x05
#define ECG2_CH2SET_REG                                            0x06
#define ECG2_CH3SET_REG                                            0x07
#define ECG2_CH4SET_REG                                            0x08
#define ECG2_CH5SET_REG                                            0x09
#define ECG2_CH6SET_REG                                            0x0A
#define ECG2_CH7SET_REG                                            0x0B
#define ECG2_CH8SET_REG                                            0x0C
#define ECG2_RLD_SENSP_REG                                         0x0D
#define ECG2_RLD_SENSN_REG                                         0x0E
#define ECG2_LOFF_SENSP_REG                                        0x0F
#define ECG2_LOFF_SENSN_REG                                        0x10
#define ECG2_LOFF_FLIP_REG                                         0x11
#define ECG2_LOFF_STATP_REG                                        0x12
#define ECG2_LOFF_STATN_REG                                        0x13
#define ECG2_GPIO_REG                                              0x14
#define ECG2_PACE_REG                                              0x15
#define ECG2_CONFIG4_REG                                           0x17
#define ECG2_WCT1_REG                                              0x18
#define ECG2_WCT2_REG                                              0x19
 
 // ecg2_reg
 
#define ECG2_WAKEUP_CMD                                             0x02
#define ECG2_STANDBY_CMD                                            0x04
#define ECG2_RESET_CMD                                              0x06
#define ECG2_START_CONVERSION                                       0x08
#define ECG2_STOP_CONVERSION                                        0x0A
#define ECG2_ENABLE_READ_DATA_CONT_MODE                             0x10
#define ECG2_STOP_DATA_CONT_MODE                                    0x11
#define ECG2_READ_DATA_CMD                                          0x12
#define ECG2_SPI_CMD_WRITE                                          0x40
#define ECG2_SPI_CMD_READ                                           0x20
 
#define ECG2_CONFIG1_REG_DEFAULT_VAL                                0x04
#define ECG2_CONFIG2_REG_DEFAULT_VAL                                0x20
#define ECG2_CONFIG3_REG_DEFAULT_VAL                                0x40
 
#define ECG2_CFG_DAISY_ENABLE                                       0x00
#define ECG2_CFG_MULTI_READBACK                                     0x40
 
#define ECG2_CFG_CLK_ENABLE                                         0x20
#define ECG2_CFG_CLK_DISABLE                                        0x00
 
#define ECG2_CFG_DATA_SPEED_8K                                      0x00
#define ECG2_CFG_DATA_SPEED_4K                                      0x01
#define ECG2_CFG_DATA_SPEED_2K                                      0x02
#define ECG2_CFG_DATA_SPEED_1K                                      0x03
#define ECG2_CFG_DATA_SPEED_500                                     0x04
#define ECG2_CFG_DATA_SPEED_250                                     0x05
#define ECG2_CFG_DATA_SPEED_125                                     0x06
#define ECG2_CFG_DATA_SPEED_OFF                                     0x07
 
#define ECG2_CFG_INT_TEST_EXT                                       0x10
#define ECG2_CFG_INT_TEST_INT                                       0x00
 
#define ECG2_CFG_FREQ_F_DIV_2_TO_21                                 0x00
#define ECG2_CFG_FREQ_F_DIV_2_TO_20                                 0x01
#define ECG2_CFG_FREQ_NOT_USED                                      0x02
#define ECG2_CFG_FREQ_AT_DC                                         0x03
 
#define ECG2_CFG_AMPLITUDE_NEGATIVE_1                               0x00
#define ECG2_CFG_AMPLITUDE_NEGATIVE_2                               0x01
 
#define ECG2_CFG_ENABLE_INT_BUFFER                                  0x80
#define ECG2_CFG_DISABLE_INT_BUFFER                                 0x00
 
#define ECG2_CFG_REFBUF_ENABLE                                      0x80
#define ECG2_CFG_REFBUF_DISABLE                                     0x00
 
#define ECG2_CFG_INTERNAL_RLDREF                                    0x08
#define ECG2_CFG_EXTERNAL_RLDREF                                    0x00
 
#define ECG2_CFG_RLD_ENABLE                                         0x0C
#define ECG2_CFG_RLD_DISABLE                                        0x00
 
#define ECG2_CFG_RLD_SENSE_ENABLE                                   0x02
#define ECG2_CFG_RLD_SENSE_DISABLE                                  0x00
 
#define ECG2_CFG_RLD_NOT_CONNECTED                                  0x01
#define ECG2_CFG_RLD_CONNECTED                                      0x00
 
#define ECG2_CFG_VREF_2V4                                          0x00
#define ECG2_CFG_VREF_4V                                            0x20
 
#define ECG2_CFG_COMPARATOR_P_95                                    0x00
#define ECG2_CFG_COMPARATOR_P_92_5                                  0x20
#define ECG2_CFG_COMPARATOR_P_90                                    0x40
#define ECG2_CFG_COMPARATOR_P_87_5                                  0x60
#define ECG2_CFG_COMPARATOR_P_85                                    0x80
#define ECG2_CFG_COMPARATOR_P_80                                    0xA0
#define ECG2_CFG_COMPARATOR_P_75                                    0xC0
#define ECG2_CFG_COMPARATOR_P_70                                    0xE0
 
#define ECG2_CFG_COMPARATOR_N_5                                     0x00
#define ECG2_CFG_COMPARATOR_N_7_5                                   0x20
#define ECG2_CFG_COMPARATOR_N_10                                    0x40
#define ECG2_CFG_COMPARATOR_N_12_5                                  0x60
#define ECG2_CFG_COMPARATOR_N_15                                    0x80
#define ECG2_CFG_COMPARATOR_N_20                                    0xA0
#define ECG2_CFG_COMPARATOR_N_25                                    0xC0
#define ECG2_CFG_COMPARATOR_N_30                                    0xE0
 
#define ECG2_CFG_VLEAD_OFF                                          0x00
#define ECG2_CFG_VLEAD_EN                                           0x10
 
#define ECG2_CFG_ILEAD_OFF_4nA                                      0x00
#define ECG2_CFG_ILEAD_OFF_8nA                                      0x04        
#define ECG2_CFG_ILEAD_OFF_12nA                                     0x08
#define ECG2_CFG_ILEAD_OFF_16nA                                     0x0C
 
#define ECG2_CFG_FLEAD_OFF_AC_OFF                                   0x01
#define ECG2_CFG_FLEAD_OFF_NOT_USED                                 0x02
#define ECG2_CFG_FLEAD_OFF_DC_OFF                                   0x03
 
#define ECG2_CFG_NORMAL_MODE                                        0x00
#define ECG2_CFG_POWER_DOWN                                         0x80
 
#define ECG2_CFG_PGA_GAIN_6                                         0x00
#define ECG2_CFG_PGA_GAIN_1                                         0x01
#define ECG2_CFG_PGA_GAIN_2                                         0x02
#define ECG2_CFG_PGA_GAIN_3                                         0x03
#define ECG2_CFG_PGA_GAIN_4                                         0x04
#define ECG2_CFG_PGA_GAIN_8                                         0x05
#define ECG2_CFG_PGA_GAIN_12                                        0x06
 
#define ECG2_CFG_MUX_NORMAL_ELECTRODE                               0x00
#define ECG2_CFG_MUX_SHORTED_INPUT                                  0x01
#define ECG2_CFG_MUX_RLD_MEASURMENTS                                0x02
#define ECG2_CFG_MUX_MVDD_MEASURMENTS                               0x03
#define ECG2_CFG_MUX_TEMPERATURE_SENSOR                             0x04
#define ECG2_CFG_MUX_TEST_SIGNAL                                    0x05
#define ECG2_CFG_MUX_RLD_DRP                                        0x06
#define ECG2_CFG_MUX_RLD_DRN                                        0x07
 
#define ECG2_CHANNEL_ODD_CHANNEL_1                                  0x00
#define ECG2_CHANNEL_ODD_CHANNEL_3                                  0x01
#define ECG2_CHANNEL_ODD_CHANNEL_5                                  0x02
#define ECG2_CHANNEL_ODD_CHANNEL_7                                  0x03
 
#define ECG2_CHANNEL_EVEN_CHANNEL_2                                 0x00
#define ECG2_CHANNEL_EVEN_CHANNEL_4                                 0x01
#define ECG2_CHANNEL_EVEN_CHANNEL_6                                 0x02
#define ECG2_CHANNEL_EVEN_CHANNEL_8                                 0x03
 
#define ECG2_CHANNEL_ENABLE                                         0x01
#define ECG2_CHANNEL_DISABLE                                        0x00
 
#define ECG2_DATA_READY                                             0x01
#define ECG2_SET_DATA_SAMPLE_EDGE      SET_SPI_DATA_SAMPLE_EDGE
#define ECG2_SET_DATA_SAMPLE_MIDDLE    SET_SPI_DATA_SAMPLE_MIDDLE
 
 // ecg2_set
 
#define ECG2_MAP_MIKROBUS( cfg, mikrobus ) \
    cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
    cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
    cfg.sck  = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
    cfg.cs   = MIKROBUS( mikrobus, MIKROBUS_CS ); \
    cfg.an = MIKROBUS( mikrobus, MIKROBUS_AN ); \
    cfg.rst = MIKROBUS( mikrobus, MIKROBUS_RST ); \
    cfg.pwd = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
    cfg.drd = MIKROBUS( mikrobus, MIKROBUS_INT )
 
 // ecg2_map
 // ecg2
 
typedef struct
{
    // Output pins
    digital_out_t  rst;         
    digital_out_t  pwd;         
    // Input pins
    digital_in_t  drd;          
    // Modules
    spi_master_t  spi;          
    pin_name_t  chip_select;    
    analog_in_t  adc;           
} ecg2_t;
 
typedef struct
{
    // Communication gpio pins
    pin_name_t  miso;          
    pin_name_t  mosi;          
    pin_name_t  sck;           
    pin_name_t  cs;            
    // Additional gpio pins
    pin_name_t  an;            
    pin_name_t  rst;           
    pin_name_t  pwd;           
    pin_name_t  drd;           
    // static variable
    uint32_t                           spi_speed;        
    spi_master_mode_t                  spi_mode;         
    spi_master_chip_select_polarity_t  cs_polarity;      
    analog_in_resolution_t  resolution;     
    float                   vref;           
} ecg2_cfg_t;
 
typedef enum
{
    ECG2_OK = 0,
    ECG2_ERROR = -1
 
} ecg2_return_value_t;
 
void ecg2_cfg_setup ( ecg2_cfg_t *cfg );
 
err_t ecg2_init ( ecg2_t *ctx, ecg2_cfg_t *cfg );
 
err_t ecg2_default_cfg ( ecg2_t *ctx );
 
err_t ecg2_generic_write ( ecg2_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len );
 
err_t ecg2_generic_read ( ecg2_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len );
 
err_t ecg2_read_an_pin_value ( ecg2_t *ctx, uint16_t *data_out );
 
err_t ecg2_write_register ( ecg2_t *ctx, uint8_t reg, uint8_t data_in );
 
err_t ecg2_read_register ( ecg2_t *ctx, uint8_t reg, uint8_t *data_out );
 
err_t ecg2_multi_write ( ecg2_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len );
 
err_t ecg2_multi_read ( ecg2_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len );
 
err_t ecg2_send_command ( ecg2_t *ctx, uint8_t command );
 
void ecg2_hw_reset ( ecg2_t *ctx );
 
uint8_t ecg2_get_device_id( ecg2_t *ctx );
 
err_t ecg2_configure_channel ( ecg2_t *ctx, uint8_t channel, uint8_t enable, uint8_t pga_gain, 
                                int8_t channel_input);
 
void ecg2_right_leg_positive_drive_set ( ecg2_t *ctx, uint8_t data_in );
 
void ecg2_right_leg_negative_drive_set ( ecg2_t *ctx, uint8_t data_in );
 
void ecg2_lead_off_positive_channel_select ( ecg2_t *ctx, uint8_t data_in );
 
void ecg2_lead_off_negative_channel_select ( ecg2_t *ctx, uint8_t data_in );
 
void ecg2_lead_off_current_direction_select ( ecg2_t *ctx, uint8_t data_in );
 
err_t ecg2_pace_detect_even_channels_select ( ecg2_t *ctx, uint8_t select );
 
err_t ecg2_pace_detect_odd_channels_select ( ecg2_t *ctx, uint8_t select );
 
void ecg2_wilson_center_terminal_configure ( ecg2_t *ctx, uint16_t set );
 
uint8_t ecg2_data_ready ( ecg2_t *ctx );
 
err_t ecg2_read_data ( ecg2_t *ctx, uint8_t *data_out, uint8_t len );
 
err_t ecg2_read_channel_data ( ecg2_t *ctx, uint8_t channel, uint16_t *data_out );
 
#ifdef __cplusplus
}
#endif
#endif // ECG2_H
 
 // ecg2
 
// ------------------------------------------------------------------------ END