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ecggsr 2.0.0.0
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| #define ECGGSR_ADC_CFGA_REG 0x88 |
| #define ECGGSR_ADC_CFGB_REG 0x89 |
| #define ECGGSR_ADC_CFGC_REG 0x8A |
| #define ECGGSR_ADC_CHANNEL_MASK_H_REG 0x8C |
| #define ECGGSR_ADC_CHANNEL_MASK_L_REG 0x8B |
| #define ECGGSR_ADC_DATA_H_MASK 0x3F |
| #define ECGGSR_ADC_DATA_H_REG 0x8F |
| #define ECGGSR_ADC_DATA_L_REG 0x8E |
| #define ECGGSR_ADC_THRESHOLD_CFG_REG 0x69 |
| #define ECGGSR_ADC_THRESHOLD_REG 0x68 |
| #define ECGGSR_AZ_CONTROL_REG 0x29 |
| #define ECGGSR_CLIPSTATUS_REG 0xA2 |
| #define ECGGSR_CONF_PHOTODIODE 0x3E |
| #define ECGGSR_CONTROL_REG 0x00 |
| #define ECGGSR_CYC_COUNTER_REG 0x60 |
| #define ECGGSR_DEV_ID 0x54 |
| #define ECGGSR_DEV_ID_MASK 0xFC |
| #define ECGGSR_EAF_BIAS_REG 0x81 |
| #define ECGGSR_EAF_CFG_REG 0x70 |
| #define ECGGSR_EAF_DAC1_H_REG 0x84 |
| #define ECGGSR_EAF_DAC1_L_REG 0x83 |
| #define ECGGSR_EAF_DAC2_H_REG 0x86 |
| #define ECGGSR_EAF_DAC2_L_REG 0x85 |
| #define ECGGSR_EAF_DAC_CFG_REG 0x87 |
| #define ECGGSR_EAF_DAC_REG 0x82 |
| #define ECGGSR_EAF_GST_REG 0x80 |
| #define ECGGSR_ECG_CFGA_REG 0x5C |
| #define ECGGSR_ECG_CFGB_REG 0x5D |
| #define ECGGSR_ECG_CFGC_REG 0x5E |
| #define ECGGSR_ECG_CFGD_REG 0x5F |
| #define ECGGSR_ECG_MODE_REG 0x5B |
| #define ECGGSR_ECG_SCALE_VAL 0x02 |
| #define ECGGSR_ECG_THRESHOLD_HIGH_REG 0x6B |
| #define ECGGSR_ECG_THRESHOLD_LOW_REG 0x6A |
| #define ECGGSR_ENABLE_ADC 0x01 |
| #define ECGGSR_ENABLE_BIAS_AND_GAIN 0x09 |
| #define ECGGSR_ENABLE_ECG_AMPLIFIER 0x88 |
| #define ECGGSR_ENABLE_GPIO1_ANALOG 0x02 |
| #define ECGGSR_ENABLE_LED12_OUTPUT 0x99 |
| #define ECGGSR_ENABLE_LED4_OUTPUT 0x90 |
| #define ECGGSR_ENABLE_OFE_AND_BIAS 0xE6 |
| #define ECGGSR_ENABLE_OSC_AND_LDO 0x03 |
| #define ECGGSR_ENABLE_PHOTOAMPLIFIER 0xBC |
| #define ECGGSR_ENABLE_REF_AMPLIFIER 0x01 |
| #define ECGGSR_ENABLE_REF_AND_DIODES 0x8B |
| #define ECGGSR_ENABLE_SIG_REFERENCE 0x80 |
| #define ECGGSR_FEEDBACK_RESISTOR 0xE2 |
| #define ECGGSR_FIFO_CFG_REG 0x78 |
| #define ECGGSR_FIFO_CNTRL_REG 0x79 |
| #define ECGGSR_FIFOH_REG 0xFF |
| #define ECGGSR_FIFOL_REG 0xFE |
| #define ECGGSR_FIFOLEVEL_REG 0xA6 |
| #define ECGGSR_FIFOSTATUS_REG 0xA4 |
| #define ECGGSR_GAIN_SETTINGS_STAGE3 0x04 |
| #define ECGGSR_GAIN_SETTINGS_STAGES1_2 0x0B |
| #define ECGGSR_GPIO_A_REG 0x08 |
| #define ECGGSR_GPIO_E_REG 0x09 |
| #define ECGGSR_GPIO_I_REG 0x0B |
| #define ECGGSR_GPIO_O_REG 0x0A |
| #define ECGGSR_GPIO_P_REG 0x0C |
| #define ECGGSR_GPIO_SR_REG 0x0D |
| #define ECGGSR_GPIO_SYNC_REG 0x0F |
| #define ECGGSR_ID_REG 0x92 |
| #define ECGGSR_INPUT_AND_REF_VOLTAGE 0xB0 |
| #define ECGGSR_INTENAB2_REG 0xA9 |
| #define ECGGSR_INTENAB_REG 0xA8 |
| #define ECGGSR_INTR2_REG 0xAB |
| #define ECGGSR_INTR_REG 0xAA |
| #define ECGGSR_ITIME_REG 0x24 |
| #define ECGGSR_LED12_MODE_REG 0x2C |
| #define ECGGSR_LED1_CURRH_REG 0x13 |
| #define ECGGSR_LED1_CURRL_REG 0x12 |
| #define ECGGSR_LED2_CURRH_REG 0x15 |
| #define ECGGSR_LED2_CURRL_REG 0x14 |
| #define ECGGSR_LED34_MODE_REG 0x2D |
| #define ECGGSR_LED3_CURRH_REG 0x17 |
| #define ECGGSR_LED3_CURRL_REG 0x16 |
| #define ECGGSR_LED4_CURRH_REG 0x19 |
| #define ECGGSR_LED4_CURRL_REG 0x18 |
| #define ECGGSR_LED_CFG_REG 0x10 |
| #define ECGGSR_LED_CURR_HIGH_2 0x59 |
| #define ECGGSR_LED_CURR_HIGH_3 0xFF |
| #define ECGGSR_LED_CURR_LOW_2 0x80 |
| #define ECGGSR_LED_CURR_LOW_3 0xC0 |
| #define ECGGSR_LED_WAIT_LOW_REG 0x11 |
| #define ECGGSR_LEDSTATUS_REG 0xA3 |
| #define ECGGSR_LTF_CONFIG_REG 0x25 |
| #define ECGGSR_LTF_CONTROL_REG 0x28 |
| #define ECGGSR_LTF_GAIN_REG 0x27 |
| #define ECGGSR_LTF_SEL_REG 0x26 |
| #define ECGGSR_LTF_THRESHOLD_HIGH0_REG 0x6E |
| #define ECGGSR_LTF_THRESHOLD_HIGH1_REG 0x6F |
| #define ECGGSR_LTF_THRESHOLD_LOW0_REG 0x6C |
| #define ECGGSR_LTF_THRESHOLD_LOW1_REG 0x6D |
| #define ECGGSR_LTFDATA0_H_REG 0x21 |
| #define ECGGSR_LTFDATA0_L_REG 0x20 |
| #define ECGGSR_LTFDATA1_H_REG 0x23 |
| #define ECGGSR_LTFDATA1_L_REG 0x22 |
| #define ECGGSR_LTFSTATUS_REG 0xA5 |
| #define ECGGSR_MAN_SEQ_CFG_REG 0x2E |
| #define ECGGSR_OFE1_CFGA 0x70 |
| #define ECGGSR_OFE1_CFGA_REG 0x54 |
| #define ECGGSR_OFE1_CFGB_REG 0x55 |
| #define ECGGSR_OFE1_PD_THCFG_REG 0x1F |
| #define ECGGSR_OFE1_SD_THCFG_REG 0x51 |
| #define ECGGSR_OFE2_CFGA 0x70 |
| #define ECGGSR_OFE2_CFGA_REG 0x58 |
| #define ECGGSR_OFE2_CFGB_REG 0x59 |
| #define ECGGSR_OFE2_PD_THCFG_REG 0x56 |
| #define ECGGSR_OFE2_SD_THCFG_REG 0x57 |
| #define ECGGSR_OFE_CFGA_REG 0x50 |
| #define ECGGSR_OFE_CFGC_REG 0x52 |
| #define ECGGSR_OFE_CFGD_REG 0x53 |
| #define ECGGSR_OFE_NOTCH_REG 0x5A |
| #define ECGGSR_OFFSET0_REG 0x2A |
| #define ECGGSR_OFFSET1_REG 0x2B |
| #define ECGGSR_PD_AMPCFG_REG 0x1E |
| #define ECGGSR_PD_AMPRCCFG_REG 0x1D |
| #define ECGGSR_PD_CFG_REG 0x1A |
| #define ECGGSR_PD_LED_CURRENT 0x80 |
| #define ECGGSR_PDOFFX_LEDOFF_REG 0x1B |
| #define ECGGSR_PDOFFX_LEDON_REG 0x1C |
| #define ECGGSR_PPG_H_THRESHOLD 0x5F |
| #define ECGGSR_PPG_L_THRESHOLD 0x48 |
| #define ECGGSR_PPG_MAX_VAL 0x64 |
| #define ECGGSR_PPG_SCALE_VAL 0x64 |
| #define ECGGSR_READ_VALUE_CONTROL_REG 0x83 |
| #define ECGGSR_RESISTIVE_BIASING 0xA0 |
| #define ECGGSR_SD_SUBS_REG 0x45 |
| #define ECGGSR_SELECT_AMPLIFIER_INPUT 0x01 |
| #define ECGGSR_SELECT_EFE 0x40 |
| #define ECGGSR_SEQ_ADC2TIA_REG 0x43 |
| #define ECGGSR_SEQ_ADC3TIA_REG 0x44 |
| #define ECGGSR_SEQ_ADC_REG 0x42 |
| #define ECGGSR_SEQ_CFG_REG 0x46 |
| #define ECGGSR_SEQ_CNT_REG 0x30 |
| #define ECGGSR_SEQ_COUNTER_REG 0x61 |
| #define ECGGSR_SEQ_DIS_SEL_REG 0x4A |
| #define ECGGSR_SEQ_DIS_VAL1_REG 0x4B |
| #define ECGGSR_SEQ_DIS_VAL2_REG 0x4C |
| #define ECGGSR_SEQ_DIV_REG 0x31 |
| #define ECGGSR_SEQ_ERR_REG 0x47 |
| #define ECGGSR_SEQ_ITG_STA_REG 0x38 |
| #define ECGGSR_SEQ_ITG_STO_REG 0x39 |
| #define ECGGSR_SEQ_LED_ST_REG 0x34 |
| #define ECGGSR_SEQ_LED_STO_REG 0x35 |
| #define ECGGSR_SEQ_OVS_SEL_REG 0x48 |
| #define ECGGSR_SEQ_OVS_VAL_REG 0x49 |
| #define ECGGSR_SEQ_PER_REG 0x33 |
| #define ECGGSR_SEQ_SDM1_STA_REG 0x3E |
| #define ECGGSR_SEQ_SDM1_STO_REG 0x3F |
| #define ECGGSR_SEQ_SDM2_STA_REG 0x40 |
| #define ECGGSR_SEQ_SDM2_STO_REG 0x41 |
| #define ECGGSR_SEQ_SDP1_STA_REG 0x3A |
| #define ECGGSR_SEQ_SDP1_STO_REG 0x3B |
| #define ECGGSR_SEQ_SDP2_STA_REG 0x3C |
| #define ECGGSR_SEQ_SDP2_STO_REG 0x3D |
| #define ECGGSR_SEQ_SECLED_STA_REG 0x36 |
| #define ECGGSR_SEQ_SECLED_STO_REG 0x37 |
| #define ECGGSR_SEQ_START_REG 0x32 |
| #define ECGGSR_SET_GPIO1_AS_INPUT 0x46 |
| #define ECGGSR_SET_RES_BIAS_GPIO1 0x40 |
| #define ECGGSR_SET_SLEW_RATE_GPIO1 0x02 |
| #define ECGGSR_START_ADC_CONVERSION 0x01 |
| #define ECGGSR_START_PPG 0xE1 |
| #define ECGGSR_START_SEQUENCER 0xE1 |
| #define ECGGSR_STATUS2_REG 0xA1 |
| #define ECGGSR_STATUS_REG 0xA0 |
| #define ECGGSR_SUBID_REG 0x91 |
| #define ECGGSR_SUBS_COUNTER_REG 0x62 |
| #define ECGGSR_SUNLIGHT_COMPENSATION 0x5E |