eeprom9.h

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/****************************************************************************
** Copyright (C) 2020 MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and associated documentation files (the "Software"), to deal
** in the Software without restriction, including without limitation the rights
** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
** copies of the Software, and to permit persons to whom the Software is
** furnished to do so, subject to the following conditions:
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
**  USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/
 
#ifndef EEPROM9_H
#define EEPROM9_H
 
#ifdef __cplusplus
extern "C"{
#endif
 
#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_spi_master.h"
#include "spi_specifics.h"
 
#define EEPROM9_HOLD_DISABLE                                    0x00
#define EEPROM9_HOLD_ENABLE                                     0x01
#define EEPROM9_WRITE_PROTECT_DISABLE                           0x00
#define EEPROM9_WRITE_PROTECT_ENABLE                            0x01
#define EEPROM9_WRITE_ENABLE                                    0x00
#define EEPROM9_WRITE_DISABLE                                   0x01
 
#define EEPROM9_SRWD_MASK                                       0x80
#define EEPROM9_TB_MASK                                         0x40
#define EEPROM9_BP2_MASK                                        0x10
#define EEPROM9_BP1_MASK                                        0x08
#define EEPROM9_BP0_MASK                                        0x04
#define EEPROM9_WEL_MASK                                        0x02
#define EEPROM9_WIP_MASK                                        0x01
 
#define EEPROM9_ST_MANUFACTURER_CODE                            0x20
 
#define EEPROM9_MEMORY_ADDR_START                               0x00000000ul
#define EEPROM9_MEMORY_ADDR_END                                 0x003FFFFFul
 
#define EEPROM9_CMD_WREN                                        0x06
#define EEPROM9_CMD_WRDI                                        0x04
#define EEPROM9_CMD_RDSR                                        0x05
#define EEPROM9_CMD_WRSR                                        0x01
#define EEPROM9_CMD_READ                                        0x03
#define EEPROM9_CMD_FREAD                                       0x0B
#define EEPROM9_CMD_FDREAD                                      0x3B
#define EEPROM9_CMD_FQREAD                                      0x6B
#define EEPROM9_CMD_PGWR                                        0x02
#define EEPROM9_CMD_PGPR                                        0x0A
#define EEPROM9_CMD_PGER                                        0xDB
#define EEPROM9_CMD_SCER                                        0x20
#define EEPROM9_CMD_BKER                                        0xD8
#define EEPROM9_CMD_CHER                                        0xC7
#define EEPROM9_CMD_RDID                                        0x83
#define EEPROM9_CMD_FRDID                                       0x8B
#define EEPROM9_CMD_WRID                                        0x82
#define EEPROM9_CMD_DPD                                         0xB9
#define EEPROM9_CMD_RDPD                                        0xAB
#define EEPROM9_CMD_JEDPC                                       0x9F
#define EEPROM9_CMD_RDCR                                        0x15
#define EEPROM9_CMD_RDVR                                        0x85
#define EEPROM9_CMD_WRVR                                        0x81
#define EEPROM9_CMD_CLRSF                                       0x50
#define EEPROM9_CMD_RDSFDP                                      0x5A
#define EEPROM9_CMD_RSTEN                                       0x66
#define EEPROM9_CMD_RESET                                       0x99
 
#define EEPROM9_SET_DATA_SAMPLE_EDGE      SET_SPI_DATA_SAMPLE_EDGE
#define EEPROM9_SET_DATA_SAMPLE_MIDDLE    SET_SPI_DATA_SAMPLE_MIDDLE
 
 // eeprom9_set
 
#define EEPROM9_MAP_MIKROBUS( cfg, mikrobus ) \
    cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
    cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
    cfg.sck  = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
    cfg.cs   = MIKROBUS( mikrobus, MIKROBUS_CS ); \
    cfg.wp   = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
    cfg.hld  = MIKROBUS( mikrobus, MIKROBUS_INT )
 
 // eeprom9_map
 // eeprom9
 
typedef struct
{
    // Output pins
    digital_out_t wp;               
    digital_out_t hld;              
    // Modules
    spi_master_t spi;               
    pin_name_t   chip_select;       
} eeprom9_t;
 
typedef struct
{
    // Communication gpio pins
    pin_name_t miso;            
    pin_name_t mosi;            
    pin_name_t sck;             
    pin_name_t cs;              
    // Additional gpio pins
    pin_name_t wp;              
    pin_name_t hld;             
    // static variable
    uint32_t                          spi_speed;    
    spi_master_mode_t                 spi_mode;     
    spi_master_chip_select_polarity_t cs_polarity;  
} eeprom9_cfg_t;
 
typedef struct
{
    uint8_t manufact_code;      
    uint8_t spi_code;           
    uint8_t memory_density;     
} id_data_t;
 
typedef enum
{
    EEPROM9_OK = 0,
    EEPROM9_ERROR = -1
 
} eeprom9_return_value_t;
 
void eeprom9_cfg_setup ( eeprom9_cfg_t *cfg );
 
err_t eeprom9_init ( eeprom9_t *ctx, eeprom9_cfg_t *cfg );
 
err_t eeprom9_generic_write ( eeprom9_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len );
 
err_t eeprom9_generic_read ( eeprom9_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len );
 
void eeprom9_set_hold ( eeprom9_t *ctx, uint8_t en_hold );
 
void eeprom9_set_write_protection ( eeprom9_t *ctx, uint8_t en_wp );
 
err_t eeprom9_send_cmd ( eeprom9_t *ctx, uint8_t cmd );
 
err_t eeprom9_set_write_enable ( eeprom9_t *ctx, uint8_t en_write );
 
err_t eeprom9_read_memory ( eeprom9_t *ctx, uint32_t mem_addr, uint8_t *data_out, uint8_t len );
 
err_t eeprom9_write_memory ( eeprom9_t *ctx, uint32_t mem_addr, uint8_t *data_in, uint8_t len );
 
err_t eeprom5_get_status_reg ( eeprom9_t *ctx, uint8_t *status_data );
 
err_t eeprom9_chip_erase ( eeprom9_t *ctx );
 
err_t eeprom9_block_erase ( eeprom9_t *ctx, uint32_t block_addr );
 
err_t eeprom9_sector_erase ( eeprom9_t *ctx, uint32_t sector_addr );
 
err_t eeprom9_page_erase ( eeprom9_t *ctx, uint32_t page_addr );
 
err_t eeprom9_read_identification ( eeprom9_t *ctx, id_data_t *id_data  );
 
#ifdef __cplusplus
}
#endif
#endif // EEPROM9_H
 
 // eeprom9
 
// ------------------------------------------------------------------------ END