Any initialization code needed for MCU to function properly. Do not remove this line or clock might not be set correctly.
◆ ENOCEAN3_BUFF_EMPTY
| #define ENOCEAN3_BUFF_EMPTY 0x00 |
◆ ENOCEAN3_CO_EVENT_SECUREDEVICES
| #define ENOCEAN3_CO_EVENT_SECUREDEVICES 0x05 |
◆ ENOCEAN3_CO_SET_NOISETHRESHOLD
| #define ENOCEAN3_CO_SET_NOISETHRESHOLD 0x32 |
◆ ENOCEAN3_CO_WR_FILTER_ADD
| #define ENOCEAN3_CO_WR_FILTER_ADD 0x0B |
◆ ENOCEAN3_CO_WR_FILTER_ENABLE
| #define ENOCEAN3_CO_WR_FILTER_ENABLE 0x0E |
◆ ENOCEAN3_CO_WR_REPEATER
| #define ENOCEAN3_CO_WR_REPEATER 0x09 |
◆ ENOCEAN3_FILT_FWRD_OFF
| #define ENOCEAN3_FILT_FWRD_OFF 0x00 |
◆ ENOCEAN3_FILT_FWRD_ON
| #define ENOCEAN3_FILT_FWRD_ON 0x01 |
◆ ENOCEAN3_FILT_KIND_NEG_TEL_FWRD
| #define ENOCEAN3_FILT_KIND_NEG_TEL_FWRD 0x00 |
◆ ENOCEAN3_FILT_KIND_NEG_TEL_RPT
| #define ENOCEAN3_FILT_KIND_NEG_TEL_RPT 0x40 |
◆ ENOCEAN3_FILT_KIND_POS_TEL_FWRD
| #define ENOCEAN3_FILT_KIND_POS_TEL_FWRD 0x80 |
◆ ENOCEAN3_FILT_KIND_POS_TEL_RPT
| #define ENOCEAN3_FILT_KIND_POS_TEL_RPT 0xC0 |
◆ ENOCEAN3_FILT_OP_AND_ALL_FILT
| #define ENOCEAN3_FILT_OP_AND_ALL_FILT 0x01 |
◆ ENOCEAN3_FILT_OP_AND_RADIO_INTER_OR_FILT_RPT
| #define ENOCEAN3_FILT_OP_AND_RADIO_INTER_OR_FILT_RPT 0x09 |
◆ ENOCEAN3_FILT_OP_OR_ALL_FILT
| #define ENOCEAN3_FILT_OP_OR_ALL_FILT 0x00 |
◆ ENOCEAN3_FILT_OP_OR_RADIO_INTER_AND_FILT_RPT
| #define ENOCEAN3_FILT_OP_OR_RADIO_INTER_AND_FILT_RPT 0x08 |
◆ ENOCEAN3_FILT_TYPE_DEST_ID
| #define ENOCEAN3_FILT_TYPE_DEST_ID 0x03 |
◆ ENOCEAN3_FILT_TYPE_R_ORG
| #define ENOCEAN3_FILT_TYPE_R_ORG 0x01 |
◆ ENOCEAN3_FILT_TYPE_RSSI
| #define ENOCEAN3_FILT_TYPE_RSSI 0x02 |
◆ ENOCEAN3_FILT_TYPE_SOURCE_ID
| #define ENOCEAN3_FILT_TYPE_SOURCE_ID 0x00 |
◆ ENOCEAN3_HEADER_SIZE
| #define ENOCEAN3_HEADER_SIZE 0x04 |
◆ ENOCEAN3_INVALID_PACKET_SIZE
| #define ENOCEAN3_INVALID_PACKET_SIZE 0x01 |
◆ ENOCEAN3_MAX_BUFF_SIZE
| #define ENOCEAN3_MAX_BUFF_SIZE 256 |
◆ ENOCEAN3_PACK_TYPE_COMMON_COMMAND
| #define ENOCEAN3_PACK_TYPE_COMMON_COMMAND 0x05 |
◆ ENOCEAN3_PACK_TYPE_EVENT
| #define ENOCEAN3_PACK_TYPE_EVENT 0x04 |
◆ ENOCEAN3_RESPONSE_NOT_READY
| #define ENOCEAN3_RESPONSE_NOT_READY 0x00 |
◆ ENOCEAN3_RESPONSE_READY
| #define ENOCEAN3_RESPONSE_READY 0x01 |
◆ ENOCEAN3_RPT_ALL_TELEG
| #define ENOCEAN3_RPT_ALL_TELEG 0x01 |
◆ ENOCEAN3_RPT_LEVEL_OFF
| #define ENOCEAN3_RPT_LEVEL_OFF 0x00 |
◆ ENOCEAN3_RPT_LEVEL_ONE
| #define ENOCEAN3_RPT_LEVEL_ONE 0x01 |
◆ ENOCEAN3_RPT_LEVEL_TWO
| #define ENOCEAN3_RPT_LEVEL_TWO 0x02 |
◆ ENOCEAN3_RPT_OFF
| #define ENOCEAN3_RPT_OFF 0x00 |
◆ ENOCEAN3_RPT_SELECTIVE
| #define ENOCEAN3_RPT_SELECTIVE 0x02 |
◆ ENOCEAN3_RSSI_LEVEL_100_DBM_NEG
| #define ENOCEAN3_RSSI_LEVEL_100_DBM_NEG 0x2E |
◆ ENOCEAN3_RSSI_LEVEL_90_DBM_NEG
| #define ENOCEAN3_RSSI_LEVEL_90_DBM_NEG 0x38 |
◆ ENOCEAN3_RSSI_LEVEL_91_DBM_NEG
| #define ENOCEAN3_RSSI_LEVEL_91_DBM_NEG 0x37 |
◆ ENOCEAN3_RSSI_LEVEL_92_DBM_NEG
| #define ENOCEAN3_RSSI_LEVEL_92_DBM_NEG 0x36 |
◆ ENOCEAN3_RSSI_LEVEL_93_DBM_NEG
| #define ENOCEAN3_RSSI_LEVEL_93_DBM_NEG 0x35 |
◆ ENOCEAN3_RSSI_LEVEL_94_DBM_NEG
| #define ENOCEAN3_RSSI_LEVEL_94_DBM_NEG 0x34 |
◆ ENOCEAN3_RSSI_LEVEL_95_DBM_NEG
| #define ENOCEAN3_RSSI_LEVEL_95_DBM_NEG 0x33 |
◆ ENOCEAN3_RSSI_LEVEL_96_DBM_NEG
| #define ENOCEAN3_RSSI_LEVEL_96_DBM_NEG 0x32 |
◆ ENOCEAN3_RSSI_LEVEL_97_DBM_NEG
| #define ENOCEAN3_RSSI_LEVEL_97_DBM_NEG 0x31 |
◆ ENOCEAN3_RSSI_LEVEL_98_DBM_NEG
| #define ENOCEAN3_RSSI_LEVEL_98_DBM_NEG 0x30 |
◆ ENOCEAN3_RSSI_LEVEL_99_DBM_NEG
| #define ENOCEAN3_RSSI_LEVEL_99_DBM_NEG 0x2F |
◆ ENOCEAN3_SYNC_BYTE
| #define ENOCEAN3_SYNC_BYTE 0x55 |
◆ ENOCEAN3_UART_RX_NOT_READY
| #define ENOCEAN3_UART_RX_NOT_READY 0x00 |
◆ ENOCEAN3_UART_RX_READY
| #define ENOCEAN3_UART_RX_READY 0x01 |