Macros
#define	ENOCEAN2_CO_WR_SLEEP 0x01

#define	ENOCEAN2_CO_WR_RESET 0x02

#define	ENOCEAN2_CO_RD_VERSION 0x03

#define	ENOCEAN2_CO_RD_SYS_LOG 0x04

#define	ENOCEAN2_CO_WR_SYS_LOG 0x05

#define	ENOCEAN2_CO_WR_BIST 0x06

#define	ENOCEAN2_CO_WR_IDBASE 0x07

#define	ENOCEAN2_CO_RD_IDBASE 0x08

#define	ENOCEAN2_CO_WR_REPEATER 0x09

#define	ENOCEAN2_CO_RD_REPEATER 0x0A

#define	ENOCEAN2_CO_WR_FILTER_ADD 0x0B

#define	ENOCEAN2_CO_WR_FILTER_DEL 0x0C

#define	ENOCEAN2_CO_WR_FILTER_DEL_ALL 0x0D

#define	ENOCEAN2_CO_WR_FILTER_ENABLE 0x0E

#define	ENOCEAN2_CO_RD_FILTER 0x0F

#define	ENOCEAN2_CO_WR_WAIT_MATURITY 0x10

#define	ENOCEAN2_CO_WR_SUBTEL 0x11

#define	ENOCEAN2_CO_WR_MEM 0x12

#define	ENOCEAN2_CO_RD_MEM 0x13

#define	ENOCEAN2_CO_RD_MEM_ADDRESS 0x14

#define	ENOCEAN2_CO_RD_SECURITY 0x15

#define	ENOCEAN2_CO_WR_SECURITY 0x16

#define	ENOCEAN2_CO_WR_LEARNMODE 0x17

#define	ENOCEAN2_CO_RD_LEARNMODE 0x18

#define	ENOCEAN2_CO_WR_SECUREDEVICE_ADD 0x19

#define	ENOCEAN2_CO_WR_SECUREDEVICE_DEL 0x20

#define	ENOCEAN2_CO_RD_SECUREDEVICE_BY_INDEX 0x21

#define	ENOCEAN2_CO_WR_MODE 0x22

#define	ENOCEAN2_CO_RD_NUMSECUREDEVICES 0x23

#define	ENOCEAN2_CO_RD_SECUREDEVICE_BY_ID 0x24

#define	ENOCEAN2_CO_WR_SECUREDEVICE_ADD_PSK 0x25

#define	ENOCEAN2_CO_WR_SECUREDEVICE_SENDTEACHIN 0x26

#define	ENOCEAN2_CO_WR_TEMPORARY_RLC_WINDOW 0x27

#define	ENOCEAN2_CO_RD_SECUREDEVICE_PSK 0x28

#define	ENOCEAN2_CO_RD_DUTYCYCLE_LIMIT 0x29

#define	ENOCEAN2_CO_SET_BAUDRATE 0x30

#define	ENOCEAN2_CO_GET_FREQUENCY_INFO 0x31

#define	ENOCEAN2_CO_GET_STEPCODE 0x32

Detailed Description

Macro Definition Documentation

◆ ENOCEAN2_CO_GET_FREQUENCY_INFO

#define ENOCEAN2_CO_GET_FREQUENCY_INFO 0x31

◆ ENOCEAN2_CO_GET_STEPCODE

#define ENOCEAN2_CO_GET_STEPCODE 0x32

◆ ENOCEAN2_CO_RD_DUTYCYCLE_LIMIT

#define ENOCEAN2_CO_RD_DUTYCYCLE_LIMIT 0x29

◆ ENOCEAN2_CO_RD_FILTER

#define ENOCEAN2_CO_RD_FILTER 0x0F

◆ ENOCEAN2_CO_RD_IDBASE

#define ENOCEAN2_CO_RD_IDBASE 0x08

◆ ENOCEAN2_CO_RD_LEARNMODE

#define ENOCEAN2_CO_RD_LEARNMODE 0x18

◆ ENOCEAN2_CO_RD_MEM

#define ENOCEAN2_CO_RD_MEM 0x13

◆ ENOCEAN2_CO_RD_MEM_ADDRESS

#define ENOCEAN2_CO_RD_MEM_ADDRESS 0x14

◆ ENOCEAN2_CO_RD_NUMSECUREDEVICES

#define ENOCEAN2_CO_RD_NUMSECUREDEVICES 0x23

◆ ENOCEAN2_CO_RD_REPEATER

#define ENOCEAN2_CO_RD_REPEATER 0x0A

◆ ENOCEAN2_CO_RD_SECUREDEVICE_BY_ID

#define ENOCEAN2_CO_RD_SECUREDEVICE_BY_ID 0x24

◆ ENOCEAN2_CO_RD_SECUREDEVICE_BY_INDEX

#define ENOCEAN2_CO_RD_SECUREDEVICE_BY_INDEX 0x21

◆ ENOCEAN2_CO_RD_SECUREDEVICE_PSK

#define ENOCEAN2_CO_RD_SECUREDEVICE_PSK 0x28

◆ ENOCEAN2_CO_RD_SECURITY

#define ENOCEAN2_CO_RD_SECURITY 0x15

◆ ENOCEAN2_CO_RD_SYS_LOG

#define ENOCEAN2_CO_RD_SYS_LOG 0x04

◆ ENOCEAN2_CO_RD_VERSION

#define ENOCEAN2_CO_RD_VERSION 0x03

◆ ENOCEAN2_CO_SET_BAUDRATE

#define ENOCEAN2_CO_SET_BAUDRATE 0x30

◆ ENOCEAN2_CO_WR_BIST

#define ENOCEAN2_CO_WR_BIST 0x06

◆ ENOCEAN2_CO_WR_FILTER_ADD

#define ENOCEAN2_CO_WR_FILTER_ADD 0x0B

◆ ENOCEAN2_CO_WR_FILTER_DEL

#define ENOCEAN2_CO_WR_FILTER_DEL 0x0C

◆ ENOCEAN2_CO_WR_FILTER_DEL_ALL

#define ENOCEAN2_CO_WR_FILTER_DEL_ALL 0x0D

◆ ENOCEAN2_CO_WR_FILTER_ENABLE

#define ENOCEAN2_CO_WR_FILTER_ENABLE 0x0E

◆ ENOCEAN2_CO_WR_IDBASE

#define ENOCEAN2_CO_WR_IDBASE 0x07

◆ ENOCEAN2_CO_WR_LEARNMODE

#define ENOCEAN2_CO_WR_LEARNMODE 0x17

◆ ENOCEAN2_CO_WR_MEM

#define ENOCEAN2_CO_WR_MEM 0x12

◆ ENOCEAN2_CO_WR_MODE

#define ENOCEAN2_CO_WR_MODE 0x22

◆ ENOCEAN2_CO_WR_REPEATER

#define ENOCEAN2_CO_WR_REPEATER 0x09

◆ ENOCEAN2_CO_WR_RESET

#define ENOCEAN2_CO_WR_RESET 0x02

◆ ENOCEAN2_CO_WR_SECUREDEVICE_ADD

#define ENOCEAN2_CO_WR_SECUREDEVICE_ADD 0x19

◆ ENOCEAN2_CO_WR_SECUREDEVICE_ADD_PSK

#define ENOCEAN2_CO_WR_SECUREDEVICE_ADD_PSK 0x25

◆ ENOCEAN2_CO_WR_SECUREDEVICE_DEL

#define ENOCEAN2_CO_WR_SECUREDEVICE_DEL 0x20

◆ ENOCEAN2_CO_WR_SECUREDEVICE_SENDTEACHIN

#define ENOCEAN2_CO_WR_SECUREDEVICE_SENDTEACHIN 0x26

◆ ENOCEAN2_CO_WR_SECURITY

#define ENOCEAN2_CO_WR_SECURITY 0x16

◆ ENOCEAN2_CO_WR_SLEEP

#define ENOCEAN2_CO_WR_SLEEP 0x01

◆ ENOCEAN2_CO_WR_SUBTEL

#define ENOCEAN2_CO_WR_SUBTEL 0x11

◆ ENOCEAN2_CO_WR_SYS_LOG

#define ENOCEAN2_CO_WR_SYS_LOG 0x05

◆ ENOCEAN2_CO_WR_TEMPORARY_RLC_WINDOW

#define ENOCEAN2_CO_WR_TEMPORARY_RLC_WINDOW 0x27

◆ ENOCEAN2_CO_WR_WAIT_MATURITY

#define ENOCEAN2_CO_WR_WAIT_MATURITY 0x10

Macros