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enocean4 2.0.0.0
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Topics | |
| MikroBUS | |
| Error Code | |
| Driver define | |
Any initialization code needed for MCU to function properly. Do not remove this line or clock might not be set correctly.
| #define ENOCEAN4_115200_BAUDRATE 0x01 |
| #define ENOCEAN4_230400_BAUDRATE 0x02 |
| #define ENOCEAN4_460800_BAUDRATE 0x03 |
| #define ENOCEAN4_57600_BAUDRATE 0x00 |
| #define ENOCEAN4_ADVANCED_MODE_ERP2 0x01 |
| #define ENOCEAN4_APPLY_FILTERED_RPT 0xC0 |
| #define ENOCEAN4_APPLY_RADIO_INTER 0x80 |
| #define ENOCEAN4_BLOCK_FILTERED_RPT 0x40 |
| #define ENOCEAN4_BLOCK_RADIO_INTER 0x00 |
| #define ENOCEAN4_BUFF_EMPTY 0x00 |
| #define ENOCEAN4_CMD_CO_GET_FREQUENCY_INFO 0x25 |
| #define ENOCEAN4_CMD_CO_GET_NOISETHRESHOLD 0x33 |
| #define ENOCEAN4_CMD_CO_GET_STEPCODE 0x27 |
| #define ENOCEAN4_CMD_CO_RD_DUTYCYCLE_LIMIT 0x23 |
| #define ENOCEAN4_CMD_CO_RD_FILTER 0x0F |
| #define ENOCEAN4_CMD_CO_RD_IDBASE 0x08 |
| #define ENOCEAN4_CMD_CO_RD_LEARNMODE 0x18 |
| #define ENOCEAN4_CMD_CO_RD_MEM 0x13 |
| #define ENOCEAN4_CMD_CO_RD_MEM_ADDRESS 0x14 |
| #define ENOCEAN4_CMD_CO_RD_NUMSECUREDEVICES 0x1D |
| #define ENOCEAN4_CMD_CO_RD_REMAN_REPEATING 0x31 |
| #define ENOCEAN4_CMD_CO_RD_REPEATER 0x0A |
| #define ENOCEAN4_CMD_CO_RD_SECUREDEVICE_BY_ID 0x1E |
| #define ENOCEAN4_CMD_CO_RD_SECUREDEVICE_BY_INDEX 0x1B |
| #define ENOCEAN4_CMD_CO_RD_SECUREDEVICE_PSK 0x22 |
| #define ENOCEAN4_CMD_CO_RD_SECURITY 0x15 |
| #define ENOCEAN4_CMD_CO_RD_SYS_LOG 0x04 |
| #define ENOCEAN4_CMD_CO_RD_VERSION 0x03 |
| #define ENOCEAN4_CMD_CO_SET_BAUDRATE 0x24 |
| #define ENOCEAN4_CMD_CO_SET_NOISETHRESHOLD 0x32 |
| #define ENOCEAN4_CMD_CO_WR_BIST 0x06 |
| #define ENOCEAN4_CMD_CO_WR_FILTER_ADD 0x0B |
| #define ENOCEAN4_CMD_CO_WR_FILTER_DEL 0x0C |
| #define ENOCEAN4_CMD_CO_WR_FILTER_DEL_ALL 0x0D |
| #define ENOCEAN4_CMD_CO_WR_FILTER_ENABLE 0x0E |
| #define ENOCEAN4_CMD_CO_WR_IDBASE 0x07 |
| #define ENOCEAN4_CMD_CO_WR_LEARNMODE 0x17 |
| #define ENOCEAN4_CMD_CO_WR_MEM 0x12 |
| #define ENOCEAN4_CMD_CO_WR_MODE 0x1C |
| #define ENOCEAN4_CMD_CO_WR_REMAN_CODE 0x2E |
| #define ENOCEAN4_CMD_CO_WR_REMAN_REPEATING 0x30 |
| #define ENOCEAN4_CMD_CO_WR_REPEATER 0x09 |
| #define ENOCEAN4_CMD_CO_WR_RESET 0x02 |
| #define ENOCEAN4_CMD_CO_WR_SECUREDEVICE_ADD 0x19 |
| #define ENOCEAN4_CMD_CO_WR_SECUREDEVICE_ADD_PSK 0x1F |
| #define ENOCEAN4_CMD_CO_WR_SECUREDEVICE_DEL 0x1A |
| #define ENOCEAN4_CMD_CO_WR_SECUREDEVICE_SENDTEACHIN 0x20 |
| #define ENOCEAN4_CMD_CO_WR_SECURITY 0x16 |
| #define ENOCEAN4_CMD_CO_WR_SLEEP 0x01 |
| #define ENOCEAN4_CMD_CO_WR_STARTUP_DELAY 0x2F |
| #define ENOCEAN4_CMD_CO_WR_SUBTEL 0x11 |
| #define ENOCEAN4_CMD_CO_WR_SYS_LOG 0x05 |
| #define ENOCEAN4_CMD_CO_WR_TEMPORARY_RLC_WINDOW 0x21 |
| #define ENOCEAN4_CMD_CO_WR_WAIT_MATURITY 0x10 |
| #define ENOCEAN4_COMPATIBLE_MODE_ERP1 0x00 |
| #define ENOCEAN4_CRC8D_ERROR 0xFD |
| #define ENOCEAN4_CRC8H_ERROR 0xFE |
| #define ENOCEAN4_DISABLE 0x00 |
| #define ENOCEAN4_ENABLE 0x01 |
| #define ENOCEAN4_EVENT_CO_DUTYCYCLE_LIMIT 0x06 |
| #define ENOCEAN4_EVENT_CO_EVENT_SECUREDEVICES 0x05 |
| #define ENOCEAN4_EVENT_CO_READY 0x04 |
| #define ENOCEAN4_EVENT_CO_TRANSMIT_FAILED 0x07 |
| #define ENOCEAN4_EVENT_SA_CONFIRM_LEARN 0x02 |
| #define ENOCEAN4_EVENT_SA_LEARN_ACK 0x03 |
| #define ENOCEAN4_EVENT_SA_RECLAIM_NOT_SUCCESSFUL 0x01 |
| #define ENOCEAN4_FILTER_TYPE_DBM 0x02 |
| #define ENOCEAN4_FILTER_TYPE_DEST_ID 0x03 |
| #define ENOCEAN4_FILTER_TYPE_DEV_ID 0x00 |
| #define ENOCEAN4_FILTER_TYPE_RORG 0x01 |
| #define ENOCEAN4_HEADER_SIZE 0x04 |
| #define ENOCEAN4_INVALID_PACKET_SIZE 0xFC |
| #define ENOCEAN4_MAX_BUFF_SIZE 256 |
| #define ENOCEAN4_PACK_TYPE_CMD_2_4 0x11 |
| #define ENOCEAN4_PACK_TYPE_COMMON_CMD 0x05 |
| #define ENOCEAN4_PACK_TYPE_EVENT 0x04 |
| #define ENOCEAN4_PACK_TYPE_RADIO_802_15_4 0x10 |
| #define ENOCEAN4_PACK_TYPE_RADIO_ERP1 0x01 |
| #define ENOCEAN4_PACK_TYPE_RADIO_ERP2 0x0A |
| #define ENOCEAN4_PACK_TYPE_RADIO_MSG 0x09 |
| #define ENOCEAN4_PACK_TYPE_RADIO_SUB_TEL 0x03 |
| #define ENOCEAN4_PACK_TYPE_REMOTE_MAN_CMD 0x07 |
| #define ENOCEAN4_PACK_TYPE_RESPONSE 0x02 |
| #define ENOCEAN4_PACK_TYPE_SMART_ACK_CMD 0x06 |
| #define ENOCEAN4_R802_WR_CHANNEL 0x01 |
| #define ENOCEAN4_R820_RD_CHANNEL 0x02 |
| #define ENOCEAN4_RESPONSE_NOT_READY 0x00 |
| #define ENOCEAN4_RESPONSE_READY 0x01 |
| #define ENOCEAN4_RET_BUFF_TO_SMALL 0x06 |
| #define ENOCEAN4_RET_ERROR 0x01 |
| #define ENOCEAN4_RET_LOCK_SET 0x05 |
| #define ENOCEAN4_RET_NO_FREE_BUFF 0x07 |
| #define ENOCEAN4_RET_NOT_SUPPORTED 0x02 |
| #define ENOCEAN4_RET_OK 0x00 |
| #define ENOCEAN4_RET_OP_DENIED 0x04 |
| #define ENOCEAN4_RET_WRONG_PARAM 0x03 |
| #define ENOCEAN4_RORG_4BS 0xA5 |
| #define ENOCEAN4_RORG_ADT 0xA6 |
| #define ENOCEAN4_RORG_VLD 0xD2 |
| #define ENOCEAN4_RPT_LEVEL_1 0x01 |
| #define ENOCEAN4_RPT_LEVEL_2 0x02 |
| #define ENOCEAN4_RPT_OFF 0x00 |
| #define ENOCEAN4_RPT_ON_ALL 0x01 |
| #define ENOCEAN4_RPT_ON_FILTERED 0x02 |
| #define ENOCEAN4_SA_DEL_MAILBOX 0x0A |
| #define ENOCEAN4_SA_RD_LEARNEDCLIENTS 0x06 |
| #define ENOCEAN4_SA_RD_LEARNMODE 0x02 |
| #define ENOCEAN4_SA_RD_MAILBOX_STATUS 0x09 |
| #define ENOCEAN4_SA_WR_CLIENTLEARNRQ 0x04 |
| #define ENOCEAN4_SA_WR_LEARNCONFIRM 0x03 |
| #define ENOCEAN4_SA_WR_LEARNMODE 0x01 |
| #define ENOCEAN4_SA_WR_POSTMASTER 0x08 |
| #define ENOCEAN4_SA_WR_RECLAIMS 0x07 |
| #define ENOCEAN4_SA_WR_RESET 0x05 |
| #define ENOCEAN4_SYNC_BYTE 0x55 |
| #define ENOCEAN4_SYNC_BYTE_ERROR 0xFF |
| #define ENOCEAN4_UART_RX_NOT_READY 0x00 |