List of registers of Expand 10 Click driver.
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List of registers of Expand 10 Click driver.
◆ EXPAND10_REG_CONFIG_P0
#define EXPAND10_REG_CONFIG_P0 0x0C |
◆ EXPAND10_REG_CONFIG_P1
#define EXPAND10_REG_CONFIG_P1 0x0D |
◆ EXPAND10_REG_CONFIG_P2
#define EXPAND10_REG_CONFIG_P2 0x0E |
◆ EXPAND10_REG_INPUT_LAT_P0
#define EXPAND10_REG_INPUT_LAT_P0 0x48 |
◆ EXPAND10_REG_INPUT_LAT_P1
#define EXPAND10_REG_INPUT_LAT_P1 0x49 |
◆ EXPAND10_REG_INPUT_LAT_P2
#define EXPAND10_REG_INPUT_LAT_P2 0x4A |
◆ EXPAND10_REG_INPUT_P0
#define EXPAND10_REG_INPUT_P0 0x00 |
Expand 10 register list.
Specified register list of Expand 10 Click driver.
◆ EXPAND10_REG_INPUT_P1
#define EXPAND10_REG_INPUT_P1 0x01 |
◆ EXPAND10_REG_INPUT_P2
#define EXPAND10_REG_INPUT_P2 0x02 |
◆ EXPAND10_REG_INPUT_STATUS_P0
#define EXPAND10_REG_INPUT_STATUS_P0 0x6C |
◆ EXPAND10_REG_INPUT_STATUS_P1
#define EXPAND10_REG_INPUT_STATUS_P1 0x6D |
◆ EXPAND10_REG_INPUT_STATUS_P2
#define EXPAND10_REG_INPUT_STATUS_P2 0x6E |
◆ EXPAND10_REG_INT_CLEAR_P0
#define EXPAND10_REG_INT_CLEAR_P0 0x68 |
◆ EXPAND10_REG_INT_CLEAR_P1
#define EXPAND10_REG_INT_CLEAR_P1 0x69 |
◆ EXPAND10_REG_INT_CLEAR_P2
#define EXPAND10_REG_INT_CLEAR_P2 0x6A |
◆ EXPAND10_REG_INT_EDGE_P0A
#define EXPAND10_REG_INT_EDGE_P0A 0x60 |
◆ EXPAND10_REG_INT_EDGE_P0B
#define EXPAND10_REG_INT_EDGE_P0B 0x61 |
◆ EXPAND10_REG_INT_EDGE_P1A
#define EXPAND10_REG_INT_EDGE_P1A 0x62 |
◆ EXPAND10_REG_INT_EDGE_P1B
#define EXPAND10_REG_INT_EDGE_P1B 0x63 |
◆ EXPAND10_REG_INT_EDGE_P2A
#define EXPAND10_REG_INT_EDGE_P2A 0x64 |
◆ EXPAND10_REG_INT_EDGE_P2B
#define EXPAND10_REG_INT_EDGE_P2B 0x65 |
◆ EXPAND10_REG_INT_MASK_P0
#define EXPAND10_REG_INT_MASK_P0 0x54 |
◆ EXPAND10_REG_INT_MASK_P1
#define EXPAND10_REG_INT_MASK_P1 0x55 |
◆ EXPAND10_REG_INT_MASK_P2
#define EXPAND10_REG_INT_MASK_P2 0x56 |
◆ EXPAND10_REG_INT_STATUS_P0
#define EXPAND10_REG_INT_STATUS_P0 0x58 |
◆ EXPAND10_REG_INT_STATUS_P1
#define EXPAND10_REG_INT_STATUS_P1 0x59 |
◆ EXPAND10_REG_INT_STATUS_P2
#define EXPAND10_REG_INT_STATUS_P2 0x5A |
◆ EXPAND10_REG_OUTPUT_DRIVE_P0A
#define EXPAND10_REG_OUTPUT_DRIVE_P0A 0x40 |
◆ EXPAND10_REG_OUTPUT_DRIVE_P0B
#define EXPAND10_REG_OUTPUT_DRIVE_P0B 0x41 |
◆ EXPAND10_REG_OUTPUT_DRIVE_P1A
#define EXPAND10_REG_OUTPUT_DRIVE_P1A 0x42 |
◆ EXPAND10_REG_OUTPUT_DRIVE_P1B
#define EXPAND10_REG_OUTPUT_DRIVE_P1B 0x43 |
◆ EXPAND10_REG_OUTPUT_DRIVE_P2A
#define EXPAND10_REG_OUTPUT_DRIVE_P2A 0x44 |
◆ EXPAND10_REG_OUTPUT_DRIVE_P2B
#define EXPAND10_REG_OUTPUT_DRIVE_P2B 0x45 |
◆ EXPAND10_REG_OUTPUT_P0
#define EXPAND10_REG_OUTPUT_P0 0x04 |
◆ EXPAND10_REG_OUTPUT_P1
#define EXPAND10_REG_OUTPUT_P1 0x05 |
◆ EXPAND10_REG_OUTPUT_P2
#define EXPAND10_REG_OUTPUT_P2 0x06 |
◆ EXPAND10_REG_OUTPUT_PORT_CONFIG
#define EXPAND10_REG_OUTPUT_PORT_CONFIG 0x5C |
◆ EXPAND10_REG_PIN_OUTPUT_P0_CONFIG
#define EXPAND10_REG_PIN_OUTPUT_P0_CONFIG 0x70 |
◆ EXPAND10_REG_PIN_OUTPUT_P1_CONFIG
#define EXPAND10_REG_PIN_OUTPUT_P1_CONFIG 0x71 |
◆ EXPAND10_REG_PIN_OUTPUT_P2_CONFIG
#define EXPAND10_REG_PIN_OUTPUT_P2_CONFIG 0x72 |
◆ EXPAND10_REG_POLARITY_INV_P0
#define EXPAND10_REG_POLARITY_INV_P0 0x08 |
◆ EXPAND10_REG_POLARITY_INV_P1
#define EXPAND10_REG_POLARITY_INV_P1 0x09 |
◆ EXPAND10_REG_POLARITY_INV_P2
#define EXPAND10_REG_POLARITY_INV_P2 0x0A |
◆ EXPAND10_REG_PULL_ENABLE_P0
#define EXPAND10_REG_PULL_ENABLE_P0 0x4C |
◆ EXPAND10_REG_PULL_ENABLE_P1
#define EXPAND10_REG_PULL_ENABLE_P1 0x4D |
◆ EXPAND10_REG_PULL_ENABLE_P2
#define EXPAND10_REG_PULL_ENABLE_P2 0x4E |
◆ EXPAND10_REG_PULL_SELECTION_P0
#define EXPAND10_REG_PULL_SELECTION_P0 0x50 |
◆ EXPAND10_REG_PULL_SELECTION_P1
#define EXPAND10_REG_PULL_SELECTION_P1 0x51 |
◆ EXPAND10_REG_PULL_SELECTION_P2
#define EXPAND10_REG_PULL_SELECTION_P2 0x52 |
◆ EXPAND10_REG_SWITCH_DEBOUNCE_CNT
#define EXPAND10_REG_SWITCH_DEBOUNCE_CNT 0x76 |
◆ EXPAND10_REG_SWITCH_DEBOUNCE_EN_0
#define EXPAND10_REG_SWITCH_DEBOUNCE_EN_0 0x74 |
◆ EXPAND10_REG_SWITCH_DEBOUNCE_EN_1
#define EXPAND10_REG_SWITCH_DEBOUNCE_EN_1 0x75 |