Settings for registers of Hall Switch 3 Click driver. More...

Macros
#define	HALLSWITCH3_STATUS_OUT_B_CLEAR 0x00
	Hall Switch 3 status reporting of modes and selections bit descriptions.

#define	HALLSWITCH3_STATUS_OUT_B_ASSERT 0x01

#define	HALLSWITCH3_STATUS_RST_COMPLETE 0x00

#define	HALLSWITCH3_STATUS_RST_NOT_COMPLETE 0x02

#define	HALLSWITCH3_STATUS_OPMODE_SA 0x00

#define	HALLSWITCH3_STATUS_OPMODE_I2C 0x08

#define	HALLSWITCH3_STATUS_MDR_DATA_RDY 0x00

#define	HALLSWITCH3_STATUS_MDR_DATA_NO_RDY 0x20

#define	HALLSWITCH3_STATUS_MDO_DATA_OK 0x00

#define	HALLSWITCH3_STATUS_MDO_DATA_FAULT 0x40

#define	HALLSWITCH3_STATUS_VOUT_LOW 0x00

#define	HALLSWITCH3_STATUS_VOUT_HIGH 0x80

#define	HALLSWITCH3_CONTROL_SW_RESET 0x01
	Hall Switch 3 control of operations bit allocation.

#define	HALLSWITCH3_CONTROL_ONE_SHOT 0x04

#define	HALLSWITCH3_CONTROL_AUTO_STOP 0x00

#define	HALLSWITCH3_CONTROL_AUTO_START 0x08

#define	HALLSWITCH3_CONTROL_V_POL_ASSERT_H 0x00

#define	HALLSWITCH3_CONTROL_V_POL_ASSERT_L 0x20

#define	HALLSWITCH3_ASSERT_THOLD_DEFAULT 0x10
	Hall Switch 3 threshold bitmask.

#define	HALLSWITCH3_CLEAR_THOLD_DEFAULT 0x15

#define	HALLSWITCH3_THOLD_BITMASK 0x1F

#define	HALLSWITCH3_OUT_M_RES_RST 0x00
	Hall Switch 3 magnetic strength report bit description.

#define	HALLSWITCH3_OUT_M_RES_LOWEST 0x01

#define	HALLSWITCH3_OUT_M_RES_HIGHEST 0x1F

#define	HALLSWITCH3_USER_ODR_LSP 0x1F
	Hall Switch 3 output data rates bit description.

#define	HALLSWITCH3_USER_ODR_LSP 0x00
	Hall Switch 3 output data rates bit description.

#define	HALLSWITCH3_USER_ODR_LSP_X5 0x01

#define	HALLSWITCH3_USER_ODR_MSP 0x02

#define	HALLSWITCH3_USER_ODR_MSP_X5 0x03

#define	HALLSWITCH3_USER_ODR_HSP 0x04

#define	HALLSWITCH3_USER_ODR_HSP_X5 0x05

#define	HALLSWITCH3_USER_ODR_HSP_X10 0x06

#define	HALLSWITCH3_USER_ODR_CFG_ERR 0x07

#define	HALLSWITCH3_OUT_STATE_LOW 0x00
	Hall Switch 3 OUT pin states.

#define	HALLSWITCH3_OUT_STATE_HIGH 0x01

#define	HALLSWITCH3_WHO_AM_I 0x01
	Hall Switch 3 threshold bitmask.

#define	HALLSWITCH3_DEVICE_ADDRESS 0x60
	Hall Switch 3 device address setting.

Detailed Description

Settings for registers of Hall Switch 3 Click driver.

Macro Definition Documentation

◆ HALLSWITCH3_ASSERT_THOLD_DEFAULT

#define HALLSWITCH3_ASSERT_THOLD_DEFAULT 0x10

Hall Switch 3 threshold bitmask.

User selectable output threshold bitmask of Hall Switch 3 Click driver.

◆ HALLSWITCH3_CLEAR_THOLD_DEFAULT

#define HALLSWITCH3_CLEAR_THOLD_DEFAULT 0x15

◆ HALLSWITCH3_CONTROL_AUTO_START

#define HALLSWITCH3_CONTROL_AUTO_START 0x08

◆ HALLSWITCH3_CONTROL_AUTO_STOP

#define HALLSWITCH3_CONTROL_AUTO_STOP 0x00

◆ HALLSWITCH3_CONTROL_ONE_SHOT

#define HALLSWITCH3_CONTROL_ONE_SHOT 0x04

◆ HALLSWITCH3_CONTROL_SW_RESET

#define HALLSWITCH3_CONTROL_SW_RESET 0x01

Hall Switch 3 control of operations bit allocation.

Control of operations bit allocation of Hall Switch 3 Click driver.

◆ HALLSWITCH3_CONTROL_V_POL_ASSERT_H

#define HALLSWITCH3_CONTROL_V_POL_ASSERT_H 0x00

◆ HALLSWITCH3_CONTROL_V_POL_ASSERT_L

#define HALLSWITCH3_CONTROL_V_POL_ASSERT_L 0x20

◆ HALLSWITCH3_DEVICE_ADDRESS

#define HALLSWITCH3_DEVICE_ADDRESS 0x60

Hall Switch 3 device address setting.

Specified setting for device slave address selection of Hall Switch 3 Click driver.

◆ HALLSWITCH3_OUT_M_RES_HIGHEST

#define HALLSWITCH3_OUT_M_RES_HIGHEST 0x1F

◆ HALLSWITCH3_OUT_M_RES_LOWEST

#define HALLSWITCH3_OUT_M_RES_LOWEST 0x01

◆ HALLSWITCH3_OUT_M_RES_RST

#define HALLSWITCH3_OUT_M_RES_RST 0x00

Hall Switch 3 magnetic strength report bit description.

Magnetic strength report bit description of Hall Switch 3 Click driver.

◆ HALLSWITCH3_OUT_STATE_HIGH

#define HALLSWITCH3_OUT_STATE_HIGH 0x01

◆ HALLSWITCH3_OUT_STATE_LOW

#define HALLSWITCH3_OUT_STATE_LOW 0x00

Hall Switch 3 OUT pin states.

OUT pin states of Hall Switch 3 Click driver.

◆ HALLSWITCH3_STATUS_MDO_DATA_FAULT

#define HALLSWITCH3_STATUS_MDO_DATA_FAULT 0x40

◆ HALLSWITCH3_STATUS_MDO_DATA_OK

#define HALLSWITCH3_STATUS_MDO_DATA_OK 0x00

◆ HALLSWITCH3_STATUS_MDR_DATA_NO_RDY

#define HALLSWITCH3_STATUS_MDR_DATA_NO_RDY 0x20

◆ HALLSWITCH3_STATUS_MDR_DATA_RDY

#define HALLSWITCH3_STATUS_MDR_DATA_RDY 0x00

◆ HALLSWITCH3_STATUS_OPMODE_I2C

#define HALLSWITCH3_STATUS_OPMODE_I2C 0x08

◆ HALLSWITCH3_STATUS_OPMODE_SA

#define HALLSWITCH3_STATUS_OPMODE_SA 0x00

◆ HALLSWITCH3_STATUS_OUT_B_ASSERT

#define HALLSWITCH3_STATUS_OUT_B_ASSERT 0x01

◆ HALLSWITCH3_STATUS_OUT_B_CLEAR

#define HALLSWITCH3_STATUS_OUT_B_CLEAR 0x00

Hall Switch 3 status reporting of modes and selections bit descriptions.

Status reporting of modes and selections bit descriptions of Hall Switch 3 Click driver.

◆ HALLSWITCH3_STATUS_RST_COMPLETE

#define HALLSWITCH3_STATUS_RST_COMPLETE 0x00

◆ HALLSWITCH3_STATUS_RST_NOT_COMPLETE

#define HALLSWITCH3_STATUS_RST_NOT_COMPLETE 0x02

◆ HALLSWITCH3_STATUS_VOUT_HIGH

#define HALLSWITCH3_STATUS_VOUT_HIGH 0x80

◆ HALLSWITCH3_STATUS_VOUT_LOW

#define HALLSWITCH3_STATUS_VOUT_LOW 0x00

◆ HALLSWITCH3_THOLD_BITMASK

#define HALLSWITCH3_THOLD_BITMASK 0x1F

◆ HALLSWITCH3_USER_ODR_CFG_ERR

#define HALLSWITCH3_USER_ODR_CFG_ERR 0x07

◆ HALLSWITCH3_USER_ODR_HSP

#define HALLSWITCH3_USER_ODR_HSP 0x04

◆ HALLSWITCH3_USER_ODR_HSP_X10

#define HALLSWITCH3_USER_ODR_HSP_X10 0x06

◆ HALLSWITCH3_USER_ODR_HSP_X5

#define HALLSWITCH3_USER_ODR_HSP_X5 0x05

◆ HALLSWITCH3_USER_ODR_LSP [1/2]

#define HALLSWITCH3_USER_ODR_LSP 0x1F

Hall Switch 3 output data rates bit description.

User selectable sleep sample output data rates bit description of Hall Switch 3 Click driver.

◆ HALLSWITCH3_USER_ODR_LSP [2/2]

#define HALLSWITCH3_USER_ODR_LSP 0x00