H-Bridge 9 Registers Settings

Settings for registers of H-Bridge 9 Click driver. More...

Macros
#define	HBRIDGE9_SPI_CPHA_TEST   0x55
	H-Bridge 9 SPI CPHA test bits.
#define	HBRIDGE9_ODD_PARITY   0x01
	H-Bridge 9 ODD parity flag.
#define	HBRIDGE9_CR0_PWM_FREQ_10p240   0x0000
	H-Bridge 9 Control register 0 bits.
#define	HBRIDGE9_CR0_PWM_FREQ_12p288   0x2000
#define	HBRIDGE9_CR0_PWM_FREQ_14p336   0x4000
#define	HBRIDGE9_CR0_PWM_FREQ_16p384   0x6000
#define	HBRIDGE9_CR0_PWM_FREQ_18p432   0x8000
#define	HBRIDGE9_CR0_PWM_FREQ_20p480   0xA000
#define	HBRIDGE9_CR0_PWM_FREQ_22p528   0xC000
#define	HBRIDGE9_CR0_PWM_FREQ_24p576   0xE000
#define	HBRIDGE9_CR0_PWM_FREQ_MASK   0xE000
#define	HBRIDGE9_CR0_OUT6_POL_HIGH   0x1000
#define	HBRIDGE9_CR0_OUT6_POL_LOW   0x0040
#define	HBRIDGE9_CR0_OUT6_POL_MASK   0x1040
#define	HBRIDGE9_CR0_OUT5_POL_HIGH   0x0800
#define	HBRIDGE9_CR0_OUT5_POL_LOW   0x0020
#define	HBRIDGE9_CR0_OUT5_POL_MASK   0x0820
#define	HBRIDGE9_CR0_OUT4_POL_HIGH   0x0400
#define	HBRIDGE9_CR0_OUT4_POL_LOW   0x0010
#define	HBRIDGE9_CR0_OUT4_POL_MASK   0x0410
#define	HBRIDGE9_CR0_OUT3_POL_HIGH   0x0200
#define	HBRIDGE9_CR0_OUT3_POL_LOW   0x0008
#define	HBRIDGE9_CR0_OUT3_POL_MASK   0x0208
#define	HBRIDGE9_CR0_OUT2_POL_HIGH   0x0100
#define	HBRIDGE9_CR0_OUT2_POL_LOW   0x0004
#define	HBRIDGE9_CR0_OUT2_POL_MASK   0x0104
#define	HBRIDGE9_CR0_OUT1_POL_HIGH   0x0080
#define	HBRIDGE9_CR0_OUT1_POL_LOW   0x0002
#define	HBRIDGE9_CR0_OUT1_POL_MASK   0x0082
#define	HBRIDGE9_CR1_EX_OUT2_ON   0x8000
	H-Bridge 9 Control register 1 bits.
#define	HBRIDGE9_CR1_EX_OUT1_ON   0x4000
#define	HBRIDGE9_CR1_EX_OUT_MASK   0xC000
#define	HBRIDGE9_CR1_OUT6_ON   0x2000
#define	HBRIDGE9_CR1_OUT5_ON   0x1000
#define	HBRIDGE9_CR1_OUT4_ON   0x0800
#define	HBRIDGE9_CR1_OUT3_ON   0x0400
#define	HBRIDGE9_CR1_OUT2_ON   0x0200
#define	HBRIDGE9_CR1_OUT1_ON   0x0100
#define	HBRIDGE9_CR1_OUT_MASK   0x3F00
#define	HBRIDGE9_CR1_EMCY_NORMAL_MODE   0x0000
#define	HBRIDGE9_CR1_EMCY_EMERGENCY_MODE   0x0080
#define	HBRIDGE9_CR1_EMCY_MASK   0x00C0
#define	HBRIDGE9_CR1_EX_OUT2_POL_HIGH   0x0020
#define	HBRIDGE9_CR1_EX_OUT2_POL_LOW   0x0008
#define	HBRIDGE9_CR1_EX_OUT2_POL_MASK   0x0028
#define	HBRIDGE9_CR1_EX_OUT1_POL_HIGH   0x0010
#define	HBRIDGE9_CR1_EX_OUT1_POL_LOW   0x0004
#define	HBRIDGE9_CR1_EX_OUT1_POL_MASK   0x0014
#define	HBRIDGE9_CR1_OUT_ON   0x0002
#define	HBRIDGE9_CR2_DBN_EX2   0x8000
	H-Bridge 9 Control register 2 bits.
#define	HBRIDGE9_CR2_DBN_EX1   0x4000
#define	HBRIDGE9_CR2_DBN_EX_MASK   0xC000
#define	HBRIDGE9_CR2_DBN_6   0x2000
#define	HBRIDGE9_CR2_DBN_5   0x1000
#define	HBRIDGE9_CR2_DBN_4   0x0800
#define	HBRIDGE9_CR2_DBN_3   0x0400
#define	HBRIDGE9_CR2_DBN_2   0x0200
#define	HBRIDGE9_CR2_DBN_1   0x0100
#define	HBRIDGE9_CR2_DBN_MASK   0x3F00
#define	HBRIDGE9_CR2_ON_TIME_DUR_100MS   0x0000
#define	HBRIDGE9_CR2_ON_TIME_DUR_120MS   0x0008
#define	HBRIDGE9_CR2_ON_TIME_DUR_140MS   0x0010
#define	HBRIDGE9_CR2_ON_TIME_DUR_160MS   0x0018
#define	HBRIDGE9_CR2_ON_TIME_DUR_180MS   0x0020
#define	HBRIDGE9_CR2_ON_TIME_DUR_200MS   0x0028
#define	HBRIDGE9_CR2_ON_TIME_DUR_220MS   0x0030
#define	HBRIDGE9_CR2_ON_TIME_DUR_240MS   0x0038
#define	HBRIDGE9_CR2_ON_TIME_DUR_260MS   0x0040
#define	HBRIDGE9_CR2_ON_TIME_DUR_280MS   0x0048
#define	HBRIDGE9_CR2_ON_TIME_DUR_300MS   0x0050
#define	HBRIDGE9_CR2_ON_TIME_DUR_320MS   0x0058
#define	HBRIDGE9_CR2_ON_TIME_DUR_340MS   0x0060
#define	HBRIDGE9_CR2_ON_TIME_DUR_360MS   0x0068
#define	HBRIDGE9_CR2_ON_TIME_DUR_380MS   0x0070
#define	HBRIDGE9_CR2_ON_TIME_DUR_400MS   0x0078
#define	HBRIDGE9_CR2_ON_TIME_DUR_440MS   0x0080
#define	HBRIDGE9_CR2_ON_TIME_DUR_480MS   0x0088
#define	HBRIDGE9_CR2_ON_TIME_DUR_520MS   0x0090
#define	HBRIDGE9_CR2_ON_TIME_DUR_560MS   0x0098
#define	HBRIDGE9_CR2_ON_TIME_DUR_600MS   0x00A0
#define	HBRIDGE9_CR2_ON_TIME_DUR_640MS   0x00A8
#define	HBRIDGE9_CR2_ON_TIME_DUR_680MS   0x00B0
#define	HBRIDGE9_CR2_ON_TIME_DUR_720MS   0x00B8
#define	HBRIDGE9_CR2_ON_TIME_DUR_760MS   0x00C0
#define	HBRIDGE9_CR2_ON_TIME_DUR_800MS   0x00C8
#define	HBRIDGE9_CR2_ON_TIME_DUR_840MS   0x00D0
#define	HBRIDGE9_CR2_ON_TIME_DUR_880MS   0x00D8
#define	HBRIDGE9_CR2_ON_TIME_DUR_920MS   0x00E0
#define	HBRIDGE9_CR2_ON_TIME_DUR_960MS   0x00E8
#define	HBRIDGE9_CR2_ON_TIME_DUR_1000MS   0x00F0
#define	HBRIDGE9_CR2_ON_TIME_DUR_1040MS   0x00F8
#define	HBRIDGE9_CR2_ON_TIME_DUR_MASK   0x00F8
#define	HBRIDGE9_CR2_BRAKING_DUR_0MS   0x0000
#define	HBRIDGE9_CR2_BRAKING_DUR_100MS   0x0002
#define	HBRIDGE9_CR2_BRAKING_DUR_200MS   0x0004
#define	HBRIDGE9_CR2_BRAKING_DUR_100MS_IND   0x0006
#define	HBRIDGE9_CR2_BRAKING_DUR_MASK   0x0006
#define	HBRIDGE9_CR3_GFI   0x0080
	H-Bridge 9 Control register 3 bits.
#define	HBRIDGE9_CR3_TSD_ACT   0x0040
#define	HBRIDGE9_CR3_DITHN   0x0020
#define	HBRIDGE9_CR3_NO_GROUP   0x0000
#define	HBRIDGE9_CR3_GROUP_1_2   0x0002
#define	HBRIDGE9_CR3_GROUP_1_3   0x0004
#define	HBRIDGE9_CR3_GROUP_1_2_3   0x0006
#define	HBRIDGE9_CR3_GROUP_4_5   0x0008
#define	HBRIDGE9_CR3_GROUP_4_6   0x0010
#define	HBRIDGE9_CR3_GROUP_4_5_6   0x0018
#define	HBRIDGE9_CR3_GROUP_MASK   0x001E
#define	HBRIDGE9_CR4_OCP1_SHIFT_BITS   0x0001
	H-Bridge 9 Control register 4 and 5 bits.
#define	HBRIDGE9_CR4_OCP2_SHIFT_BITS   0x0006
#define	HBRIDGE9_CR4_OCP3_SHIFT_BITS   0x000B
#define	HBRIDGE9_CR5_OCP4_SHIFT_BITS   0x0001
#define	HBRIDGE9_CR5_OCP5_SHIFT_BITS   0x0006
#define	HBRIDGE9_CR5_OCP6_SHIFT_BITS   0x000B
#define	HBRIDGE9_DUTY_CYCLE_6p25   0x0000
#define	HBRIDGE9_DUTY_CYCLE_12p5   0x0001
#define	HBRIDGE9_DUTY_CYCLE_18p75   0x0002
#define	HBRIDGE9_DUTY_CYCLE_25   0x0003
#define	HBRIDGE9_DUTY_CYCLE_31p25   0x0004
#define	HBRIDGE9_DUTY_CYCLE_37p5   0x0005
#define	HBRIDGE9_DUTY_CYCLE_43p75   0x0006
#define	HBRIDGE9_DUTY_CYCLE_50   0x0007
#define	HBRIDGE9_DUTY_CYCLE_56p25   0x0008
#define	HBRIDGE9_DUTY_CYCLE_62p5   0x0009
#define	HBRIDGE9_DUTY_CYCLE_68p75   0x000A
#define	HBRIDGE9_DUTY_CYCLE_75   0x000B
#define	HBRIDGE9_DUTY_CYCLE_81p25   0x000C
#define	HBRIDGE9_DUTY_CYCLE_87p5   0x000D
#define	HBRIDGE9_DUTY_CYCLE_93p75   0x000E
#define	HBRIDGE9_DUTY_CYCLE_100   0x000F
#define	HBRIDGE9_DUTY_CYCLE_MASK   0x001F
#define	HBRIDGE9_CURRENT_1A   0x0010
#define	HBRIDGE9_CURRENT_1p2A   0x0011
#define	HBRIDGE9_CURRENT_1p4A   0x0012
#define	HBRIDGE9_CURRENT_1p6A   0x0013
#define	HBRIDGE9_CURRENT_1p8A   0x0014
#define	HBRIDGE9_CURRENT_2A   0x0015
#define	HBRIDGE9_CURRENT_2p2A   0x0016
#define	HBRIDGE9_CURRENT_2p4A   0x0017
#define	HBRIDGE9_CURRENT_2p6A   0x0018
#define	HBRIDGE9_CURRENT_2p8A   0x0019
#define	HBRIDGE9_CURRENT_3A   0x001A
#define	HBRIDGE9_CURRENT_3p2A   0x001B
#define	HBRIDGE9_CURRENT_3p4A   0x001C
#define	HBRIDGE9_CURRENT_3p6A   0x001D
#define	HBRIDGE9_CURRENT_3p8A   0x001E
#define	HBRIDGE9_CURRENT_4A   0x001F
#define	HBRIDGE9_CURRENT_MASK   0x001F
#define	HBRIDGE9_CR6_HBDCL2   0x8000
	H-Bridge 9 Control register 6 bits.
#define	HBRIDGE9_CR6_HBDCH2   0x4000
#define	HBRIDGE9_CR6_HBDC2_MASK   0xC000
#define	HBRIDGE9_CR6_STBY1   0x2000
#define	HBRIDGE9_CR6_EXT2_VDT_1US   0x0000
#define	HBRIDGE9_CR6_EXT2_VDT_2US   0x0800
#define	HBRIDGE9_CR6_EXT2_VDT_3US   0x1000
#define	HBRIDGE9_CR6_EXT2_VDT_4US   0x1800
#define	HBRIDGE9_CR6_EXT2_VDT_MASK   0x1800
#define	HBRIDGE9_CR6_EXT1_VDT_1US   0x0000
#define	HBRIDGE9_CR6_EXT1_VDT_2US   0x0200
#define	HBRIDGE9_CR6_EXT1_VDT_3US   0x0400
#define	HBRIDGE9_CR6_EXT1_VDT_4US   0x0600
#define	HBRIDGE9_CR6_EXT1_VDT_MASK   0x0600
#define	HBRIDGE9_CR6_EXT2_VDS_OFF   0x0000
#define	HBRIDGE9_CR6_EXT2_VDS_0p25V   0x0100
#define	HBRIDGE9_CR6_EXT2_VDS_0p5V   0x0120
#define	HBRIDGE9_CR6_EXT2_VDS_0p75V   0x0140
#define	HBRIDGE9_CR6_EXT2_VDS_1V   0x0160
#define	HBRIDGE9_CR6_EXT2_VDS_1p25V   0x0180
#define	HBRIDGE9_CR6_EXT2_VDS_1p5V   0x01A0
#define	HBRIDGE9_CR6_EXT2_VDS_1p75V   0x01C0
#define	HBRIDGE9_CR6_EXT2_VDS_2V   0x01E0
#define	HBRIDGE9_CR6_EXT2_VDS_MASK   0x01E0
#define	HBRIDGE9_CR6_EXT1_VDS_OFF   0x0000
#define	HBRIDGE9_CR6_EXT1_VDS_0p25V   0x0010
#define	HBRIDGE9_CR6_EXT1_VDS_0p5V   0x0012
#define	HBRIDGE9_CR6_EXT1_VDS_0p75V   0x0014
#define	HBRIDGE9_CR6_EXT1_VDS_1V   0x0016
#define	HBRIDGE9_CR6_EXT1_VDS_1p25V   0x0018
#define	HBRIDGE9_CR6_EXT1_VDS_1p5V   0x001A
#define	HBRIDGE9_CR6_EXT1_VDS_1p75V   0x001C
#define	HBRIDGE9_CR6_EXT1_VDS_2V   0x001E
#define	HBRIDGE9_CR6_EXT1_VDS_MASK   0x001E
#define	HBRIDGE9_CR7_HBDCL1   0x8000
	H-Bridge 9 Control register 7 bits.
#define	HBRIDGE9_CR7_HBDCH1   0x4000
#define	HBRIDGE9_CR7_HBDC1_MASK   0xC000
#define	HBRIDGE9_CR7_STBY2   0x2000
#define	HBRIDGE9_CR7_ODCL6   0x1000
#define	HBRIDGE9_CR7_ODCH6   0x0800
#define	HBRIDGE9_CR7_ODC6_MASK   0x1800
#define	HBRIDGE9_CR7_ODCL5   0x0400
#define	HBRIDGE9_CR7_ODCH5   0x0200
#define	HBRIDGE9_CR7_ODC5_MASK   0x0600
#define	HBRIDGE9_CR7_ODCL4   0x0100
#define	HBRIDGE9_CR7_ODCH4   0x0080
#define	HBRIDGE9_CR7_ODC4_MASK   0x0180
#define	HBRIDGE9_CR7_ODCL3   0x0040
#define	HBRIDGE9_CR7_ODCH3   0x0020
#define	HBRIDGE9_CR7_ODC3_MASK   0x0060
#define	HBRIDGE9_CR7_ODCL2   0x0010
#define	HBRIDGE9_CR7_ODCH2   0x0008
#define	HBRIDGE9_CR7_ODC2_MASK   0x0018
#define	HBRIDGE9_CR7_ODCL1   0x0004
#define	HBRIDGE9_CR7_ODCH1   0x0002
#define	HBRIDGE9_CR7_ODC1_MASK   0x0006
#define	HBRIDGE9_CR8_KI_GAIN_1_OVER_128   0x0000
	H-Bridge 9 Control register 8 bits.
#define	HBRIDGE9_CR8_KI_GAIN_1_OVER_64   0x0010
#define	HBRIDGE9_CR8_KI_GAIN_1_OVER_32   0x0020
#define	HBRIDGE9_CR8_KI_GAIN_1_OVER_16   0x0030
#define	HBRIDGE9_CR8_KI_GAIN_1_OVER_8   0x0040
#define	HBRIDGE9_CR8_KI_GAIN_1_OVER_4   0x0050
#define	HBRIDGE9_CR8_KI_GAIN_1_OVER_2   0x0060
#define	HBRIDGE9_CR8_KI_GAIN_1   0x0070
#define	HBRIDGE9_CR8_KI_GAIN_MASK   0x0070
#define	HBRIDGE9_CR8_KP_GAIN_2   0x0000
#define	HBRIDGE9_CR8_KP_GAIN_4   0x0001
#define	HBRIDGE9_CR8_KP_GAIN_8   0x0002
#define	HBRIDGE9_CR8_KP_GAIN_16   0x0003
#define	HBRIDGE9_CR8_KP_GAIN_32   0x0004
#define	HBRIDGE9_CR8_KP_GAIN_64   0x0005
#define	HBRIDGE9_CR8_KP_GAIN_128   0x0006
#define	HBRIDGE9_CR8_KP_GAIN_256   0x0007
#define	HBRIDGE9_CR8_KP_GAIN_MASK   0x0007
#define	HBRIDGE9_SET_DATA_SAMPLE_EDGE   SET_SPI_DATA_SAMPLE_EDGE
	Data sample selection.
#define	HBRIDGE9_SET_DATA_SAMPLE_MIDDLE   SET_SPI_DATA_SAMPLE_MIDDLE

Detailed Description

Settings for registers of H-Bridge 9 Click driver.

Macro Definition Documentation

HBRIDGE9_CR0_OUT1_POL_HIGH

#define HBRIDGE9_CR0_OUT1_POL_HIGH   0x0080

HBRIDGE9_CR0_OUT1_POL_LOW

#define HBRIDGE9_CR0_OUT1_POL_LOW   0x0002

HBRIDGE9_CR0_OUT1_POL_MASK

#define HBRIDGE9_CR0_OUT1_POL_MASK   0x0082

HBRIDGE9_CR0_OUT2_POL_HIGH

#define HBRIDGE9_CR0_OUT2_POL_HIGH   0x0100

HBRIDGE9_CR0_OUT2_POL_LOW

#define HBRIDGE9_CR0_OUT2_POL_LOW   0x0004

HBRIDGE9_CR0_OUT2_POL_MASK

#define HBRIDGE9_CR0_OUT2_POL_MASK   0x0104

HBRIDGE9_CR0_OUT3_POL_HIGH

#define HBRIDGE9_CR0_OUT3_POL_HIGH   0x0200

HBRIDGE9_CR0_OUT3_POL_LOW

#define HBRIDGE9_CR0_OUT3_POL_LOW   0x0008

HBRIDGE9_CR0_OUT3_POL_MASK

#define HBRIDGE9_CR0_OUT3_POL_MASK   0x0208

HBRIDGE9_CR0_OUT4_POL_HIGH

#define HBRIDGE9_CR0_OUT4_POL_HIGH   0x0400

HBRIDGE9_CR0_OUT4_POL_LOW

#define HBRIDGE9_CR0_OUT4_POL_LOW   0x0010

HBRIDGE9_CR0_OUT4_POL_MASK

#define HBRIDGE9_CR0_OUT4_POL_MASK   0x0410

HBRIDGE9_CR0_OUT5_POL_HIGH

#define HBRIDGE9_CR0_OUT5_POL_HIGH   0x0800

HBRIDGE9_CR0_OUT5_POL_LOW

#define HBRIDGE9_CR0_OUT5_POL_LOW   0x0020

HBRIDGE9_CR0_OUT5_POL_MASK

#define HBRIDGE9_CR0_OUT5_POL_MASK   0x0820

HBRIDGE9_CR0_OUT6_POL_HIGH

#define HBRIDGE9_CR0_OUT6_POL_HIGH   0x1000

HBRIDGE9_CR0_OUT6_POL_LOW

#define HBRIDGE9_CR0_OUT6_POL_LOW   0x0040

HBRIDGE9_CR0_OUT6_POL_MASK

#define HBRIDGE9_CR0_OUT6_POL_MASK   0x1040

HBRIDGE9_CR0_PWM_FREQ_10p240

#define HBRIDGE9_CR0_PWM_FREQ_10p240   0x0000

H-Bridge 9 Control register 0 bits.

Specified bits for Control register 0 of H-Bridge 9 Click driver.

HBRIDGE9_CR0_PWM_FREQ_12p288

#define HBRIDGE9_CR0_PWM_FREQ_12p288   0x2000

HBRIDGE9_CR0_PWM_FREQ_14p336

#define HBRIDGE9_CR0_PWM_FREQ_14p336   0x4000

HBRIDGE9_CR0_PWM_FREQ_16p384

#define HBRIDGE9_CR0_PWM_FREQ_16p384   0x6000

HBRIDGE9_CR0_PWM_FREQ_18p432

#define HBRIDGE9_CR0_PWM_FREQ_18p432   0x8000

HBRIDGE9_CR0_PWM_FREQ_20p480

#define HBRIDGE9_CR0_PWM_FREQ_20p480   0xA000

HBRIDGE9_CR0_PWM_FREQ_22p528

#define HBRIDGE9_CR0_PWM_FREQ_22p528   0xC000

HBRIDGE9_CR0_PWM_FREQ_24p576

#define HBRIDGE9_CR0_PWM_FREQ_24p576   0xE000

HBRIDGE9_CR0_PWM_FREQ_MASK

#define HBRIDGE9_CR0_PWM_FREQ_MASK   0xE000

HBRIDGE9_CR1_EMCY_EMERGENCY_MODE

#define HBRIDGE9_CR1_EMCY_EMERGENCY_MODE   0x0080

HBRIDGE9_CR1_EMCY_MASK

#define HBRIDGE9_CR1_EMCY_MASK   0x00C0

HBRIDGE9_CR1_EMCY_NORMAL_MODE

#define HBRIDGE9_CR1_EMCY_NORMAL_MODE   0x0000

HBRIDGE9_CR1_EX_OUT1_ON

#define HBRIDGE9_CR1_EX_OUT1_ON   0x4000

HBRIDGE9_CR1_EX_OUT1_POL_HIGH

#define HBRIDGE9_CR1_EX_OUT1_POL_HIGH   0x0010

HBRIDGE9_CR1_EX_OUT1_POL_LOW

#define HBRIDGE9_CR1_EX_OUT1_POL_LOW   0x0004

HBRIDGE9_CR1_EX_OUT1_POL_MASK

#define HBRIDGE9_CR1_EX_OUT1_POL_MASK   0x0014

HBRIDGE9_CR1_EX_OUT2_ON

#define HBRIDGE9_CR1_EX_OUT2_ON   0x8000

H-Bridge 9 Control register 1 bits.

Specified bits for Control register 1 of H-Bridge 9 Click driver.

HBRIDGE9_CR1_EX_OUT2_POL_HIGH

#define HBRIDGE9_CR1_EX_OUT2_POL_HIGH   0x0020

HBRIDGE9_CR1_EX_OUT2_POL_LOW

#define HBRIDGE9_CR1_EX_OUT2_POL_LOW   0x0008

HBRIDGE9_CR1_EX_OUT2_POL_MASK

#define HBRIDGE9_CR1_EX_OUT2_POL_MASK   0x0028

HBRIDGE9_CR1_EX_OUT_MASK

#define HBRIDGE9_CR1_EX_OUT_MASK   0xC000

HBRIDGE9_CR1_OUT1_ON

#define HBRIDGE9_CR1_OUT1_ON   0x0100

HBRIDGE9_CR1_OUT2_ON

#define HBRIDGE9_CR1_OUT2_ON   0x0200

HBRIDGE9_CR1_OUT3_ON

#define HBRIDGE9_CR1_OUT3_ON   0x0400

HBRIDGE9_CR1_OUT4_ON

#define HBRIDGE9_CR1_OUT4_ON   0x0800

HBRIDGE9_CR1_OUT5_ON

#define HBRIDGE9_CR1_OUT5_ON   0x1000

HBRIDGE9_CR1_OUT6_ON

#define HBRIDGE9_CR1_OUT6_ON   0x2000

HBRIDGE9_CR1_OUT_MASK

#define HBRIDGE9_CR1_OUT_MASK   0x3F00

HBRIDGE9_CR1_OUT_ON

#define HBRIDGE9_CR1_OUT_ON   0x0002

HBRIDGE9_CR2_BRAKING_DUR_0MS

#define HBRIDGE9_CR2_BRAKING_DUR_0MS   0x0000

HBRIDGE9_CR2_BRAKING_DUR_100MS

#define HBRIDGE9_CR2_BRAKING_DUR_100MS   0x0002

HBRIDGE9_CR2_BRAKING_DUR_100MS_IND

#define HBRIDGE9_CR2_BRAKING_DUR_100MS_IND   0x0006

HBRIDGE9_CR2_BRAKING_DUR_200MS

#define HBRIDGE9_CR2_BRAKING_DUR_200MS   0x0004

HBRIDGE9_CR2_BRAKING_DUR_MASK

#define HBRIDGE9_CR2_BRAKING_DUR_MASK   0x0006

HBRIDGE9_CR2_DBN_1

#define HBRIDGE9_CR2_DBN_1   0x0100

HBRIDGE9_CR2_DBN_2

#define HBRIDGE9_CR2_DBN_2   0x0200

HBRIDGE9_CR2_DBN_3

#define HBRIDGE9_CR2_DBN_3   0x0400

HBRIDGE9_CR2_DBN_4

#define HBRIDGE9_CR2_DBN_4   0x0800

HBRIDGE9_CR2_DBN_5

#define HBRIDGE9_CR2_DBN_5   0x1000

HBRIDGE9_CR2_DBN_6

#define HBRIDGE9_CR2_DBN_6   0x2000

HBRIDGE9_CR2_DBN_EX1

#define HBRIDGE9_CR2_DBN_EX1   0x4000

HBRIDGE9_CR2_DBN_EX2

#define HBRIDGE9_CR2_DBN_EX2   0x8000

H-Bridge 9 Control register 2 bits.

Specified bits for Control register 2 of H-Bridge 9 Click driver.

HBRIDGE9_CR2_DBN_EX_MASK

#define HBRIDGE9_CR2_DBN_EX_MASK   0xC000

HBRIDGE9_CR2_DBN_MASK

#define HBRIDGE9_CR2_DBN_MASK   0x3F00

HBRIDGE9_CR2_ON_TIME_DUR_1000MS

#define HBRIDGE9_CR2_ON_TIME_DUR_1000MS   0x00F0

HBRIDGE9_CR2_ON_TIME_DUR_100MS

#define HBRIDGE9_CR2_ON_TIME_DUR_100MS   0x0000

HBRIDGE9_CR2_ON_TIME_DUR_1040MS

#define HBRIDGE9_CR2_ON_TIME_DUR_1040MS   0x00F8

HBRIDGE9_CR2_ON_TIME_DUR_120MS

#define HBRIDGE9_CR2_ON_TIME_DUR_120MS   0x0008

HBRIDGE9_CR2_ON_TIME_DUR_140MS

#define HBRIDGE9_CR2_ON_TIME_DUR_140MS   0x0010

HBRIDGE9_CR2_ON_TIME_DUR_160MS

#define HBRIDGE9_CR2_ON_TIME_DUR_160MS   0x0018

HBRIDGE9_CR2_ON_TIME_DUR_180MS

#define HBRIDGE9_CR2_ON_TIME_DUR_180MS   0x0020

HBRIDGE9_CR2_ON_TIME_DUR_200MS

#define HBRIDGE9_CR2_ON_TIME_DUR_200MS   0x0028

HBRIDGE9_CR2_ON_TIME_DUR_220MS

#define HBRIDGE9_CR2_ON_TIME_DUR_220MS   0x0030

HBRIDGE9_CR2_ON_TIME_DUR_240MS

#define HBRIDGE9_CR2_ON_TIME_DUR_240MS   0x0038

HBRIDGE9_CR2_ON_TIME_DUR_260MS

#define HBRIDGE9_CR2_ON_TIME_DUR_260MS   0x0040

HBRIDGE9_CR2_ON_TIME_DUR_280MS

#define HBRIDGE9_CR2_ON_TIME_DUR_280MS   0x0048

HBRIDGE9_CR2_ON_TIME_DUR_300MS

#define HBRIDGE9_CR2_ON_TIME_DUR_300MS   0x0050

HBRIDGE9_CR2_ON_TIME_DUR_320MS

#define HBRIDGE9_CR2_ON_TIME_DUR_320MS   0x0058

HBRIDGE9_CR2_ON_TIME_DUR_340MS

#define HBRIDGE9_CR2_ON_TIME_DUR_340MS   0x0060

HBRIDGE9_CR2_ON_TIME_DUR_360MS

#define HBRIDGE9_CR2_ON_TIME_DUR_360MS   0x0068

HBRIDGE9_CR2_ON_TIME_DUR_380MS

#define HBRIDGE9_CR2_ON_TIME_DUR_380MS   0x0070

HBRIDGE9_CR2_ON_TIME_DUR_400MS

#define HBRIDGE9_CR2_ON_TIME_DUR_400MS   0x0078

HBRIDGE9_CR2_ON_TIME_DUR_440MS

#define HBRIDGE9_CR2_ON_TIME_DUR_440MS   0x0080

HBRIDGE9_CR2_ON_TIME_DUR_480MS

#define HBRIDGE9_CR2_ON_TIME_DUR_480MS   0x0088

HBRIDGE9_CR2_ON_TIME_DUR_520MS

#define HBRIDGE9_CR2_ON_TIME_DUR_520MS   0x0090

HBRIDGE9_CR2_ON_TIME_DUR_560MS

#define HBRIDGE9_CR2_ON_TIME_DUR_560MS   0x0098

HBRIDGE9_CR2_ON_TIME_DUR_600MS

#define HBRIDGE9_CR2_ON_TIME_DUR_600MS   0x00A0

HBRIDGE9_CR2_ON_TIME_DUR_640MS

#define HBRIDGE9_CR2_ON_TIME_DUR_640MS   0x00A8

HBRIDGE9_CR2_ON_TIME_DUR_680MS

#define HBRIDGE9_CR2_ON_TIME_DUR_680MS   0x00B0

HBRIDGE9_CR2_ON_TIME_DUR_720MS

#define HBRIDGE9_CR2_ON_TIME_DUR_720MS   0x00B8

HBRIDGE9_CR2_ON_TIME_DUR_760MS

#define HBRIDGE9_CR2_ON_TIME_DUR_760MS   0x00C0

HBRIDGE9_CR2_ON_TIME_DUR_800MS

#define HBRIDGE9_CR2_ON_TIME_DUR_800MS   0x00C8

HBRIDGE9_CR2_ON_TIME_DUR_840MS

#define HBRIDGE9_CR2_ON_TIME_DUR_840MS   0x00D0

HBRIDGE9_CR2_ON_TIME_DUR_880MS

#define HBRIDGE9_CR2_ON_TIME_DUR_880MS   0x00D8

HBRIDGE9_CR2_ON_TIME_DUR_920MS

#define HBRIDGE9_CR2_ON_TIME_DUR_920MS   0x00E0

HBRIDGE9_CR2_ON_TIME_DUR_960MS

#define HBRIDGE9_CR2_ON_TIME_DUR_960MS   0x00E8

HBRIDGE9_CR2_ON_TIME_DUR_MASK

#define HBRIDGE9_CR2_ON_TIME_DUR_MASK   0x00F8

HBRIDGE9_CR3_DITHN

#define HBRIDGE9_CR3_DITHN   0x0020

HBRIDGE9_CR3_GFI

#define HBRIDGE9_CR3_GFI   0x0080

H-Bridge 9 Control register 3 bits.

Specified bits for Control register 3 of H-Bridge 9 Click driver.

HBRIDGE9_CR3_GROUP_1_2

#define HBRIDGE9_CR3_GROUP_1_2   0x0002

HBRIDGE9_CR3_GROUP_1_2_3

#define HBRIDGE9_CR3_GROUP_1_2_3   0x0006

HBRIDGE9_CR3_GROUP_1_3

#define HBRIDGE9_CR3_GROUP_1_3   0x0004

HBRIDGE9_CR3_GROUP_4_5

#define HBRIDGE9_CR3_GROUP_4_5   0x0008

HBRIDGE9_CR3_GROUP_4_5_6

#define HBRIDGE9_CR3_GROUP_4_5_6   0x0018

HBRIDGE9_CR3_GROUP_4_6

#define HBRIDGE9_CR3_GROUP_4_6   0x0010

HBRIDGE9_CR3_GROUP_MASK

#define HBRIDGE9_CR3_GROUP_MASK   0x001E

HBRIDGE9_CR3_NO_GROUP

#define HBRIDGE9_CR3_NO_GROUP   0x0000

HBRIDGE9_CR3_TSD_ACT

#define HBRIDGE9_CR3_TSD_ACT   0x0040

HBRIDGE9_CR4_OCP1_SHIFT_BITS

#define HBRIDGE9_CR4_OCP1_SHIFT_BITS   0x0001

H-Bridge 9 Control register 4 and 5 bits.

Specified bits for Control register 4 and 5 of H-Bridge 9 Click driver.

HBRIDGE9_CR4_OCP2_SHIFT_BITS

#define HBRIDGE9_CR4_OCP2_SHIFT_BITS   0x0006

HBRIDGE9_CR4_OCP3_SHIFT_BITS

#define HBRIDGE9_CR4_OCP3_SHIFT_BITS   0x000B

HBRIDGE9_CR5_OCP4_SHIFT_BITS

#define HBRIDGE9_CR5_OCP4_SHIFT_BITS   0x0001

HBRIDGE9_CR5_OCP5_SHIFT_BITS

#define HBRIDGE9_CR5_OCP5_SHIFT_BITS   0x0006

HBRIDGE9_CR5_OCP6_SHIFT_BITS

#define HBRIDGE9_CR5_OCP6_SHIFT_BITS   0x000B

HBRIDGE9_CR6_EXT1_VDS_0p25V

#define HBRIDGE9_CR6_EXT1_VDS_0p25V   0x0010

HBRIDGE9_CR6_EXT1_VDS_0p5V

#define HBRIDGE9_CR6_EXT1_VDS_0p5V   0x0012

HBRIDGE9_CR6_EXT1_VDS_0p75V

#define HBRIDGE9_CR6_EXT1_VDS_0p75V   0x0014

HBRIDGE9_CR6_EXT1_VDS_1p25V

#define HBRIDGE9_CR6_EXT1_VDS_1p25V   0x0018

HBRIDGE9_CR6_EXT1_VDS_1p5V

#define HBRIDGE9_CR6_EXT1_VDS_1p5V   0x001A

HBRIDGE9_CR6_EXT1_VDS_1p75V

#define HBRIDGE9_CR6_EXT1_VDS_1p75V   0x001C

HBRIDGE9_CR6_EXT1_VDS_1V

#define HBRIDGE9_CR6_EXT1_VDS_1V   0x0016

HBRIDGE9_CR6_EXT1_VDS_2V

#define HBRIDGE9_CR6_EXT1_VDS_2V   0x001E

HBRIDGE9_CR6_EXT1_VDS_MASK

#define HBRIDGE9_CR6_EXT1_VDS_MASK   0x001E

HBRIDGE9_CR6_EXT1_VDS_OFF

#define HBRIDGE9_CR6_EXT1_VDS_OFF   0x0000

HBRIDGE9_CR6_EXT1_VDT_1US

#define HBRIDGE9_CR6_EXT1_VDT_1US   0x0000

HBRIDGE9_CR6_EXT1_VDT_2US

#define HBRIDGE9_CR6_EXT1_VDT_2US   0x0200

HBRIDGE9_CR6_EXT1_VDT_3US

#define HBRIDGE9_CR6_EXT1_VDT_3US   0x0400

HBRIDGE9_CR6_EXT1_VDT_4US

#define HBRIDGE9_CR6_EXT1_VDT_4US   0x0600

HBRIDGE9_CR6_EXT1_VDT_MASK

#define HBRIDGE9_CR6_EXT1_VDT_MASK   0x0600

HBRIDGE9_CR6_EXT2_VDS_0p25V

#define HBRIDGE9_CR6_EXT2_VDS_0p25V   0x0100

HBRIDGE9_CR6_EXT2_VDS_0p5V

#define HBRIDGE9_CR6_EXT2_VDS_0p5V   0x0120

HBRIDGE9_CR6_EXT2_VDS_0p75V

#define HBRIDGE9_CR6_EXT2_VDS_0p75V   0x0140

HBRIDGE9_CR6_EXT2_VDS_1p25V

#define HBRIDGE9_CR6_EXT2_VDS_1p25V   0x0180

HBRIDGE9_CR6_EXT2_VDS_1p5V

#define HBRIDGE9_CR6_EXT2_VDS_1p5V   0x01A0

HBRIDGE9_CR6_EXT2_VDS_1p75V

#define HBRIDGE9_CR6_EXT2_VDS_1p75V   0x01C0

HBRIDGE9_CR6_EXT2_VDS_1V

#define HBRIDGE9_CR6_EXT2_VDS_1V   0x0160

HBRIDGE9_CR6_EXT2_VDS_2V

#define HBRIDGE9_CR6_EXT2_VDS_2V   0x01E0

HBRIDGE9_CR6_EXT2_VDS_MASK

#define HBRIDGE9_CR6_EXT2_VDS_MASK   0x01E0

HBRIDGE9_CR6_EXT2_VDS_OFF

#define HBRIDGE9_CR6_EXT2_VDS_OFF   0x0000

HBRIDGE9_CR6_EXT2_VDT_1US

#define HBRIDGE9_CR6_EXT2_VDT_1US   0x0000

HBRIDGE9_CR6_EXT2_VDT_2US

#define HBRIDGE9_CR6_EXT2_VDT_2US   0x0800

HBRIDGE9_CR6_EXT2_VDT_3US

#define HBRIDGE9_CR6_EXT2_VDT_3US   0x1000

HBRIDGE9_CR6_EXT2_VDT_4US

#define HBRIDGE9_CR6_EXT2_VDT_4US   0x1800

HBRIDGE9_CR6_EXT2_VDT_MASK

#define HBRIDGE9_CR6_EXT2_VDT_MASK   0x1800

HBRIDGE9_CR6_HBDC2_MASK

#define HBRIDGE9_CR6_HBDC2_MASK   0xC000

HBRIDGE9_CR6_HBDCH2

#define HBRIDGE9_CR6_HBDCH2   0x4000

HBRIDGE9_CR6_HBDCL2

#define HBRIDGE9_CR6_HBDCL2   0x8000

H-Bridge 9 Control register 6 bits.

Specified bits for Control register 6 of H-Bridge 9 Click driver.

HBRIDGE9_CR6_STBY1

#define HBRIDGE9_CR6_STBY1   0x2000

HBRIDGE9_CR7_HBDC1_MASK

#define HBRIDGE9_CR7_HBDC1_MASK   0xC000

HBRIDGE9_CR7_HBDCH1

#define HBRIDGE9_CR7_HBDCH1   0x4000

HBRIDGE9_CR7_HBDCL1

#define HBRIDGE9_CR7_HBDCL1   0x8000

H-Bridge 9 Control register 7 bits.

Specified bits for Control register 7 of H-Bridge 9 Click driver.

HBRIDGE9_CR7_ODC1_MASK

#define HBRIDGE9_CR7_ODC1_MASK   0x0006

HBRIDGE9_CR7_ODC2_MASK

#define HBRIDGE9_CR7_ODC2_MASK   0x0018

HBRIDGE9_CR7_ODC3_MASK

#define HBRIDGE9_CR7_ODC3_MASK   0x0060

HBRIDGE9_CR7_ODC4_MASK

#define HBRIDGE9_CR7_ODC4_MASK   0x0180

HBRIDGE9_CR7_ODC5_MASK

#define HBRIDGE9_CR7_ODC5_MASK   0x0600

HBRIDGE9_CR7_ODC6_MASK

#define HBRIDGE9_CR7_ODC6_MASK   0x1800

HBRIDGE9_CR7_ODCH1

#define HBRIDGE9_CR7_ODCH1   0x0002

HBRIDGE9_CR7_ODCH2

#define HBRIDGE9_CR7_ODCH2   0x0008

HBRIDGE9_CR7_ODCH3

#define HBRIDGE9_CR7_ODCH3   0x0020

HBRIDGE9_CR7_ODCH4

#define HBRIDGE9_CR7_ODCH4   0x0080

HBRIDGE9_CR7_ODCH5

#define HBRIDGE9_CR7_ODCH5   0x0200

HBRIDGE9_CR7_ODCH6

#define HBRIDGE9_CR7_ODCH6   0x0800

HBRIDGE9_CR7_ODCL1

#define HBRIDGE9_CR7_ODCL1   0x0004

HBRIDGE9_CR7_ODCL2

#define HBRIDGE9_CR7_ODCL2   0x0010

HBRIDGE9_CR7_ODCL3

#define HBRIDGE9_CR7_ODCL3   0x0040

HBRIDGE9_CR7_ODCL4

#define HBRIDGE9_CR7_ODCL4   0x0100

HBRIDGE9_CR7_ODCL5

#define HBRIDGE9_CR7_ODCL5   0x0400

HBRIDGE9_CR7_ODCL6

#define HBRIDGE9_CR7_ODCL6   0x1000

HBRIDGE9_CR7_STBY2

#define HBRIDGE9_CR7_STBY2   0x2000

HBRIDGE9_CR8_KI_GAIN_1

#define HBRIDGE9_CR8_KI_GAIN_1   0x0070

HBRIDGE9_CR8_KI_GAIN_1_OVER_128

#define HBRIDGE9_CR8_KI_GAIN_1_OVER_128   0x0000

H-Bridge 9 Control register 8 bits.

Specified bits for Control register 8 of H-Bridge 9 Click driver.

HBRIDGE9_CR8_KI_GAIN_1_OVER_16

#define HBRIDGE9_CR8_KI_GAIN_1_OVER_16   0x0030

HBRIDGE9_CR8_KI_GAIN_1_OVER_2

#define HBRIDGE9_CR8_KI_GAIN_1_OVER_2   0x0060

HBRIDGE9_CR8_KI_GAIN_1_OVER_32

#define HBRIDGE9_CR8_KI_GAIN_1_OVER_32   0x0020

HBRIDGE9_CR8_KI_GAIN_1_OVER_4

#define HBRIDGE9_CR8_KI_GAIN_1_OVER_4   0x0050

HBRIDGE9_CR8_KI_GAIN_1_OVER_64

#define HBRIDGE9_CR8_KI_GAIN_1_OVER_64   0x0010

HBRIDGE9_CR8_KI_GAIN_1_OVER_8

#define HBRIDGE9_CR8_KI_GAIN_1_OVER_8   0x0040

HBRIDGE9_CR8_KI_GAIN_MASK

#define HBRIDGE9_CR8_KI_GAIN_MASK   0x0070

HBRIDGE9_CR8_KP_GAIN_128

#define HBRIDGE9_CR8_KP_GAIN_128   0x0006

HBRIDGE9_CR8_KP_GAIN_16

#define HBRIDGE9_CR8_KP_GAIN_16   0x0003

HBRIDGE9_CR8_KP_GAIN_2

#define HBRIDGE9_CR8_KP_GAIN_2   0x0000

HBRIDGE9_CR8_KP_GAIN_256

#define HBRIDGE9_CR8_KP_GAIN_256   0x0007

HBRIDGE9_CR8_KP_GAIN_32

#define HBRIDGE9_CR8_KP_GAIN_32   0x0004

HBRIDGE9_CR8_KP_GAIN_4

#define HBRIDGE9_CR8_KP_GAIN_4   0x0001

HBRIDGE9_CR8_KP_GAIN_64

#define HBRIDGE9_CR8_KP_GAIN_64   0x0005

HBRIDGE9_CR8_KP_GAIN_8

#define HBRIDGE9_CR8_KP_GAIN_8   0x0002

HBRIDGE9_CR8_KP_GAIN_MASK

#define HBRIDGE9_CR8_KP_GAIN_MASK   0x0007

HBRIDGE9_CURRENT_1A

#define HBRIDGE9_CURRENT_1A   0x0010

HBRIDGE9_CURRENT_1p2A

#define HBRIDGE9_CURRENT_1p2A   0x0011

HBRIDGE9_CURRENT_1p4A

#define HBRIDGE9_CURRENT_1p4A   0x0012

HBRIDGE9_CURRENT_1p6A

#define HBRIDGE9_CURRENT_1p6A   0x0013

HBRIDGE9_CURRENT_1p8A

#define HBRIDGE9_CURRENT_1p8A   0x0014

HBRIDGE9_CURRENT_2A

#define HBRIDGE9_CURRENT_2A   0x0015

HBRIDGE9_CURRENT_2p2A

#define HBRIDGE9_CURRENT_2p2A   0x0016

HBRIDGE9_CURRENT_2p4A

#define HBRIDGE9_CURRENT_2p4A   0x0017

HBRIDGE9_CURRENT_2p6A

#define HBRIDGE9_CURRENT_2p6A   0x0018

HBRIDGE9_CURRENT_2p8A

#define HBRIDGE9_CURRENT_2p8A   0x0019

HBRIDGE9_CURRENT_3A

#define HBRIDGE9_CURRENT_3A   0x001A

HBRIDGE9_CURRENT_3p2A

#define HBRIDGE9_CURRENT_3p2A   0x001B

HBRIDGE9_CURRENT_3p4A

#define HBRIDGE9_CURRENT_3p4A   0x001C

HBRIDGE9_CURRENT_3p6A

#define HBRIDGE9_CURRENT_3p6A   0x001D

HBRIDGE9_CURRENT_3p8A

#define HBRIDGE9_CURRENT_3p8A   0x001E

HBRIDGE9_CURRENT_4A

#define HBRIDGE9_CURRENT_4A   0x001F

HBRIDGE9_CURRENT_MASK

#define HBRIDGE9_CURRENT_MASK   0x001F

HBRIDGE9_DUTY_CYCLE_100

#define HBRIDGE9_DUTY_CYCLE_100   0x000F

HBRIDGE9_DUTY_CYCLE_12p5

#define HBRIDGE9_DUTY_CYCLE_12p5   0x0001

HBRIDGE9_DUTY_CYCLE_18p75

#define HBRIDGE9_DUTY_CYCLE_18p75   0x0002

HBRIDGE9_DUTY_CYCLE_25

#define HBRIDGE9_DUTY_CYCLE_25   0x0003

HBRIDGE9_DUTY_CYCLE_31p25

#define HBRIDGE9_DUTY_CYCLE_31p25   0x0004

HBRIDGE9_DUTY_CYCLE_37p5

#define HBRIDGE9_DUTY_CYCLE_37p5   0x0005

HBRIDGE9_DUTY_CYCLE_43p75

#define HBRIDGE9_DUTY_CYCLE_43p75   0x0006

HBRIDGE9_DUTY_CYCLE_50

#define HBRIDGE9_DUTY_CYCLE_50   0x0007

HBRIDGE9_DUTY_CYCLE_56p25

#define HBRIDGE9_DUTY_CYCLE_56p25   0x0008

HBRIDGE9_DUTY_CYCLE_62p5

#define HBRIDGE9_DUTY_CYCLE_62p5   0x0009

HBRIDGE9_DUTY_CYCLE_68p75

#define HBRIDGE9_DUTY_CYCLE_68p75   0x000A

HBRIDGE9_DUTY_CYCLE_6p25

#define HBRIDGE9_DUTY_CYCLE_6p25   0x0000

HBRIDGE9_DUTY_CYCLE_75

#define HBRIDGE9_DUTY_CYCLE_75   0x000B

HBRIDGE9_DUTY_CYCLE_81p25

#define HBRIDGE9_DUTY_CYCLE_81p25   0x000C

HBRIDGE9_DUTY_CYCLE_87p5

#define HBRIDGE9_DUTY_CYCLE_87p5   0x000D

HBRIDGE9_DUTY_CYCLE_93p75

#define HBRIDGE9_DUTY_CYCLE_93p75   0x000E

HBRIDGE9_DUTY_CYCLE_MASK

#define HBRIDGE9_DUTY_CYCLE_MASK   0x001F

HBRIDGE9_ODD_PARITY

#define HBRIDGE9_ODD_PARITY   0x01

H-Bridge 9 ODD parity flag.

Specified flag for ODD parity of H-Bridge 9 Click driver.

HBRIDGE9_SET_DATA_SAMPLE_EDGE

#define HBRIDGE9_SET_DATA_SAMPLE_EDGE   SET_SPI_DATA_SAMPLE_EDGE

Data sample selection.

This macro sets data samples for SPI modules.

Note

Available only on Microchip PIC family devices. This macro will set data sampling for all SPI modules on MCU. Can be overwritten with hbridge9_init which will set SET_SPI_DATA_SAMPLE_MIDDLE by default on the mapped mikrobus.

HBRIDGE9_SET_DATA_SAMPLE_MIDDLE

#define HBRIDGE9_SET_DATA_SAMPLE_MIDDLE   SET_SPI_DATA_SAMPLE_MIDDLE

HBRIDGE9_SPI_CPHA_TEST

#define HBRIDGE9_SPI_CPHA_TEST   0x55

H-Bridge 9 SPI CPHA test bits.

Specified bits for SPI CPHA test of H-Bridge 9 Click driver.