Macros
#define	I2C1WIRE_RESULT_ERROR 0x00

#define	I2C1WIRE_RESULT_OK 0x01

#define	I2C1WIRE_WIRE_RESULT_OK 0xFF

#define	I2C1WIRE_I2C_ADDRESS_0 0x18

#define	I2C1WIRE_I2C_ADDRESS_1 0x19

#define	I2C1WIRE_I2C_ADDRESS_2 0x1A

#define	I2C1WIRE_I2C_ADDRESS_3 0x1B

#define	I2C1WIRE_I2C_ADDRESS_4 0x1C

#define	I2C1WIRE_I2C_ADDRESS_5 0x1D

#define	I2C1WIRE_I2C_ADDRESS_6 0x1E

#define	I2C1WIRE_I2C_ADDRESS_7 0x1F

#define	I2C1WIRE_COMMAND_RESET 0xF0

#define	I2C1WIRE_COMMAND_SRP 0xE1

#define	I2C1WIRE_POINTER_STATUS 0xF0

#define	I2C1WIRE_STATUS_BUSY 0x01

#define	I2C1WIRE_STATUS_PPD 0x02

#define	I2C1WIRE_STATUS_SD 0x04

#define	I2C1WIRE_STATUS_LL 0x08

#define	I2C1WIRE_STATUS_RST 0x10

#define	I2C1WIRE_STATUS_SBR 0x20

#define	I2C1WIRE_STATUS_TSB 0x40

#define	I2C1WIRE_STATUS_DIR 0x80

#define	I2C1WIRE_POINTER_DATA 0xE1

#define	I2C1WIRE_POINTER_CONFIG 0xC3

#define	I2C1WIRE_CONFIG_APU_HIGH 0x30

#define	I2C1WIRE_CONFIG_APU_LOW 0x01

#define	I2C1WIRE_CONFIG_SPU_HIGH 0x60

#define	I2C1WIRE_CONFIG_SPU_LOW 0x04

#define	I2C1WIRE_CONFIG_1WS_HIGH 0xA0

#define	I2C1WIRE_CONFIG_1WS_LOW 0x08

#define	I2C1WIRE_COMMAND_WRITECONFIG 0xD2

#define	I2C1WIRE_COMMAND_RESETWIRE 0xB4

#define	I2C1WIRE_COMMAND_WRITEBYTE 0xA5

#define	I2C1WIRE_COMMAND_READBYTE 0x96

#define	I2C1WIRE_COMMAND_SINGLEBIT 0x87

#define	I2C1WIRE_COMMAND_TRIPLET 0x78

#define	I2C1WIRE_WIRE_COMMAND_SKIP 0xCC

#define	I2C1WIRE_WIRE_COMMAND_SELECT 0x55

#define	I2C1WIRE_WIRE_COMMAND_READ_ROM 0x33

#define	I2C1WIRE_WIRE_COMMAND_SEARCH 0xF0

#define	I2C1WIRE_ERROR_TIMEOUT 0x01

#define	I2C1WIRE_ERROR_SHORT 0x02

#define	I2C1WIRE_ERROR_CONFIG 0x04

#define	I2C1WIRE_CMD_CHSL 0xC3

#define	I2C1WIRE_CH_IO0 0xF0

#define	I2C1WIRE_CH_IO1 0xE1

#define	I2C1WIRE_CH_IO2 0xD2

#define	I2C1WIRE_CH_IO3 0xC3

#define	I2C1WIRE_CH_IO4 0xB4

#define	I2C1WIRE_CH_IO5 0xA5

#define	I2C1WIRE_CH_IO6 0x96

#define	I2C1WIRE_CH_IO7 0x87

#define	I2C1WIRE_RCH_IO0 0xB8

#define	I2C1WIRE_RCH_IO1 0xB1

#define	I2C1WIRE_RCH_IO2 0xAA

#define	I2C1WIRE_RCH_IO3 0xA3

#define	I2C1WIRE_RCH_IO4 0x9C

#define	I2C1WIRE_RCH_IO5 0x95

#define	I2C1WIRE_RCH_IO6 0x8E

#define	I2C1WIRE_RCH_IO7 0x87

Detailed Description

Macro Definition Documentation

◆ I2C1WIRE_CH_IO0

#define I2C1WIRE_CH_IO0 0xF0

◆ I2C1WIRE_CH_IO1

#define I2C1WIRE_CH_IO1 0xE1

◆ I2C1WIRE_CH_IO2

#define I2C1WIRE_CH_IO2 0xD2

◆ I2C1WIRE_CH_IO3

#define I2C1WIRE_CH_IO3 0xC3

◆ I2C1WIRE_CH_IO4

#define I2C1WIRE_CH_IO4 0xB4

◆ I2C1WIRE_CH_IO5

#define I2C1WIRE_CH_IO5 0xA5

◆ I2C1WIRE_CH_IO6

#define I2C1WIRE_CH_IO6 0x96

◆ I2C1WIRE_CH_IO7

#define I2C1WIRE_CH_IO7 0x87

◆ I2C1WIRE_CMD_CHSL

#define I2C1WIRE_CMD_CHSL 0xC3

◆ I2C1WIRE_COMMAND_READBYTE

#define I2C1WIRE_COMMAND_READBYTE 0x96

◆ I2C1WIRE_COMMAND_RESET

#define I2C1WIRE_COMMAND_RESET 0xF0

◆ I2C1WIRE_COMMAND_RESETWIRE

#define I2C1WIRE_COMMAND_RESETWIRE 0xB4

◆ I2C1WIRE_COMMAND_SINGLEBIT

#define I2C1WIRE_COMMAND_SINGLEBIT 0x87

◆ I2C1WIRE_COMMAND_SRP

#define I2C1WIRE_COMMAND_SRP 0xE1

◆ I2C1WIRE_COMMAND_TRIPLET

#define I2C1WIRE_COMMAND_TRIPLET 0x78

◆ I2C1WIRE_COMMAND_WRITEBYTE

#define I2C1WIRE_COMMAND_WRITEBYTE 0xA5

◆ I2C1WIRE_COMMAND_WRITECONFIG

#define I2C1WIRE_COMMAND_WRITECONFIG 0xD2

◆ I2C1WIRE_CONFIG_1WS_HIGH

#define I2C1WIRE_CONFIG_1WS_HIGH 0xA0

◆ I2C1WIRE_CONFIG_1WS_LOW

#define I2C1WIRE_CONFIG_1WS_LOW 0x08

◆ I2C1WIRE_CONFIG_APU_HIGH

#define I2C1WIRE_CONFIG_APU_HIGH 0x30

◆ I2C1WIRE_CONFIG_APU_LOW

#define I2C1WIRE_CONFIG_APU_LOW 0x01

◆ I2C1WIRE_CONFIG_SPU_HIGH

#define I2C1WIRE_CONFIG_SPU_HIGH 0x60

◆ I2C1WIRE_CONFIG_SPU_LOW

#define I2C1WIRE_CONFIG_SPU_LOW 0x04

◆ I2C1WIRE_ERROR_CONFIG

#define I2C1WIRE_ERROR_CONFIG 0x04

◆ I2C1WIRE_ERROR_SHORT

#define I2C1WIRE_ERROR_SHORT 0x02

◆ I2C1WIRE_ERROR_TIMEOUT

#define I2C1WIRE_ERROR_TIMEOUT 0x01

◆ I2C1WIRE_I2C_ADDRESS_0

#define I2C1WIRE_I2C_ADDRESS_0 0x18

◆ I2C1WIRE_I2C_ADDRESS_1

#define I2C1WIRE_I2C_ADDRESS_1 0x19

◆ I2C1WIRE_I2C_ADDRESS_2

#define I2C1WIRE_I2C_ADDRESS_2 0x1A

◆ I2C1WIRE_I2C_ADDRESS_3

#define I2C1WIRE_I2C_ADDRESS_3 0x1B

◆ I2C1WIRE_I2C_ADDRESS_4

#define I2C1WIRE_I2C_ADDRESS_4 0x1C

◆ I2C1WIRE_I2C_ADDRESS_5

#define I2C1WIRE_I2C_ADDRESS_5 0x1D

◆ I2C1WIRE_I2C_ADDRESS_6

#define I2C1WIRE_I2C_ADDRESS_6 0x1E

◆ I2C1WIRE_I2C_ADDRESS_7

#define I2C1WIRE_I2C_ADDRESS_7 0x1F

◆ I2C1WIRE_POINTER_CONFIG

#define I2C1WIRE_POINTER_CONFIG 0xC3

◆ I2C1WIRE_POINTER_DATA

#define I2C1WIRE_POINTER_DATA 0xE1

◆ I2C1WIRE_POINTER_STATUS

#define I2C1WIRE_POINTER_STATUS 0xF0

◆ I2C1WIRE_RCH_IO0

#define I2C1WIRE_RCH_IO0 0xB8

◆ I2C1WIRE_RCH_IO1

#define I2C1WIRE_RCH_IO1 0xB1

◆ I2C1WIRE_RCH_IO2

#define I2C1WIRE_RCH_IO2 0xAA

◆ I2C1WIRE_RCH_IO3

#define I2C1WIRE_RCH_IO3 0xA3

◆ I2C1WIRE_RCH_IO4

#define I2C1WIRE_RCH_IO4 0x9C

◆ I2C1WIRE_RCH_IO5

#define I2C1WIRE_RCH_IO5 0x95

◆ I2C1WIRE_RCH_IO6

#define I2C1WIRE_RCH_IO6 0x8E

◆ I2C1WIRE_RCH_IO7

#define I2C1WIRE_RCH_IO7 0x87

◆ I2C1WIRE_RESULT_ERROR

#define I2C1WIRE_RESULT_ERROR 0x00

◆ I2C1WIRE_RESULT_OK

#define I2C1WIRE_RESULT_OK 0x01

◆ I2C1WIRE_STATUS_BUSY

#define I2C1WIRE_STATUS_BUSY 0x01

◆ I2C1WIRE_STATUS_DIR

#define I2C1WIRE_STATUS_DIR 0x80

◆ I2C1WIRE_STATUS_LL

#define I2C1WIRE_STATUS_LL 0x08

◆ I2C1WIRE_STATUS_PPD

#define I2C1WIRE_STATUS_PPD 0x02

◆ I2C1WIRE_STATUS_RST

#define I2C1WIRE_STATUS_RST 0x10

◆ I2C1WIRE_STATUS_SBR

#define I2C1WIRE_STATUS_SBR 0x20

◆ I2C1WIRE_STATUS_SD

#define I2C1WIRE_STATUS_SD 0x04

◆ I2C1WIRE_STATUS_TSB

#define I2C1WIRE_STATUS_TSB 0x40

◆ I2C1WIRE_WIRE_COMMAND_READ_ROM

#define I2C1WIRE_WIRE_COMMAND_READ_ROM 0x33

◆ I2C1WIRE_WIRE_COMMAND_SEARCH

#define I2C1WIRE_WIRE_COMMAND_SEARCH 0xF0

◆ I2C1WIRE_WIRE_COMMAND_SELECT

#define I2C1WIRE_WIRE_COMMAND_SELECT 0x55

◆ I2C1WIRE_WIRE_COMMAND_SKIP

#define I2C1WIRE_WIRE_COMMAND_SKIP 0xCC

◆ I2C1WIRE_WIRE_RESULT_OK

#define I2C1WIRE_WIRE_RESULT_OK 0xFF

Macros