Settings for registers of I2C MUX 5 Click driver.
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Settings for registers of I2C MUX 5 Click driver.
◆ I2CMUX5_CH_SEL_ERROR
| #define I2CMUX5_CH_SEL_ERROR 0xFF |
I2C MUX 5 Channel Selection Status.
Specified setting for channel selection status of I2C MUX 5 Click driver.
◆ I2CMUX5_SET_6DOF_IMU_11_ADDR
| #define I2CMUX5_SET_6DOF_IMU_11_ADDR 0x0E |
◆ I2CMUX5_SET_6DOF_IMU_9_ADDR
| #define I2CMUX5_SET_6DOF_IMU_9_ADDR 0x69 |
I2C MUX 5 channel slave address setting.
Specified setting for channel slave address selection of I2C MUX 5 Click driver.
◆ I2CMUX5_SET_ACCEL_10_ADDR
| #define I2CMUX5_SET_ACCEL_10_ADDR 0x18 |
◆ I2CMUX5_SET_DEV_ADDR
| #define I2CMUX5_SET_DEV_ADDR 0x44 |
I2C MUX 5 device address setting.
Specified setting for device slave address selection of I2C MUX 5 Click driver.
◆ I2CMUX5_SET_REG_0_ALERT1_STATE_HIGH
| #define I2CMUX5_SET_REG_0_ALERT1_STATE_HIGH 0x40 |
◆ I2CMUX5_SET_REG_0_ALERT1_STATE_LOW
| #define I2CMUX5_SET_REG_0_ALERT1_STATE_LOW 0x00 |
◆ I2CMUX5_SET_REG_0_ALERT2_STATE_HIGH
| #define I2CMUX5_SET_REG_0_ALERT2_STATE_HIGH 0x20 |
◆ I2CMUX5_SET_REG_0_ALERT2_STATE_LOW
| #define I2CMUX5_SET_REG_0_ALERT2_STATE_LOW 0x00 |
◆ I2CMUX5_SET_REG_0_ALERT3_STATE_HIGH
| #define I2CMUX5_SET_REG_0_ALERT3_STATE_HIGH 0x10 |
◆ I2CMUX5_SET_REG_0_ALERT3_STATE_LOW
| #define I2CMUX5_SET_REG_0_ALERT3_STATE_LOW 0x00 |
◆ I2CMUX5_SET_REG_0_ALERT4_STATE_LOW
| #define I2CMUX5_SET_REG_0_ALERT4_STATE_LOW 0x00 |
◆ I2CMUX5_SET_REG_0_ALERT5_STATE_HIGH
| #define I2CMUX5_SET_REG_0_ALERT5_STATE_HIGH 0x08 |
◆ I2CMUX5_SET_REG_0_ATTEMPT_CONN_FAILED
| #define I2CMUX5_SET_REG_0_ATTEMPT_CONN_FAILED 0x00 |
◆ I2CMUX5_SET_REG_0_ATTEMPT_CONN_OK
| #define I2CMUX5_SET_REG_0_ATTEMPT_CONN_OK 0x04 |
◆ I2CMUX5_SET_REG_0_LATCHED_TIMEOUT
| #define I2CMUX5_SET_REG_0_LATCHED_TIMEOUT 0x02 |
◆ I2CMUX5_SET_REG_0_NO_LATCHED_TIMEOUT
| #define I2CMUX5_SET_REG_0_NO_LATCHED_TIMEOUT 0x00 |
◆ I2CMUX5_SET_REG_0_NO_TIMEOUT_OCCURRING
| #define I2CMUX5_SET_REG_0_NO_TIMEOUT_OCCURRING 0x00 |
◆ I2CMUX5_SET_REG_0_TIMEOUT_OCCURRING
| #define I2CMUX5_SET_REG_0_TIMEOUT_OCCURRING 0x01 |
◆ I2CMUX5_SET_REG_0_US_BUS_CONNECTED
| #define I2CMUX5_SET_REG_0_US_BUS_CONNECTED 0x80 |
◆ I2CMUX5_SET_REG_0_US_BUS_DISCONNECTED
| #define I2CMUX5_SET_REG_0_US_BUS_DISCONNECTED 0x00 |
I2C MUX 5 description setting.
Specified setting for description of I2C MUX 5 Click driver.
I2C MUX 5 Register 0 setting.
Specified setting for Register 1 of I2C MUX 5 Click driver.
◆ I2CMUX5_SET_REG_1_DRTAC_ACTIVE
| #define I2CMUX5_SET_REG_1_DRTAC_ACTIVE 0x40 |
◆ I2CMUX5_SET_REG_1_DRTAC_INACTIVE
| #define I2CMUX5_SET_REG_1_DRTAC_INACTIVE 0x00 |
◆ I2CMUX5_SET_REG_1_GPIO_1_HIGH
| #define I2CMUX5_SET_REG_1_GPIO_1_HIGH 0x20 |
◆ I2CMUX5_SET_REG_1_GPIO_1_LOW
| #define I2CMUX5_SET_REG_1_GPIO_1_LOW 0x00 |
◆ I2CMUX5_SET_REG_1_GPIO_2_HIGH
| #define I2CMUX5_SET_REG_1_GPIO_2_HIGH 0x10 |
◆ I2CMUX5_SET_REG_1_GPIO_2_LOW
| #define I2CMUX5_SET_REG_1_GPIO_2_LOW 0x00 |
◆ I2CMUX5_SET_REG_1_URTAC_ACTIVE
| #define I2CMUX5_SET_REG_1_URTAC_ACTIVE 0x80 |
◆ I2CMUX5_SET_REG_1_URTAC_INACTIVE
| #define I2CMUX5_SET_REG_1_URTAC_INACTIVE 0x00 |
I2C MUX 5 Register 1 setting.
Specified setting for Register 1 of I2C MUX 5 Click driver.
◆ I2CMUX5_SET_REG_2_BUS_LOGIC_STATE_BITS
| #define I2CMUX5_SET_REG_2_BUS_LOGIC_STATE_BITS 0x00 |
◆ I2CMUX5_SET_REG_2_CFG_GPIO_1_INPUT
| #define I2CMUX5_SET_REG_2_CFG_GPIO_1_INPUT 0x80 |
◆ I2CMUX5_SET_REG_2_CFG_GPIO_1_OD_PULL_DOWN
| #define I2CMUX5_SET_REG_2_CFG_GPIO_1_OD_PULL_DOWN 0x00 |
◆ I2CMUX5_SET_REG_2_CFG_GPIO_1_OUTPUT
| #define I2CMUX5_SET_REG_2_CFG_GPIO_1_OUTPUT 0x00 |
I2C MUX 5 Register 2 setting.
Specified setting for Register 2 of I2C MUX 5 Click driver.
◆ I2CMUX5_SET_REG_2_CFG_GPIO_1_PUSH_PULL
| #define I2CMUX5_SET_REG_2_CFG_GPIO_1_PUSH_PULL 0x10 |
◆ I2CMUX5_SET_REG_2_CFG_GPIO_2_INPUT
| #define I2CMUX5_SET_REG_2_CFG_GPIO_2_INPUT 0x40 |
◆ I2CMUX5_SET_REG_2_CFG_GPIO_2_OD_PULL_DOWN
| #define I2CMUX5_SET_REG_2_CFG_GPIO_2_OD_PULL_DOWN 0x00 |
◆ I2CMUX5_SET_REG_2_CFG_GPIO_2_OUTPUT
| #define I2CMUX5_SET_REG_2_CFG_GPIO_2_OUTPUT 0x00 |
◆ I2CMUX5_SET_REG_2_CFG_GPIO_2_PUSH_PULL
| #define I2CMUX5_SET_REG_2_CFG_GPIO_2_PUSH_PULL 0x08 |
◆ I2CMUX5_SET_REG_2_CONN_RGL_LOGIC_STATE
| #define I2CMUX5_SET_REG_2_CONN_RGL_LOGIC_STATE 0x20 |
◆ I2CMUX5_SET_REG_2_MASS_WRITE_DISABLE
| #define I2CMUX5_SET_REG_2_MASS_WRITE_DISABLE 0x00 |
◆ I2CMUX5_SET_REG_2_MASS_WRITE_ENABLE
| #define I2CMUX5_SET_REG_2_MASS_WRITE_ENABLE 0x04 |
◆ I2CMUX5_SET_REG_2_TIMEOUT_DISABLED
| #define I2CMUX5_SET_REG_2_TIMEOUT_DISABLED 0x00 |
◆ I2CMUX5_SET_REG_2_TIMEOUT_MODE_15_MS
| #define I2CMUX5_SET_REG_2_TIMEOUT_MODE_15_MS 0x02 |
◆ I2CMUX5_SET_REG_2_TIMEOUT_MODE_30_MS
| #define I2CMUX5_SET_REG_2_TIMEOUT_MODE_30_MS 0x01 |
◆ I2CMUX5_SET_REG_2_TIMEOUT_MODE_7_5_MS
| #define I2CMUX5_SET_REG_2_TIMEOUT_MODE_7_5_MS 0x03 |
◆ I2CMUX5_SET_REG_3_BUS_1_SWITCH_CLOSED
| #define I2CMUX5_SET_REG_3_BUS_1_SWITCH_CLOSED 0x80 |
◆ I2CMUX5_SET_REG_3_BUS_1_SWITCH_OPEN
| #define I2CMUX5_SET_REG_3_BUS_1_SWITCH_OPEN 0x00 |
I2C MUX 5 Register 3 setting.
Specified setting for Register 3 of I2C MUX 5 Click driver.
◆ I2CMUX5_SET_REG_3_BUS_2_SWITCH_CLOSED
| #define I2CMUX5_SET_REG_3_BUS_2_SWITCH_CLOSED 0x40 |
◆ I2CMUX5_SET_REG_3_BUS_2_SWITCH_OPEN
| #define I2CMUX5_SET_REG_3_BUS_2_SWITCH_OPEN 0x00 |
◆ I2CMUX5_SET_REG_3_BUS_3_SWITCH_CLOSED
| #define I2CMUX5_SET_REG_3_BUS_3_SWITCH_CLOSED 0x20 |
◆ I2CMUX5_SET_REG_3_BUS_3_SWITCH_OPEN
| #define I2CMUX5_SET_REG_3_BUS_3_SWITCH_OPEN 0x00 |
◆ I2CMUX5_SET_REG_3_BUS_4_SWITCH_CLOSED
| #define I2CMUX5_SET_REG_3_BUS_4_SWITCH_CLOSED 0x10 |
◆ I2CMUX5_SET_REG_3_BUS_4_SWITCH_OPEN
| #define I2CMUX5_SET_REG_3_BUS_4_SWITCH_OPEN 0x00 |
◆ I2CMUX5_SET_RTC_10_ADDR
| #define I2CMUX5_SET_RTC_10_ADDR 0x68 |