Macros
#define	I2CTOSPI_CONFIGURE_GPIO_QUASI_BIDIRECTIONAL_SS0 0x00

#define	I2CTOSPI_CONFIGURE_GPIO_PUSH_PULL_SS0 0x01

#define	I2CTOSPI_CONFIGURE_GPIO_INPUT_ONLY_SS0 0x02

#define	I2CTOSPI_CONFIGURE_GPIO_OPEN_DRAIN_SS0 0x03

#define	I2CTOSPI_CONFIGURE_GPIO_QUASI_BIDIRECTIONAL_SS1 0x00

#define	I2CTOSPI_CONFIGURE_GPIO_PUSH_PULL_SS1 0x04

#define	I2CTOSPI_CONFIGURE_GPIO_INPUT_ONLY_SS1 0x08

#define	I2CTOSPI_CONFIGURE_GPIO_OPEN_DRAIN_SS1 0x0C

#define	I2CTOSPI_CONFIGURE_GPIO_QUASI_BIDIRECTIONAL_SS2 0x00

#define	I2CTOSPI_CONFIGURE_GPIO_PUSH_PULL_SS2 0x10

#define	I2CTOSPI_CONFIGURE_GPIO_INPUT_ONLY_SS2 0x20

#define	I2CTOSPI_CONFIGURE_GPIO_OPEN_DRAIN_SS2 0x30

#define	I2CTOSPI_CONFIGURE_GPIO_QUASI_BIDIRECTIONAL_SS3 0x00

#define	I2CTOSPI_CONFIGURE_GPIO_PUSH_PULL_SS3 0x40

#define	I2CTOSPI_CONFIGURE_GPIO_INPUT_ONLY_SS3 0x80

#define	I2CTOSPI_CONFIGURE_GPIO_OPEN_DRAIN_SS3 0xC0

#define	I2CTOSPI_SLAVEDEVICE_SS0 0x01

#define	I2CTOSPI_SLAVEDEVICE_SS1 0x02

#define	I2CTOSPI_SLAVEDEVICE_SS2 0x04

#define	I2CTOSPI_SLAVEDEVICE_SS3 0x08

#define	I2CTOSPI_RTC5_COMMAND_WRITE 0x12

#define	I2CTOSPI_RTC5_COMMAND_READ 0x13

#define	I2CTOSPI_RTC5_REG_TIME_HUN_OF_SEC 0x00

#define	I2CTOSPI_RTC5_REG_TIME_SEC 0x01

#define	I2CTOSPI_RTC5_REG_TIME_MIN 0x02

#define	I2CTOSPI_RTC5_REG_TIME_HOUR 0x03

#define	I2CTOSPI_RTC5_REG_TIME_DAY_OF_THE_WEEK 0x04

#define	I2CTOSPI_RTC5_REG_TIME_DATE_DAY 0x05

#define	I2CTOSPI_RTC5_REG_TIME_DATE_MONTH 0x06

#define	I2CTOSPI_RTC5_REG_TIME_DATE_YEAR 0x07

#define	I2CTOSPI_RTC5_REG_CONFIG 0x08

#define	I2CTOSPI_RTC5_REG_CALIBRATION 0x09

#define	I2CTOSPI_RTC5_COMMAND_CLEAR 0x54

#define	I2CTOSPI_RTC5_COMMAND_ENABLE_COUNTING 0x80

Detailed Description

Macro Definition Documentation

◆ I2CTOSPI_CONFIGURE_GPIO_INPUT_ONLY_SS0

#define I2CTOSPI_CONFIGURE_GPIO_INPUT_ONLY_SS0 0x02

◆ I2CTOSPI_CONFIGURE_GPIO_INPUT_ONLY_SS1

#define I2CTOSPI_CONFIGURE_GPIO_INPUT_ONLY_SS1 0x08

◆ I2CTOSPI_CONFIGURE_GPIO_INPUT_ONLY_SS2

#define I2CTOSPI_CONFIGURE_GPIO_INPUT_ONLY_SS2 0x20

◆ I2CTOSPI_CONFIGURE_GPIO_INPUT_ONLY_SS3

#define I2CTOSPI_CONFIGURE_GPIO_INPUT_ONLY_SS3 0x80

◆ I2CTOSPI_CONFIGURE_GPIO_OPEN_DRAIN_SS0

#define I2CTOSPI_CONFIGURE_GPIO_OPEN_DRAIN_SS0 0x03

◆ I2CTOSPI_CONFIGURE_GPIO_OPEN_DRAIN_SS1

#define I2CTOSPI_CONFIGURE_GPIO_OPEN_DRAIN_SS1 0x0C

◆ I2CTOSPI_CONFIGURE_GPIO_OPEN_DRAIN_SS2

#define I2CTOSPI_CONFIGURE_GPIO_OPEN_DRAIN_SS2 0x30

◆ I2CTOSPI_CONFIGURE_GPIO_OPEN_DRAIN_SS3

#define I2CTOSPI_CONFIGURE_GPIO_OPEN_DRAIN_SS3 0xC0

◆ I2CTOSPI_CONFIGURE_GPIO_PUSH_PULL_SS0

#define I2CTOSPI_CONFIGURE_GPIO_PUSH_PULL_SS0 0x01

◆ I2CTOSPI_CONFIGURE_GPIO_PUSH_PULL_SS1

#define I2CTOSPI_CONFIGURE_GPIO_PUSH_PULL_SS1 0x04

◆ I2CTOSPI_CONFIGURE_GPIO_PUSH_PULL_SS2

#define I2CTOSPI_CONFIGURE_GPIO_PUSH_PULL_SS2 0x10

◆ I2CTOSPI_CONFIGURE_GPIO_PUSH_PULL_SS3

#define I2CTOSPI_CONFIGURE_GPIO_PUSH_PULL_SS3 0x40

◆ I2CTOSPI_CONFIGURE_GPIO_QUASI_BIDIRECTIONAL_SS0

#define I2CTOSPI_CONFIGURE_GPIO_QUASI_BIDIRECTIONAL_SS0 0x00

◆ I2CTOSPI_CONFIGURE_GPIO_QUASI_BIDIRECTIONAL_SS1

#define I2CTOSPI_CONFIGURE_GPIO_QUASI_BIDIRECTIONAL_SS1 0x00

◆ I2CTOSPI_CONFIGURE_GPIO_QUASI_BIDIRECTIONAL_SS2

#define I2CTOSPI_CONFIGURE_GPIO_QUASI_BIDIRECTIONAL_SS2 0x00

◆ I2CTOSPI_CONFIGURE_GPIO_QUASI_BIDIRECTIONAL_SS3

#define I2CTOSPI_CONFIGURE_GPIO_QUASI_BIDIRECTIONAL_SS3 0x00

◆ I2CTOSPI_RTC5_COMMAND_CLEAR

#define I2CTOSPI_RTC5_COMMAND_CLEAR 0x54

◆ I2CTOSPI_RTC5_COMMAND_ENABLE_COUNTING

#define I2CTOSPI_RTC5_COMMAND_ENABLE_COUNTING 0x80

◆ I2CTOSPI_RTC5_COMMAND_READ

#define I2CTOSPI_RTC5_COMMAND_READ 0x13

◆ I2CTOSPI_RTC5_COMMAND_WRITE

#define I2CTOSPI_RTC5_COMMAND_WRITE 0x12

◆ I2CTOSPI_RTC5_REG_CALIBRATION

#define I2CTOSPI_RTC5_REG_CALIBRATION 0x09

◆ I2CTOSPI_RTC5_REG_CONFIG

#define I2CTOSPI_RTC5_REG_CONFIG 0x08

◆ I2CTOSPI_RTC5_REG_TIME_DATE_DAY

#define I2CTOSPI_RTC5_REG_TIME_DATE_DAY 0x05

◆ I2CTOSPI_RTC5_REG_TIME_DATE_MONTH

#define I2CTOSPI_RTC5_REG_TIME_DATE_MONTH 0x06

◆ I2CTOSPI_RTC5_REG_TIME_DATE_YEAR

#define I2CTOSPI_RTC5_REG_TIME_DATE_YEAR 0x07

◆ I2CTOSPI_RTC5_REG_TIME_DAY_OF_THE_WEEK

#define I2CTOSPI_RTC5_REG_TIME_DAY_OF_THE_WEEK 0x04

◆ I2CTOSPI_RTC5_REG_TIME_HOUR

#define I2CTOSPI_RTC5_REG_TIME_HOUR 0x03

◆ I2CTOSPI_RTC5_REG_TIME_HUN_OF_SEC

#define I2CTOSPI_RTC5_REG_TIME_HUN_OF_SEC 0x00

◆ I2CTOSPI_RTC5_REG_TIME_MIN

#define I2CTOSPI_RTC5_REG_TIME_MIN 0x02

◆ I2CTOSPI_RTC5_REG_TIME_SEC

#define I2CTOSPI_RTC5_REG_TIME_SEC 0x01

◆ I2CTOSPI_SLAVEDEVICE_SS0

#define I2CTOSPI_SLAVEDEVICE_SS0 0x01

◆ I2CTOSPI_SLAVEDEVICE_SS1

#define I2CTOSPI_SLAVEDEVICE_SS1 0x02

◆ I2CTOSPI_SLAVEDEVICE_SS2

#define I2CTOSPI_SLAVEDEVICE_SS2 0x04

◆ I2CTOSPI_SLAVEDEVICE_SS3

#define I2CTOSPI_SLAVEDEVICE_SS3 0x08

Macros