List of registers of ISM Click driver. More...

Macros
#define	ISM_REG_BANK_0_CONFIG 0x00
	ISM description register.

#define	ISM_REG_BANK_0_EN_AA 0x01

#define	ISM_REG_BANK_0_EN_RXADDR 0x02

#define	ISM_REG_BANK_0_SETUP_AW 0x03

#define	ISM_REG_BANK_0_SETUP_RETR 0x04

#define	ISM_REG_BANK_0_RF_CH 0x05

#define	ISM_REG_BANK_0_RF_SETUP 0x06

#define	ISM_REG_BANK_0_STATUS 0x07

#define	ISM_REG_BANK_0_OBSERVE_TX 0x08

#define	ISM_REG_BANK_0_CD 0x09

#define	ISM_REG_BANK_0_RX_ADDR_P0 0x0A

#define	ISM_REG_BANK_0_RX_ADDR_P1 0x0B

#define	ISM_REG_BANK_0_RX_ADDR_P2 0x0C

#define	ISM_REG_BANK_0_RX_ADDR_P3 0x0D

#define	ISM_REG_BANK_0_RX_ADDR_P4 0x0E

#define	ISM_REG_BANK_0_RX_ADDR_P5 0x0F

#define	ISM_REG_BANK_0_TX_ADDR 0x10

#define	ISM_REG_BANK_0_RX_PW_P0 0x11

#define	ISM_REG_BANK_0_RX_PW_P1 0x12

#define	ISM_REG_BANK_0_RX_PW_P2 0x13

#define	ISM_REG_BANK_0_RX_PW_P3 0x14

#define	ISM_REG_BANK_0_RX_PW_P4 0x15

#define	ISM_REG_BANK_0_RX_PW_P5 0x16

#define	ISM_REG_BANK_0_FIFO_STATUS 0x17

#define	ISM_REG_BANK_0_PAYLOAD_WIDTH 0x1F

#define	ISM_REG_BANK_1_REG_0 0x00

#define	ISM_REG_BANK_1_REG_1 0x01

#define	ISM_REG_BANK_1_REG_2 0x02

#define	ISM_REG_BANK_1_REG_3 0x03

#define	ISM_REG_BANK_1_REG_4 0x04

#define	ISM_REG_BANK_1_REG_5 0x05

#define	ISM_REG_BANK_1_REG_6 0x06

#define	ISM_REG_BANK_1_REG_7 0x07

#define	ISM_REG_BANK_1_REG_8 0x08

#define	ISM_REG_BANK_1_REG_9 0x09

#define	ISM_REG_BANK_1_REG_A 0x0A

#define	ISM_REG_BANK_1_REG_B 0x0B

#define	ISM_REG_BANK_1_REG_C 0x0C

#define	ISM_REG_BANK_1_REG_D 0x0D

#define	ISM_REG_BANK_1_REG_E 0x0E

Detailed Description

List of registers of ISM Click driver.

Macro Definition Documentation

◆ ISM_REG_BANK_0_CD

#define ISM_REG_BANK_0_CD 0x09

◆ ISM_REG_BANK_0_CONFIG

#define ISM_REG_BANK_0_CONFIG 0x00

ISM description register.

Specified register for description of ISM Click driver.

◆ ISM_REG_BANK_0_EN_AA

#define ISM_REG_BANK_0_EN_AA 0x01

◆ ISM_REG_BANK_0_EN_RXADDR

#define ISM_REG_BANK_0_EN_RXADDR 0x02

◆ ISM_REG_BANK_0_FIFO_STATUS

#define ISM_REG_BANK_0_FIFO_STATUS 0x17

◆ ISM_REG_BANK_0_OBSERVE_TX

#define ISM_REG_BANK_0_OBSERVE_TX 0x08

◆ ISM_REG_BANK_0_PAYLOAD_WIDTH

#define ISM_REG_BANK_0_PAYLOAD_WIDTH 0x1F

◆ ISM_REG_BANK_0_RF_CH

#define ISM_REG_BANK_0_RF_CH 0x05

◆ ISM_REG_BANK_0_RF_SETUP

#define ISM_REG_BANK_0_RF_SETUP 0x06

◆ ISM_REG_BANK_0_RX_ADDR_P0

#define ISM_REG_BANK_0_RX_ADDR_P0 0x0A

◆ ISM_REG_BANK_0_RX_ADDR_P1

#define ISM_REG_BANK_0_RX_ADDR_P1 0x0B

◆ ISM_REG_BANK_0_RX_ADDR_P2

#define ISM_REG_BANK_0_RX_ADDR_P2 0x0C

◆ ISM_REG_BANK_0_RX_ADDR_P3

#define ISM_REG_BANK_0_RX_ADDR_P3 0x0D

◆ ISM_REG_BANK_0_RX_ADDR_P4

#define ISM_REG_BANK_0_RX_ADDR_P4 0x0E

◆ ISM_REG_BANK_0_RX_ADDR_P5

#define ISM_REG_BANK_0_RX_ADDR_P5 0x0F

◆ ISM_REG_BANK_0_RX_PW_P0

#define ISM_REG_BANK_0_RX_PW_P0 0x11

◆ ISM_REG_BANK_0_RX_PW_P1

#define ISM_REG_BANK_0_RX_PW_P1 0x12

◆ ISM_REG_BANK_0_RX_PW_P2

#define ISM_REG_BANK_0_RX_PW_P2 0x13

◆ ISM_REG_BANK_0_RX_PW_P3

#define ISM_REG_BANK_0_RX_PW_P3 0x14

◆ ISM_REG_BANK_0_RX_PW_P4

#define ISM_REG_BANK_0_RX_PW_P4 0x15

◆ ISM_REG_BANK_0_RX_PW_P5

#define ISM_REG_BANK_0_RX_PW_P5 0x16

◆ ISM_REG_BANK_0_SETUP_AW

#define ISM_REG_BANK_0_SETUP_AW 0x03

◆ ISM_REG_BANK_0_SETUP_RETR

#define ISM_REG_BANK_0_SETUP_RETR 0x04

◆ ISM_REG_BANK_0_STATUS

#define ISM_REG_BANK_0_STATUS 0x07

◆ ISM_REG_BANK_0_TX_ADDR

#define ISM_REG_BANK_0_TX_ADDR 0x10

◆ ISM_REG_BANK_1_REG_0

#define ISM_REG_BANK_1_REG_0 0x00

◆ ISM_REG_BANK_1_REG_1

#define ISM_REG_BANK_1_REG_1 0x01

◆ ISM_REG_BANK_1_REG_2

#define ISM_REG_BANK_1_REG_2 0x02

◆ ISM_REG_BANK_1_REG_3

#define ISM_REG_BANK_1_REG_3 0x03

◆ ISM_REG_BANK_1_REG_4

#define ISM_REG_BANK_1_REG_4 0x04

◆ ISM_REG_BANK_1_REG_5

#define ISM_REG_BANK_1_REG_5 0x05

◆ ISM_REG_BANK_1_REG_6

#define ISM_REG_BANK_1_REG_6 0x06

◆ ISM_REG_BANK_1_REG_7

#define ISM_REG_BANK_1_REG_7 0x07

◆ ISM_REG_BANK_1_REG_8

#define ISM_REG_BANK_1_REG_8 0x08

◆ ISM_REG_BANK_1_REG_9

#define ISM_REG_BANK_1_REG_9 0x09

◆ ISM_REG_BANK_1_REG_A

#define ISM_REG_BANK_1_REG_A 0x0A

◆ ISM_REG_BANK_1_REG_B

#define ISM_REG_BANK_1_REG_B 0x0B

◆ ISM_REG_BANK_1_REG_C

#define ISM_REG_BANK_1_REG_C 0x0C

◆ ISM_REG_BANK_1_REG_D

#define ISM_REG_BANK_1_REG_D 0x0D

◆ ISM_REG_BANK_1_REG_E

#define ISM_REG_BANK_1_REG_E 0x0E

Macros