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ism5 2.1.0.0
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Settings for registers of ISM 5 Click driver. More...
Settings for registers of ISM 5 Click driver.
| #define ISM5_CHIP_PEND_CAL 0x40 |
| #define ISM5_CHIP_PEND_CHIP_READY 0x04 |
| #define ISM5_CHIP_PEND_CMD_ERROR 0x08 |
| #define ISM5_CHIP_PEND_FIFO_UNDERFLOW_OVERFLOW_ERROR 0x20 |
| #define ISM5_CHIP_PEND_LOW_BATT 0x02 |
| #define ISM5_CHIP_PEND_STATE_CHANGE 0x10 |
| #define ISM5_CHIP_PEND_WUT 0x01 |
| #define ISM5_CHIP_STATUS_CAL 0x40 |
| #define ISM5_CHIP_STATUS_CHIP_READY 0x04 |
| #define ISM5_CHIP_STATUS_CMD_ERROR 0x08 |
| #define ISM5_CHIP_STATUS_FIFO_UNDERFLOW_OVERFLOW_ERROR 0x20 |
| #define ISM5_CHIP_STATUS_LOW_BATT 0x02 |
| #define ISM5_CHIP_STATUS_STATE_CHANGE 0x10 |
| #define ISM5_CHIP_STATUS_WUT 0x01 |
| #define ISM5_CTS_READY_BYTE 0xFF |
ISM 5 radio ready setting.
Specified setting for radio ready of ISM 5 Click driver.
| #define ISM5_CTS_READY_TIMEOUT 5000ul |
| #define ISM5_FIFO_RESET_MASK 0x03 |
| #define ISM5_FIFO_RESET_NONE 0x00 |
ISM 5 fifo reset flags setting.
Specified setting for fifo reset flags of ISM 5 Click driver.
| #define ISM5_FIFO_RESET_RX 0x02 |
| #define ISM5_FIFO_RESET_TX 0x01 |
| #define ISM5_FIFO_RESET_TX_RX 0x03 |
| #define ISM5_INT_CLEAR 0x00 |
ISM 5 interrupts setting.
Specified setting for interrupts of ISM 5 Click driver.
| #define ISM5_INT_PEND_CHIP 0x04 |
| #define ISM5_INT_PEND_MODEM 0x02 |
| #define ISM5_INT_PEND_PH 0x01 |
| #define ISM5_INT_STATUS_CHIP 0x04 |
| #define ISM5_INT_STATUS_MODEM 0x02 |
| #define ISM5_INT_STATUS_PH 0x01 |
| #define ISM5_MODEM_PEND_INVALID_PREAMBLE 0x04 |
| #define ISM5_MODEM_PEND_INVALID_SYNC 0x20 |
| #define ISM5_MODEM_PEND_POSTAMBLE_DETECT 0x40 |
| #define ISM5_MODEM_PEND_PREAMBLE_DETECT 0x02 |
| #define ISM5_MODEM_PEND_RSSI 0x08 |
| #define ISM5_MODEM_PEND_RSSI_JUMP 0x10 |
| #define ISM5_MODEM_PEND_RSSI_LATCH 0x80 |
| #define ISM5_MODEM_PEND_SYNC_DETECT 0x01 |
| #define ISM5_MODEM_STATUS_INVALID_PREAMBLE 0x04 |
| #define ISM5_MODEM_STATUS_INVALID_SYNC 0x20 |
| #define ISM5_MODEM_STATUS_POSTAMBLE_DETECT 0x40 |
| #define ISM5_MODEM_STATUS_PREAMBLE_DETECT 0x02 |
| #define ISM5_MODEM_STATUS_RSSI 0x08 |
| #define ISM5_MODEM_STATUS_RSSI_JUMP 0x10 |
| #define ISM5_MODEM_STATUS_RSSI_LATCH 0x80 |
| #define ISM5_MODEM_STATUS_SYNC_DETECT 0x01 |
| #define ISM5_PA_PWR_LVL_MAX 0x7F |
| #define ISM5_PA_PWR_LVL_MIN 0x00 |
ISM 5 PA output power level setting.
Specified setting for PA output power level of ISM 5 Click driver.
| #define ISM5_PACKET_FIXED_SIZE 0 |
| #define ISM5_PACKET_MAX_SIZE 64 |
ISM 5 packet setting.
Specified setting for packet of ISM 5 Click driver.
| #define ISM5_PACKET_TIMEOUT_1_SEC 1000 |
| #define ISM5_PACKET_TIMEOUT_DISABLE 0 |
| #define ISM5_PART_NUMBER 0x4461u |
ISM 5 part number setting.
Specified setting for part number of ISM 5 Click driver.
| #define ISM5_PH_PEND_ALT_CRC_ERROR 0x04 |
| #define ISM5_PH_PEND_CRC_ERROR 0x08 |
| #define ISM5_PH_PEND_FILTER_MATCH 0x80 |
| #define ISM5_PH_PEND_FILTER_MISS 0x40 |
| #define ISM5_PH_PEND_PACKET_RX 0x10 |
| #define ISM5_PH_PEND_PACKET_SEND 0x20 |
| #define ISM5_PH_PEND_RX_FIFO_ALMOST_FULL 0x01 |
| #define ISM5_PH_PEND_TX_FIFO_ALMOST_EMPTY 0x02 |
| #define ISM5_PH_STATUS_ALT_CRC_ERROR 0x04 |
| #define ISM5_PH_STATUS_CRC_ERROR 0x08 |
| #define ISM5_PH_STATUS_FILTER_MATCH 0x80 |
| #define ISM5_PH_STATUS_FILTER_MISS 0x40 |
| #define ISM5_PH_STATUS_PACKET_RX 0x10 |
| #define ISM5_PH_STATUS_PACKET_SEND 0x20 |
| #define ISM5_PH_STATUS_RX_FIFO_ALMOST_FULL 0x01 |
| #define ISM5_PH_STATUS_TX_FIFO_ALMOST_EMPTY 0x02 |
| #define ISM5_POWER_UP_BOOT_FUNCTIONAL 1 |
ISM 5 power up setting.
Specified setting for power up of ISM 5 Click driver.
| #define ISM5_POWER_UP_SELECT_TCXO 1 |
| #define ISM5_POWER_UP_TCXO_26MHZ 26000000ul |
| #define ISM5_PROPERTY_FREQ_CONTROL_CHANNEL_STEP_SIZE_0 0x4005 |
| #define ISM5_PROPERTY_FREQ_CONTROL_CHANNEL_STEP_SIZE_1 0x4004 |
| #define ISM5_PROPERTY_FREQ_CONTROL_FRAC_0 0x4003 |
| #define ISM5_PROPERTY_FREQ_CONTROL_FRAC_1 0x4002 |
| #define ISM5_PROPERTY_FREQ_CONTROL_FRAC_2 0x4001 |
| #define ISM5_PROPERTY_FREQ_CONTROL_INTE 0x4000 |
| #define ISM5_PROPERTY_FREQ_CONTROL_VCOCNT_RX_ADJ 0x4007 |
| #define ISM5_PROPERTY_FREQ_CONTROL_W_SIZE 0x4006 |
| #define ISM5_PROPERTY_FRR_CTL_A_MODE 0x0200 |
| #define ISM5_PROPERTY_FRR_CTL_B_MODE 0x0201 |
| #define ISM5_PROPERTY_FRR_CTL_C_MODE 0x0202 |
| #define ISM5_PROPERTY_FRR_CTL_D_MODE 0x0203 |
| #define ISM5_PROPERTY_GLOBAL_CLK_CFG 0x0001 |
| #define ISM5_PROPERTY_GLOBAL_CONFIG 0x0003 |
| #define ISM5_PROPERTY_GLOBAL_LOW_BATT_THRESH 0x0001 |
| #define ISM5_PROPERTY_GLOBAL_WUT_CAL 0x0009 |
| #define ISM5_PROPERTY_GLOBAL_WUT_CONFIG 0x0004 |
| #define ISM5_PROPERTY_GLOBAL_WUT_LDC 0x0008 |
| #define ISM5_PROPERTY_GLOBAL_WUT_M_15_8 0x0005 |
| #define ISM5_PROPERTY_GLOBAL_WUT_M_7_0 0x0006 |
| #define ISM5_PROPERTY_GLOBAL_WUT_R 0x0007 |
| #define ISM5_PROPERTY_GLOBAL_XO_TUNE 0x0000 |
ISM 5 property index setting.
Specified setting for property index of ISM 5 Click driver.
| #define ISM5_PROPERTY_INT_CTL_CHIP_ENABLE 0x0103 |
| #define ISM5_PROPERTY_INT_CTL_ENABLE 0x0100 |
| #define ISM5_PROPERTY_INT_CTL_MODEM_ENABLE 0x0102 |
| #define ISM5_PROPERTY_INT_CTL_PH_ENABLE 0x0101 |
| #define ISM5_PROPERTY_MATCH_CTRL_1 0x3002 |
| #define ISM5_PROPERTY_MATCH_CTRL_2 0x3005 |
| #define ISM5_PROPERTY_MATCH_CTRL_3 0x3008 |
| #define ISM5_PROPERTY_MATCH_CTRL_4 0x300B |
| #define ISM5_PROPERTY_MATCH_MASK_1 0x3001 |
| #define ISM5_PROPERTY_MATCH_MASK_2 0x3004 |
| #define ISM5_PROPERTY_MATCH_MASK_3 0x3007 |
| #define ISM5_PROPERTY_MATCH_MASK_4 0x300A |
| #define ISM5_PROPERTY_MATCH_VALUE_1 0x3000 |
| #define ISM5_PROPERTY_MATCH_VALUE_2 0x3003 |
| #define ISM5_PROPERTY_MATCH_VALUE_3 0x3006 |
| #define ISM5_PROPERTY_MATCH_VALUE_4 0x3009 |
| #define ISM5_PROPERTY_MODEM_ADC_CTRL 0x2034 |
| #define ISM5_PROPERTY_MODEM_AFC_GAIN_0 0x202F |
| #define ISM5_PROPERTY_MODEM_AFC_GAIN_1 0x202E |
| #define ISM5_PROPERTY_MODEM_AFC_GEAR 0x202C |
| #define ISM5_PROPERTY_MODEM_AFC_LIMITER_0 0x2031 |
| #define ISM5_PROPERTY_MODEM_AFC_LIMITER_1 0x2030 |
| #define ISM5_PROPERTY_MODEM_AFC_MISC 0x2032 |
| #define ISM5_PROPERTY_MODEM_AFC_WAIT 0x202D |
| #define ISM5_PROPERTY_MODEM_AFC_ZIFOFF 0x2033 |
| #define ISM5_PROPERTY_MODEM_AGC_CONTROL 0x2035 |
| #define ISM5_PROPERTY_MODEM_AGC_IFPD_DECAY 0x203A |
| #define ISM5_PROPERTY_MODEM_AGC_RFPD_DECAY 0x2039 |
| #define ISM5_PROPERTY_MODEM_AGC_WINDOW_SIZE 0x2038 |
| #define ISM5_PROPERTY_MODEM_ANT_DIV_CONTROL 0x2049 |
| #define ISM5_PROPERTY_MODEM_ANT_DIV_MODE 0x2048 |
| #define ISM5_PROPERTY_MODEM_BCR_GAIN_0 0x2028 |
| #define ISM5_PROPERTY_MODEM_BCR_GAIN_1 0x2027 |
| #define ISM5_PROPERTY_MODEM_BCR_GEAR 0x2029 |
| #define ISM5_PROPERTY_MODEM_BCR_MISC0 0x202B |
| #define ISM5_PROPERTY_MODEM_BCR_MISC1 0x202A |
| #define ISM5_PROPERTY_MODEM_BCR_NCO_OFFSET_0 0x2026 |
| #define ISM5_PROPERTY_MODEM_BCR_NCO_OFFSET_1 0x2025 |
| #define ISM5_PROPERTY_MODEM_BCR_NCO_OFFSET_2 0x2024 |
| #define ISM5_PROPERTY_MODEM_BCR_OSR_0 0x2023 |
| #define ISM5_PROPERTY_MODEM_BCR_OSR_1 0x2022 |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX1_CHFLT_COE0_7_0 0x210D |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX1_CHFLT_COE10_7_0 0x2103 |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX1_CHFLT_COE11_7_0 0x2102 |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX1_CHFLT_COE12_7_0 0x2101 |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX1_CHFLT_COE13_7_0 0x2100 |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX1_CHFLT_COE1_7_0 0x210C |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX1_CHFLT_COE2_7_0 0x210B |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX1_CHFLT_COE3_7_0 0x210A |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX1_CHFLT_COE4_7_0 0x2109 |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX1_CHFLT_COE5_7_0 0x2108 |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX1_CHFLT_COE6_7_0 0x2107 |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX1_CHFLT_COE7_7_0 0x2106 |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX1_CHFLT_COE8_7_0 0x2105 |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX1_CHFLT_COE9_7_0 0x2104 |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX1_CHFLT_COEM0 0x210E |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX1_CHFLT_COEM1 0x210F |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX1_CHFLT_COEM2 0x2110 |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX1_CHFLT_COEM3 0x2111 |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX2_CHFLT_COE0_7_0 0x211F |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX2_CHFLT_COE10_7_0 0x2115 |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX2_CHFLT_COE11_7_0 0x2114 |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX2_CHFLT_COE12_7_0 0x2113 |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX2_CHFLT_COE13_7_0 0x2112 |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX2_CHFLT_COE1_7_0 0x211E |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX2_CHFLT_COE2_7_0 0x211D |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX2_CHFLT_COE3_7_0 0x211C |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX2_CHFLT_COE4_7_0 0x211B |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX2_CHFLT_COE5_7_0 0x211A |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX2_CHFLT_COE6_7_0 0x2119 |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX2_CHFLT_COE7_7_0 0x2118 |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX2_CHFLT_COE8_7_0 0x2117 |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX2_CHFLT_COE9_7_0 0x2116 |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX2_CHFLT_COEM0 0x2120 |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX2_CHFLT_COEM1 0x2121 |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX2_CHFLT_COEM2 0x2122 |
| #define ISM5_PROPERTY_MODEM_CHFLT_RX2_CHFLT_COEM3 0x2123 |
| #define ISM5_PROPERTY_MODEM_CLKGEN_BAND 0x2051 |
| #define ISM5_PROPERTY_MODEM_DATA_RATE_0 0x2005 |
| #define ISM5_PROPERTY_MODEM_DATA_RATE_1 0x2004 |
| #define ISM5_PROPERTY_MODEM_DATA_RATE_2 0x2003 |
| #define ISM5_PROPERTY_MODEM_DECIMATION_CFG0 0x201F |
| #define ISM5_PROPERTY_MODEM_DECIMATION_CFG1 0x201E |
| #define ISM5_PROPERTY_MODEM_FREQ_DEV_0 0x200C |
| #define ISM5_PROPERTY_MODEM_FREQ_DEV_1 0x200B |
| #define ISM5_PROPERTY_MODEM_FREQ_DEV_2 0x200A |
| #define ISM5_PROPERTY_MODEM_FREQ_OFFSET_0 0x200E |
| #define ISM5_PROPERTY_MODEM_FREQ_OFFSET_1 0x200D |
| #define ISM5_PROPERTY_MODEM_FSK4_GAIN0 0x203C |
| #define ISM5_PROPERTY_MODEM_FSK4_GAIN1 0x203B |
| #define ISM5_PROPERTY_MODEM_FSK4_MAP 0x203F |
| #define ISM5_PROPERTY_MODEM_FSK4_TH0 0x203E |
| #define ISM5_PROPERTY_MODEM_FSK4_TH1 0x203D |
| #define ISM5_PROPERTY_MODEM_IF_CONTROL 0x201A |
| #define ISM5_PROPERTY_MODEM_IF_FREQ_0 0x201D |
| #define ISM5_PROPERTY_MODEM_IF_FREQ_1 0x201C |
| #define ISM5_PROPERTY_MODEM_IF_FREQ_2 0x201B |
| #define ISM5_PROPERTY_MODEM_MAP_CONTROL 0x2001 |
| #define ISM5_PROPERTY_MODEM_MDM_CTRL 0x2019 |
| #define ISM5_PROPERTY_MODEM_MOD_TYPE 0x2000 |
| #define ISM5_PROPERTY_MODEM_OOK_BLOPK 0x2041 |
| #define ISM5_PROPERTY_MODEM_OOK_CNT1 0x2042 |
| #define ISM5_PROPERTY_MODEM_OOK_MISC 0x2043 |
| #define ISM5_PROPERTY_MODEM_OOK_PDTC 0x2040 |
| #define ISM5_PROPERTY_MODEM_RAW_CONTROL 0x2045 |
| #define ISM5_PROPERTY_MODEM_RAW_EYE_0 0x2047 |
| #define ISM5_PROPERTY_MODEM_RAW_EYE_1 0x2046 |
| #define ISM5_PROPERTY_MODEM_RAW_SEARCH 0x2044 |
| #define ISM5_PROPERTY_MODEM_RSSI_COMP 0x204E |
| #define ISM5_PROPERTY_MODEM_RSSI_CONTROL 0x204C |
| #define ISM5_PROPERTY_MODEM_RSSI_CONTROL2 0x204D |
| #define ISM5_PROPERTY_MODEM_RSSI_JUMP_THRESH 0x204B |
| #define ISM5_PROPERTY_MODEM_RSSI_THRESH 0x204A |
| #define ISM5_PROPERTY_MODEM_TX_FILTER_COEFF_0 0x2017 |
| #define ISM5_PROPERTY_MODEM_TX_FILTER_COEFF_1 0x2016 |
| #define ISM5_PROPERTY_MODEM_TX_FILTER_COEFF_2 0x2015 |
| #define ISM5_PROPERTY_MODEM_TX_FILTER_COEFF_3 0x2014 |
| #define ISM5_PROPERTY_MODEM_TX_FILTER_COEFF_4 0x2013 |
| #define ISM5_PROPERTY_MODEM_TX_FILTER_COEFF_5 0x2012 |
| #define ISM5_PROPERTY_MODEM_TX_FILTER_COEFF_6 0x2011 |
| #define ISM5_PROPERTY_MODEM_TX_FILTER_COEFF_7 0x2010 |
| #define ISM5_PROPERTY_MODEM_TX_FILTER_COEFF_8 0x200F |
| #define ISM5_PROPERTY_MODEM_TX_NCO_MODE_0 0x2009 |
| #define ISM5_PROPERTY_MODEM_TX_NCO_MODE_1 0x2008 |
| #define ISM5_PROPERTY_MODEM_TX_NCO_MODE_2 0x2007 |
| #define ISM5_PROPERTY_MODEM_TX_NCO_MODE_3 0x2006 |
| #define ISM5_PROPERTY_MODEM_TX_RAMP_DELAY 0x2018 |
| #define ISM5_PROPERTY_PA_BIAS_CLKDUTY 0x2202 |
| #define ISM5_PROPERTY_PA_MODE 0x2200 |
| #define ISM5_PROPERTY_PA_PWR_LVL 0x2201 |
| #define ISM5_PROPERTY_PA_RAMP_DOWN_DELAY 0x2205 |
| #define ISM5_PROPERTY_PA_RAMP_EX 0x2204 |
| #define ISM5_PROPERTY_PA_TC 0x2203 |
| #define ISM5_PROPERTY_PKT_CONFIG1 0x1206 |
| #define ISM5_PROPERTY_PKT_CRC_CONFIG 0x1200 |
| #define ISM5_PROPERTY_PKT_FIELD_1_CONFIG 0x120F |
| #define ISM5_PROPERTY_PKT_FIELD_1_CRC_CONFIG 0x1210 |
| #define ISM5_PROPERTY_PKT_FIELD_1_LENGTH_12_8 0x120D |
| #define ISM5_PROPERTY_PKT_FIELD_1_LENGTH_7_0 0x120E |
| #define ISM5_PROPERTY_PKT_FIELD_2_CONFIG 0x1213 |
| #define ISM5_PROPERTY_PKT_FIELD_2_CRC_CONFIG 0x1214 |
| #define ISM5_PROPERTY_PKT_FIELD_2_LENGTH_12_8 0x1211 |
| #define ISM5_PROPERTY_PKT_FIELD_2_LENGTH_7_0 0x1212 |
| #define ISM5_PROPERTY_PKT_FIELD_3_CONFIG 0x1217 |
| #define ISM5_PROPERTY_PKT_FIELD_3_CRC_CONFIG 0x1218 |
| #define ISM5_PROPERTY_PKT_FIELD_3_LENGTH_12_8 0x1215 |
| #define ISM5_PROPERTY_PKT_FIELD_3_LENGTH_7_0 0x1216 |
| #define ISM5_PROPERTY_PKT_FIELD_4_CONFIG 0x121B |
| #define ISM5_PROPERTY_PKT_FIELD_4_CRC_CONFIG 0x121C |
| #define ISM5_PROPERTY_PKT_FIELD_4_LENGTH_12_8 0x1219 |
| #define ISM5_PROPERTY_PKT_FIELD_4_LENGTH_7_0 0x121A |
| #define ISM5_PROPERTY_PKT_FIELD_5_CONFIG 0x121F |
| #define ISM5_PROPERTY_PKT_FIELD_5_CRC_CONFIG 0x1220 |
| #define ISM5_PROPERTY_PKT_FIELD_5_LENGTH_12_8 0x121D |
| #define ISM5_PROPERTY_PKT_FIELD_5_LENGTH_7_0 0x121E |
| #define ISM5_PROPERTY_PKT_LEN 0x1208 |
| #define ISM5_PROPERTY_PKT_LEN_ADJUST 0x120A |
| #define ISM5_PROPERTY_PKT_LEN_FIELD_SOURCE 0x1209 |
| #define ISM5_PROPERTY_PKT_RX_FIELD_1_CONFIG 0x1223 |
| #define ISM5_PROPERTY_PKT_RX_FIELD_1_CRC_CONFIG 0x1224 |
| #define ISM5_PROPERTY_PKT_RX_FIELD_1_LENGTH_12_8 0x1221 |
| #define ISM5_PROPERTY_PKT_RX_FIELD_1_LENGTH_7_0 0x1222 |
| #define ISM5_PROPERTY_PKT_RX_FIELD_2_CONFIG 0x1227 |
| #define ISM5_PROPERTY_PKT_RX_FIELD_2_CRC_CONFIG 0x1228 |
| #define ISM5_PROPERTY_PKT_RX_FIELD_2_LENGTH_12_8 0x1225 |
| #define ISM5_PROPERTY_PKT_RX_FIELD_2_LENGTH_7_0 0x1226 |
| #define ISM5_PROPERTY_PKT_RX_FIELD_3_CONFIG 0x122B |
| #define ISM5_PROPERTY_PKT_RX_FIELD_3_CRC_CONFIG 0x122C |
| #define ISM5_PROPERTY_PKT_RX_FIELD_3_LENGTH_12_8 0x1229 |
| #define ISM5_PROPERTY_PKT_RX_FIELD_3_LENGTH_7_0 0x122A |
| #define ISM5_PROPERTY_PKT_RX_FIELD_4_CONFIG 0x122F |
| #define ISM5_PROPERTY_PKT_RX_FIELD_4_CRC_CONFIG 0x1230 |
| #define ISM5_PROPERTY_PKT_RX_FIELD_4_LENGTH_12_8 0x122D |
| #define ISM5_PROPERTY_PKT_RX_FIELD_4_LENGTH_7_0 0x122E |
| #define ISM5_PROPERTY_PKT_RX_FIELD_5_CONFIG 0x1233 |
| #define ISM5_PROPERTY_PKT_RX_FIELD_5_CRC_CONFIG 0x1234 |
| #define ISM5_PROPERTY_PKT_RX_FIELD_5_LENGTH_12_8 0x1231 |
| #define ISM5_PROPERTY_PKT_RX_FIELD_5_LENGTH_7_0 0x1232 |
| #define ISM5_PROPERTY_PKT_RX_THRESHOLD 0x120C |
| #define ISM5_PROPERTY_PKT_TX_THRESHOLD 0x120B |
| #define ISM5_PROPERTY_PREAMBLE_CONFIG 0x1004 |
| #define ISM5_PROPERTY_PREAMBLE_CONFIG_NSTD 0x1002 |
| #define ISM5_PROPERTY_PREAMBLE_CONFIG_STD_1 0x1001 |
| #define ISM5_PROPERTY_PREAMBLE_CONFIG_STD_2 0x1003 |
| #define ISM5_PROPERTY_PREAMBLE_PATTERN_15_8 0x1007 |
| #define ISM5_PROPERTY_PREAMBLE_PATTERN_23_16 0x1006 |
| #define ISM5_PROPERTY_PREAMBLE_PATTERN_31_24 0x1005 |
| #define ISM5_PROPERTY_PREAMBLE_PATTERN_7_0 0x1008 |
| #define ISM5_PROPERTY_PREAMBLE_POSTAMBLE_CONFIG 0x1009 |
| #define ISM5_PROPERTY_PREAMBLE_POSTAMBLE_PATTERN_15_8 0x100C |
| #define ISM5_PROPERTY_PREAMBLE_POSTAMBLE_PATTERN_23_16 0x100B |
| #define ISM5_PROPERTY_PREAMBLE_POSTAMBLE_PATTERN_31_24 0x100A |
| #define ISM5_PROPERTY_PREAMBLE_POSTAMBLE_PATTERN_7_0 0x100D |
| #define ISM5_PROPERTY_PREAMBLE_TX_LENGTH 0x1000 |
| #define ISM5_PROPERTY_RX_HOP_CONTROL 0x5000 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_0 0x5002 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_1 0x5003 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_10 0x500C |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_11 0x500D |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_12 0x500E |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_13 0x500F |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_14 0x5010 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_15 0x5011 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_16 0x5012 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_17 0x5013 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_18 0x5014 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_19 0x5015 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_2 0x5004 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_20 0x5016 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_21 0x5017 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_22 0x5018 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_23 0x5019 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_24 0x501A |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_25 0x501B |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_26 0x501C |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_27 0x501D |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_28 0x501E |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_29 0x501F |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_3 0x5005 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_30 0x5020 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_31 0x5021 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_32 0x5022 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_33 0x5023 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_34 0x5024 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_35 0x5025 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_36 0x5026 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_37 0x5027 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_38 0x5028 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_39 0x5029 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_4 0x5006 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_40 0x502A |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_41 0x502B |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_42 0x502C |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_43 0x502D |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_44 0x502E |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_45 0x502F |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_46 0x5030 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_47 0x5031 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_48 0x5032 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_49 0x5033 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_5 0x5007 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_50 0x5034 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_51 0x5035 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_52 0x5036 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_53 0x5037 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_54 0x5038 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_55 0x5039 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_56 0x503A |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_57 0x503B |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_58 0x503C |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_59 0x503D |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_6 0x5008 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_60 0x503E |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_61 0x503F |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_62 0x5040 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_63 0x5041 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_7 0x5009 |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_8 0x500A |
| #define ISM5_PROPERTY_RX_HOP_TABLE_ENTRY_9 0x500B |
| #define ISM5_PROPERTY_RX_HOP_TABLE_SIZE 0x5001 |
| #define ISM5_PROPERTY_SYNC_BITS_15_8 0x1103 |
| #define ISM5_PROPERTY_SYNC_BITS_23_16 0x1102 |
| #define ISM5_PROPERTY_SYNC_BITS_31_24 0x1101 |
| #define ISM5_PROPERTY_SYNC_BITS_7_0 0x1104 |
| #define ISM5_PROPERTY_SYNC_CONFIG 0x1100 |
| #define ISM5_PROPERTY_SYNTH_LPFILT0 0x2306 |
| #define ISM5_PROPERTY_SYNTH_LPFILT1 0x2305 |
| #define ISM5_PROPERTY_SYNTH_LPFILT2 0x2304 |
| #define ISM5_PROPERTY_SYNTH_LPFILT3 0x2303 |
| #define ISM5_PROPERTY_SYNTH_PFDCP_CPFF 0x2300 |
| #define ISM5_PROPERTY_SYNTH_PFDCP_CPINT 0x2301 |
| #define ISM5_PROPERTY_SYNTH_VCO_KV 0x2302 |
| #define ISM5_PROPERTY_SYNTH_VCO_KVCAL 0x2307 |
| #define ISM5_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE |
Data sample selection.
This macro sets data samples for SPI modules.
| #define ISM5_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE |
| #define ISM5_STATE_MASK 0x0F |
| #define ISM5_STATE_NO_CHANGE 0x00 |
ISM 5 operating state setting.
Specified setting for operating state of ISM 5 Click driver.
| #define ISM5_STATE_READY 0x03 |
| #define ISM5_STATE_RX 0x08 |
| #define ISM5_STATE_RX_TUNE 0x06 |
| #define ISM5_STATE_SLEEP 0x01 |
| #define ISM5_STATE_SPI_ACTIVE 0x02 |
| #define ISM5_STATE_TX 0x07 |
| #define ISM5_STATE_TX_TUNE 0x05 |