ism5 2.1.0.0
ism5_radio_config.h
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1
14#ifndef RADIO_CONFIG_H_
15#define RADIO_CONFIG_H_
16
17// USER DEFINED PARAMETERS
18// Define your own parameters here
19
20// INPUT DATA
21/*
22// Crys_freq(Hz): 26000000 Crys_tol(ppm): 20 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0
23// MOD_type: 2 Rsymb(sps): 10000 Fdev(Hz): 20000 RXBW(Hz): 150000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2
24// RF Freq.(MHz): 868 API_TC: 29 fhst: 250000 inputBW: 0 BERT: 0 RAW_dout: 0 D_source: 0 Hi_pfm_div: 1
25// API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 0
26//
27// # RX IF frequency is -406250 Hz
28// # WB filter 2 (BW = 119.09 kHz); NB-filter 2 (BW = 119.09 kHz)
29//
30// Modulation index: 4
31*/
32
33
34// CONFIGURATION PARAMETERS
35#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ 26000000L
36#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER 0x00
37#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH 0x07
38#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP 0x03
39#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET 0xF000
40
41#include "ism5_patch.h"
42
43
44// CONFIGURATION COMMANDS
45
46/*
47// Command: RF_POWER_UP
48// Description: Command to power-up the device and select the operational mode and functionality.
49*/
50#define RF_POWER_UP 0x02, 0x81, 0x01, 0x01, 0x8C, 0xBA, 0x80
51
52/*
53// Command: RF_GPIO_PIN_CFG
54// Description: Configures the GPIO pins.
55*/
56#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
57
58/*
59// Set properties: RF_GLOBAL_XO_TUNE_2
60// Number of properties: 2
61// Group ID: 0x00
62// Start ID: 0x00
63// Default values: 0x40, 0x00,
64// Descriptions:
65// GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
66// GLOBAL_CLK_CFG - Clock configuration options.
67*/
68#define RF_GLOBAL_XO_TUNE_2 0x11, 0x00, 0x02, 0x00, 0x00, 0x00
69
70/*
71// Set properties: RF_GLOBAL_CONFIG_1
72// Number of properties: 1
73// Group ID: 0x00
74// Start ID: 0x03
75// Default values: 0x20,
76// Descriptions:
77// GLOBAL_CONFIG - Global configuration settings.
78*/
79#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x20
80
81/*
82// Set properties: RF_INT_CTL_ENABLE_2
83// Number of properties: 2
84// Group ID: 0x01
85// Start ID: 0x00
86// Default values: 0x04, 0x00,
87// Descriptions:
88// INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
89// INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
90*/
91#define RF_INT_CTL_ENABLE_2 0x11, 0x01, 0x02, 0x00, 0x01, 0x10
92
93/*
94// Set properties: RF_FRR_CTL_A_MODE_4
95// Number of properties: 4
96// Group ID: 0x02
97// Start ID: 0x00
98// Default values: 0x01, 0x02, 0x09, 0x00,
99// Descriptions:
100// FRR_CTL_A_MODE - Fast Response Register A Configuration.
101// FRR_CTL_B_MODE - Fast Response Register B Configuration.
102// FRR_CTL_C_MODE - Fast Response Register C Configuration.
103// FRR_CTL_D_MODE - Fast Response Register D Configuration.
104*/
105#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00
106
107/*
108// Set properties: RF_PREAMBLE_TX_LENGTH_9
109// Number of properties: 9
110// Group ID: 0x10
111// Start ID: 0x00
112// Default values: 0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00,
113// Descriptions:
114// PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
115// PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
116// PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.
117// PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern.
118// PREAMBLE_CONFIG - General configuration bits for the Preamble field.
119// PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern.
120// PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern.
121// PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern.
122// PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern.
123*/
124#define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x08, 0x14, 0x00, 0x0F, 0x31, 0x00, 0x00, 0x00, 0x00
125
126/*
127// Set properties: RF_SYNC_CONFIG_6
128// Number of properties: 6
129// Group ID: 0x11
130// Start ID: 0x00
131// Default values: 0x01, 0x2D, 0xD4, 0x2D, 0xD4, 0x00,
132// Descriptions:
133// SYNC_CONFIG - Sync Word configuration bits.
134// SYNC_BITS_31_24 - Sync word.
135// SYNC_BITS_23_16 - Sync word.
136// SYNC_BITS_15_8 - Sync word.
137// SYNC_BITS_7_0 - Sync word.
138// SYNC_CONFIG2 - Sync Word configuration bits.
139*/
140#define RF_SYNC_CONFIG_6 0x11, 0x11, 0x06, 0x00, 0x01, 0xB4, 0x2B, 0x00, 0x00, 0x00
141
142/*
143// Set properties: RF_PKT_CRC_CONFIG_12
144// Number of properties: 12
145// Group ID: 0x12
146// Start ID: 0x00
147// Default values: 0x00, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
148// Descriptions:
149// PKT_CRC_CONFIG - Select a CRC polynomial and seed.
150// PKT_WHT_POLY_15_8 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
151// PKT_WHT_POLY_7_0 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
152// PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
153// PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
154// PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.
155// PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
156// PKT_CONFIG2 - General packet configuration bits.
157// PKT_LEN - Configuration bits for reception of a variable length packet.
158// PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s).
159// PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length).
160// PKT_TX_THRESHOLD - TX FIFO almost empty threshold.
161*/
162#define RF_PKT_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x02, 0x00, 0x00, 0x00, 0x00, 0x30
163
164/*
165// Set properties: RF_PKT_RX_THRESHOLD_12
166// Number of properties: 12
167// Group ID: 0x12
168// Start ID: 0x0C
169// Default values: 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
170// Descriptions:
171// PKT_RX_THRESHOLD - RX FIFO Almost Full threshold.
172// PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value.
173// PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value.
174// PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
175// PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1.
176// PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value.
177// PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value.
178// PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2.
179// PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2.
180// PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value.
181// PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value.
182// PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3.
183*/
184#define RF_PKT_RX_THRESHOLD_12 0x11, 0x12, 0x0C, 0x0C, 0x30, 0x00, 0x40, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
185
186/*
187// Set properties: RF_PKT_FIELD_3_CRC_CONFIG_12
188// Number of properties: 12
189// Group ID: 0x12
190// Start ID: 0x18
191// Default values: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
192// Descriptions:
193// PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3.
194// PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value.
195// PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value.
196// PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4.
197// PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4.
198// PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value.
199// PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value.
200// PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5.
201// PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5.
202// PKT_RX_FIELD_1_LENGTH_12_8 - Unsigned 13-bit RX Field 1 length value.
203// PKT_RX_FIELD_1_LENGTH_7_0 - Unsigned 13-bit RX Field 1 length value.
204// PKT_RX_FIELD_1_CONFIG - General data processing and packet configuration bits for RX Field 1.
205*/
206#define RF_PKT_FIELD_3_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
207
208/*
209// Set properties: RF_PKT_RX_FIELD_1_CRC_CONFIG_12
210// Number of properties: 12
211// Group ID: 0x12
212// Start ID: 0x24
213// Default values: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
214// Descriptions:
215// PKT_RX_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across RX Field 1.
216// PKT_RX_FIELD_2_LENGTH_12_8 - Unsigned 13-bit RX Field 2 length value.
217// PKT_RX_FIELD_2_LENGTH_7_0 - Unsigned 13-bit RX Field 2 length value.
218// PKT_RX_FIELD_2_CONFIG - General data processing and packet configuration bits for RX Field 2.
219// PKT_RX_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across RX Field 2.
220// PKT_RX_FIELD_3_LENGTH_12_8 - Unsigned 13-bit RX Field 3 length value.
221// PKT_RX_FIELD_3_LENGTH_7_0 - Unsigned 13-bit RX Field 3 length value.
222// PKT_RX_FIELD_3_CONFIG - General data processing and packet configuration bits for RX Field 3.
223// PKT_RX_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across RX Field 3.
224// PKT_RX_FIELD_4_LENGTH_12_8 - Unsigned 13-bit RX Field 4 length value.
225// PKT_RX_FIELD_4_LENGTH_7_0 - Unsigned 13-bit RX Field 4 length value.
226// PKT_RX_FIELD_4_CONFIG - General data processing and packet configuration bits for RX Field 4.
227*/
228#define RF_PKT_RX_FIELD_1_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
229
230/*
231// Set properties: RF_PKT_RX_FIELD_4_CRC_CONFIG_5
232// Number of properties: 5
233// Group ID: 0x12
234// Start ID: 0x30
235// Default values: 0x00, 0x00, 0x00, 0x00, 0x00,
236// Descriptions:
237// PKT_RX_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across RX Field 4.
238// PKT_RX_FIELD_5_LENGTH_12_8 - Unsigned 13-bit RX Field 5 length value.
239// PKT_RX_FIELD_5_LENGTH_7_0 - Unsigned 13-bit RX Field 5 length value.
240// PKT_RX_FIELD_5_CONFIG - General data processing and packet configuration bits for RX Field 5.
241// PKT_RX_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across RX Field 5.
242*/
243#define RF_PKT_RX_FIELD_4_CRC_CONFIG_5 0x11, 0x12, 0x05, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00
244
245/*
246// Set properties: RF_PKT_CRC_SEED_31_24_4
247// Number of properties: 4
248// Group ID: 0x12
249// Start ID: 0x36
250// Default values: 0x00, 0x00, 0x00, 0x00,
251// Descriptions:
252// PKT_CRC_SEED_31_24 - 32-bit seed value for the 32-bit CRC engine
253// PKT_CRC_SEED_23_16 - 32-bit seed value for the 32-bit CRC engine
254// PKT_CRC_SEED_15_8 - 32-bit seed value for the 32-bit CRC engine
255// PKT_CRC_SEED_7_0 - 32-bit seed value for the 32-bit CRC engine
256*/
257#define RF_PKT_CRC_SEED_31_24_4 0x11, 0x12, 0x04, 0x36, 0x00, 0x00, 0x00, 0x00
258
259/*
260// Set properties: RF_MODEM_MOD_TYPE_12
261// Number of properties: 12
262// Group ID: 0x20
263// Start ID: 0x00
264// Default values: 0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06,
265// Descriptions:
266// MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
267// MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
268// MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
269// MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
270// MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
271// MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
272// MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
273// MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
274// MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
275// MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
276// MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
277// MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
278*/
279#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x02, 0x00, 0x07, 0x01, 0x86, 0xA0, 0x01, 0x8C, 0xBA, 0x80, 0x00, 0x03
280
281/*
282// Set properties: RF_MODEM_FREQ_DEV_0_1
283// Number of properties: 1
284// Group ID: 0x20
285// Start ID: 0x0C
286// Default values: 0xD3,
287// Descriptions:
288// MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
289*/
290#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x27
291
292/*
293// Set properties: RF_MODEM_TX_RAMP_DELAY_12
294// Number of properties: 12
295// Group ID: 0x20
296// Start ID: 0x18
297// Default values: 0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B,
298// Descriptions:
299// MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
300// MODEM_MDM_CTRL - MDM control.
301// MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
302// MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
303// MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
304// MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
305// MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
306// MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
307// MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
308// MODEM_IFPKD_THRESHOLDS -
309// MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
310// MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
311*/
312#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x80, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x10, 0x00, 0xE8, 0x01, 0xB1
313
314/*
315// Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12
316// Number of properties: 12
317// Group ID: 0x20
318// Start ID: 0x24
319// Default values: 0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69,
320// Descriptions:
321// MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
322// MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
323// MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
324// MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
325// MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
326// MODEM_BCR_GEAR - RX BCR loop gear control.
327// MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
328// MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
329// MODEM_AFC_GEAR - RX AFC loop gear control.
330// MODEM_AFC_WAIT - RX AFC loop wait time control.
331// MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
332// MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
333*/
334#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x01, 0x2E, 0x79, 0x00, 0x97, 0x02, 0xC2, 0x00, 0x04, 0x23, 0x80, 0x11
335
336/*
337// Set properties: RF_MODEM_AFC_LIMITER_1_3
338// Number of properties: 3
339// Group ID: 0x20
340// Start ID: 0x30
341// Default values: 0x00, 0x40, 0xA0,
342// Descriptions:
343// MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
344// MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
345// MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
346*/
347#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x16, 0x97, 0x80
348
349/*
350// Set properties: RF_MODEM_AGC_CONTROL_1
351// Number of properties: 1
352// Group ID: 0x20
353// Start ID: 0x35
354// Default values: 0xE0,
355// Descriptions:
356// MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
357*/
358#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE0
359
360/*
361// Set properties: RF_MODEM_AGC_WINDOW_SIZE_12
362// Number of properties: 12
363// Group ID: 0x20
364// Start ID: 0x38
365// Default values: 0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03,
366// Descriptions:
367// MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
368// MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
369// MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
370// MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
371// MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
372// MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
373// MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
374// MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
375// MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
376// MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
377// MODEM_OOK_CNT1 - OOK control.
378// MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
379*/
380#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x5F, 0x5F, 0x80, 0x02, 0xFF, 0xFF, 0x00, 0x2A, 0x0C, 0xA4, 0x22
381
382/*
383// Set properties: RF_MODEM_RAW_CONTROL_10
384// Number of properties: 10
385// Group ID: 0x20
386// Start ID: 0x45
387// Default values: 0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01, 0x00, 0x40,
388// Descriptions:
389// MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
390// MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
391// MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
392// MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
393// MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
394// MODEM_RSSI_THRESH - Configures the RSSI threshold.
395// MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
396// MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
397// MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
398// MODEM_RSSI_COMP - RSSI compensation value.
399*/
400#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x83, 0x01, 0x27, 0x01, 0x00, 0xFF, 0x06, 0x00, 0x18, 0x40
401
402/*
403// Set properties: RF_MODEM_RAW_SEARCH2_2
404// Number of properties: 2
405// Group ID: 0x20
406// Start ID: 0x50
407// Default values: 0x00, 0x08,
408// Descriptions:
409// MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
410// MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
411*/
412#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x84, 0x08
413
414/*
415// Set properties: RF_MODEM_SPIKE_DET_2
416// Number of properties: 2
417// Group ID: 0x20
418// Start ID: 0x54
419// Default values: 0x00, 0x00,
420// Descriptions:
421// MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
422// MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
423*/
424#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x04, 0x07
425
426/*
427// Set properties: RF_MODEM_RSSI_MUTE_1
428// Number of properties: 1
429// Group ID: 0x20
430// Start ID: 0x57
431// Default values: 0x00,
432// Descriptions:
433// MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
434*/
435#define RF_MODEM_RSSI_MUTE_1 0x11, 0x20, 0x01, 0x57, 0x00
436
437/*
438// Set properties: RF_MODEM_DSA_CTRL1_5
439// Number of properties: 5
440// Group ID: 0x20
441// Start ID: 0x5B
442// Default values: 0x00, 0x00, 0x00, 0x00, 0x00,
443// Descriptions:
444// MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
445// MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
446// MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
447// MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
448// MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
449*/
450#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0B, 0x78, 0x20
451
452/*
453// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
454// Number of properties: 12
455// Group ID: 0x21
456// Start ID: 0x00
457// Default values: 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01,
458// Descriptions:
459// MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
460// MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
461// MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
462// MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
463// MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
464// MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
465// MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
466// MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
467// MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
468// MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
469// MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
470// MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
471*/
472#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C
473
474/*
475// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
476// Number of properties: 12
477// Group ID: 0x21
478// Start ID: 0x0C
479// Default values: 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5,
480// Descriptions:
481// MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
482// MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
483// MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
484// MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
485// MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
486// MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
487// MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
488// MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
489// MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
490// MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
491// MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
492// MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
493*/
494#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5
495
496/*
497// Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
498// Number of properties: 12
499// Group ID: 0x21
500// Start ID: 0x18
501// Default values: 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00,
502// Descriptions:
503// MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
504// MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
505// MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
506// MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
507// MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
508// MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
509// MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
510// MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
511// MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
512// MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
513// MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
514// MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
515*/
516#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00
517
518/*
519// Set properties: RF_PA_MODE_4
520// Number of properties: 4
521// Group ID: 0x22
522// Start ID: 0x00
523// Default values: 0x08, 0x7F, 0x00, 0x5D,
524// Descriptions:
525// PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
526// PA_PWR_LVL - Configuration of PA output power level.
527// PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
528// PA_TC - Configuration of PA ramping parameters.
529*/
530#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x20, 0x2F, 0x00, 0x1D
531
532/*
533// Set properties: RF_SYNTH_PFDCP_CPFF_7
534// Number of properties: 7
535// Group ID: 0x23
536// Start ID: 0x00
537// Default values: 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03,
538// Descriptions:
539// SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
540// SYNTH_PFDCP_CPINT - Integration charge pump current selection.
541// SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
542// SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
543// SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
544// SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
545// SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
546*/
547#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
548
549/*
550// Set properties: RF_MATCH_VALUE_1_12
551// Number of properties: 12
552// Group ID: 0x30
553// Start ID: 0x00
554// Default values: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
555// Descriptions:
556// MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.
557// MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.
558// MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.
559// MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.
560// MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.
561// MATCH_CTRL_2 - Configuration of Match Byte 2.
562// MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.
563// MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.
564// MATCH_CTRL_3 - Configuration of Match Byte 3.
565// MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.
566// MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.
567// MATCH_CTRL_4 - Configuration of Match Byte 4.
568*/
569#define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
570
571/*
572// Set properties: RF_FREQ_CONTROL_INTE_8
573// Number of properties: 8
574// Group ID: 0x40
575// Start ID: 0x00
576// Default values: 0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF,
577// Descriptions:
578// FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
579// FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
580// FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
581// FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
582// FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
583// FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
584// FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
585// FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
586*/
587#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x0E, 0x27, 0x62, 0x27, 0x62, 0x20, 0xFF
588
589
590// AUTOMATICALLY GENERATED CODE!
591// DO NOT EDIT/MODIFY BELOW THIS LINE!
592// --------------------------------------------
593
594#ifndef FIRMWARE_LOAD_COMPILE
595#define RADIO_CONFIGURATION_DATA_ARRAY { \
596 SI446X_PATCH_CMDS, \
597 0x07, RF_POWER_UP, \
598 0x08, RF_GPIO_PIN_CFG, \
599 0x06, RF_GLOBAL_XO_TUNE_2, \
600 0x05, RF_GLOBAL_CONFIG_1, \
601 0x06, RF_INT_CTL_ENABLE_2, \
602 0x08, RF_FRR_CTL_A_MODE_4, \
603 0x0D, RF_PREAMBLE_TX_LENGTH_9, \
604 0x0A, RF_SYNC_CONFIG_6, \
605 0x10, RF_PKT_CRC_CONFIG_12, \
606 0x10, RF_PKT_RX_THRESHOLD_12, \
607 0x10, RF_PKT_FIELD_3_CRC_CONFIG_12, \
608 0x10, RF_PKT_RX_FIELD_1_CRC_CONFIG_12, \
609 0x09, RF_PKT_RX_FIELD_4_CRC_CONFIG_5, \
610 0x08, RF_PKT_CRC_SEED_31_24_4, \
611 0x10, RF_MODEM_MOD_TYPE_12, \
612 0x05, RF_MODEM_FREQ_DEV_0_1, \
613 0x10, RF_MODEM_TX_RAMP_DELAY_12, \
614 0x10, RF_MODEM_BCR_NCO_OFFSET_2_12, \
615 0x07, RF_MODEM_AFC_LIMITER_1_3, \
616 0x05, RF_MODEM_AGC_CONTROL_1, \
617 0x10, RF_MODEM_AGC_WINDOW_SIZE_12, \
618 0x0E, RF_MODEM_RAW_CONTROL_10, \
619 0x06, RF_MODEM_RAW_SEARCH2_2, \
620 0x06, RF_MODEM_SPIKE_DET_2, \
621 0x05, RF_MODEM_RSSI_MUTE_1, \
622 0x09, RF_MODEM_DSA_CTRL1_5, \
623 0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
624 0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
625 0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
626 0x08, RF_PA_MODE_4, \
627 0x0B, RF_SYNTH_PFDCP_CPFF_7, \
628 0x10, RF_MATCH_VALUE_1_12, \
629 0x0C, RF_FREQ_CONTROL_INTE_8, \
630 0x00 \
631 }
632#else
633#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
634#endif
635
636// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
637#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 30000000L
638#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 0x00
639#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 0x10
640#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 0x01
641#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 0x1000
642
643#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED 0x00
644#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE 0x00
645#define RADIO_CONFIGURATION_DATA_RADIO_PATCH { }
646
647#ifndef RADIO_CONFIGURATION_DATA_ARRAY
648#error "This property must be defined!"
649#endif
650
651#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
652#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT
653#endif
654
655#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
656#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT
657#endif
658
659#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
660#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT
661#endif
662
663#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
664#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT
665#endif
666
667#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
668#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT
669#endif
670
671#define RADIO_CONFIGURATION_DATA { \
672 Radio_Configuration_Data_Array, \
673 RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER, \
674 RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH, \
675 RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP, \
676 RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET \
677 }
678
679#endif /* RADIO_CONFIG_H_ */
ism5_patch.h