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lightranger4 2.0.0.0
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| #define LR4_FIRMWARE__INTERNAL_STREAM_COUNT_DIV 0x0F46 |
| #define LR4_FIRMWARE__INTERNAL_STREAM_COUNTER_VAL 0x0F47 |
| #define LR4_GPH_DSS_CONFIG_MANUAL_BLOCK_SELECT 0x0F32 |
| #define LR4_GPH_DSS_CONFIG_MANUAL_EFFECTIVE_SPADS_SELECT 0x0F30 |
| #define LR4_GPH_DSS_CONFIG_MANUAL_EFFECTIVE_SPADS_SELECT_HI 0x0F30 |
| #define LR4_GPH_DSS_CONFIG_MANUAL_EFFECTIVE_SPADS_SELECT_LO 0x0F31 |
| #define LR4_GPH_DSS_CONFIG_MAX_SPADS_LIMIT 0x0F33 |
| #define LR4_GPH_DSS_CONFIG_MIN_SPADS_LIMIT 0x0F34 |
| #define LR4_GPH_DSS_CONFIG_ROI_MODE_CONTROL 0x0F2F |
| #define LR4_GPH_GPH_ID 0x00FB |
| #define LR4_GPH_MM_CONFIG_TIMEOUT_MACROP_A_HI 0x0F36 |
| #define LR4_GPH_MM_CONFIG_TIMEOUT_MACROP_A_LO 0x0F37 |
| #define LR4_GPH_MM_CONFIG_TIMEOUT_MACROP_B_HI 0x0F38 |
| #define LR4_GPH_MM_CONFIG_TIMEOUT_MACROP_B_LO 0x0F39 |
| #define LR4_GPH_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT_MCPS 0x0F42 |
| #define LR4_GPH_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT_MCPS_HI 0x0F42 |
| #define LR4_GPH_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT_MCPS_LO 0x0F43 |
| #define LR4_GPH_RANGE_CONFIG_SIGMA_THRESH 0x0F40 |
| #define LR4_GPH_RANGE_CONFIG_SIGMA_THRESH_HI 0x0F40 |
| #define LR4_GPH_RANGE_CONFIG_SIGMA_THRESH_LO 0x0F41 |
| #define LR4_GPH_RANGE_CONFIG_TIMEOUT_MACROP_A_HI 0x0F3A |
| #define LR4_GPH_RANGE_CONFIG_TIMEOUT_MACROP_A_LO 0x0F3B |
| #define LR4_GPH_RANGE_CONFIG_TIMEOUT_MACROP_B_HI 0x0F3E |
| #define LR4_GPH_RANGE_CONFIG_TIMEOUT_MACROP_B_LO 0x0F3F |
| #define LR4_GPH_RANGE_CONFIG_VALID_PHASE_HIGH 0x0F45 |
| #define LR4_GPH_RANGE_CONFIG_VALID_PHASE_LOW 0x0F44 |
| #define LR4_GPH_RANGE_CONFIG_VCSEL_PERIOD_A 0x0F3C |
| #define LR4_GPH_RANGE_CONFIG_VCSEL_PERIOD_B 0x0F3D |
| #define LR4_GPH_ROI_CONFIG_USER_ROI_CENTRE_SPAD 0x00F8 |
| #define LR4_GPH_ROI_CONFIG_USER_ROI_REQUESTED_GLOBAL_XY_SIZE 0x00F9 |
| #define LR4_GPH_SD_CONFIG_FIRST_ORDER_SELECT 0x00F6 |
| #define LR4_GPH_SD_CONFIG_INITIAL_PHASE_SD0 0x00F4 |
| #define LR4_GPH_SD_CONFIG_INITIAL_PHASE_SD1 0x00F5 |
| #define LR4_GPH_SD_CONFIG_QUANTIFIER 0x00F7 |
| #define LR4_GPH_SD_CONFIG_WOI_SD0 0x00F2 |
| #define LR4_GPH_SD_CONFIG_WOI_SD1 0x00F3 |
| #define LR4_GPH_SPARE_0 0x00F1 |
| #define LR4_GPH_SYSTEM_ENABLE_XTALK_PER_QUADRANT 0x00F0 |
| #define LR4_GPH_SYSTEM_INTERRUPT_CONFIG_GPIO 0x0F28 |
| #define LR4_GPH_SYSTEM_SEQUENCE_CONFIG 0x00FA |
| #define LR4_GPH_SYSTEM_THRESH_HIGH 0x00EC |
| #define LR4_GPH_SYSTEM_THRESH_HIGH_HI 0x00EC |
| #define LR4_GPH_SYSTEM_THRESH_HIGH_LO 0x00ED |
| #define LR4_GPH_SYSTEM_THRESH_LOW 0x00EE |
| #define LR4_GPH_SYSTEM_THRESH_LOW_HI 0x00EE |
| #define LR4_GPH_SYSTEM_THRESH_LOW_LO 0x00EF |
| #define LR4_GPH_SYSTEM_THRESH_RATE_HIGH 0x0F24 |
| #define LR4_GPH_SYSTEM_THRESH_RATE_HIGH_HI 0x0F24 |
| #define LR4_GPH_SYSTEM_THRESH_RATE_HIGH_LO 0x0F25 |
| #define LR4_GPH_SYSTEM_THRESH_RATE_LOW 0x0F26 |
| #define LR4_GPH_SYSTEM_THRESH_RATE_LOW_HI 0x0F26 |
| #define LR4_GPH_SYSTEM_THRESH_RATE_LOW_LO 0x0F27 |
| #define LR4_INTERRUPT_MANAGER_CLEAR 0x00FE |
| #define LR4_INTERRUPT_MANAGER_ENABLES 0x00FD |
| #define LR4_INTERRUPT_MANAGER_STATUS 0x00FF |
| #define LR4_INTERRUPT_SCHEDULER_DATA_OUT 0x0108 |
| #define LR4_INTERRUPT_SCHEDULER_DATA_OUT_0 0x010B |
| #define LR4_INTERRUPT_SCHEDULER_DATA_OUT_1 0x010A |
| #define LR4_INTERRUPT_SCHEDULER_DATA_OUT_2 0x0109 |
| #define LR4_INTERRUPT_SCHEDULER_DATA_OUT_3 0x0108 |
| #define LR4_MCU_TO_HOST_BANK_WR_ACCESS_EN 0x0100 |
| #define LR4_NVM_BIST_COMPLETE 0x010C |
| #define LR4_NVM_BIST_STATUS 0x010D |
| #define LR4_PAD_STARTUP_MODE_VALUE_CTRL 0x0103 |
| #define LR4_PAD_STARTUP_MODE_VALUE_RO 0x0102 |
| #define LR4_PLL_PERIOD_US 0x0104 |
| #define LR4_PLL_PERIOD_US_0 0x0107 |
| #define LR4_PLL_PERIOD_US_1 0x0106 |
| #define LR4_PLL_PERIOD_US_2 0x0105 |
| #define LR4_PLL_PERIOD_US_3 0x0104 |
| #define LR4_POWER_MANAGEMENT_GO1_RESET_STATUS 0x0101 |
| #define LR4_SYSTEM_INTERRUPT_SET 0x00FC |