Settings for registers of Load Cell 3 Click driver. More...

Macros
#define	LOADCELL3_SET_IF_SEL_ACCESSES_CONTROLLER 0x00
	Load Cell 3 description setting.

#define	LOADCELL3_SET_IF_SEL_ACCESSES_DIGITAL_INTERFACE 0x01

#define	LOADCELL3_SET_TSEM_MODE_SINGLE_ENDED 0x00

#define	LOADCELL3_SET_TSEM_MODE_DIFFERENTIAL 0x01

#define	LOADCELL3_SET_T_MUX_CTRL_EXT_TEMPE 0x00

#define	LOADCELL3_SET_T_MUX_CTRL_TEST 0x01

#define	LOADCELL3_SET_T_MUX_CTRL_INT_TEMPE 0x02

#define	LOADCELL3_SET_T_MUX_CTRL_BRIDGE_CURRENT 0x03

#define	LOADCELL3_SET_T_MUX_CTRL_ITEMP 0x04

#define	LOADCELL3_SET_GAIN_1_33 0x00

#define	LOADCELL3_SET_GAIN_2 0x01

#define	LOADCELL3_SET_GAIN_4 0x02

#define	LOADCELL3_SET_GAIN_10 0x03

#define	LOADCELL3_SET_GAIN_20 0x04

#define	LOADCELL3_SET_GAIN_40 0x05

#define	LOADCELL3_SET_GAIN_100 0x06

#define	LOADCELL3_SET_GAIN_200 0x07

#define	LOADCELL3_SET_ITEMP_CTRL_50_mA 0x00

#define	LOADCELL3_SET_ITEMP_CTRL_100_mA 0x01

#define	LOADCELL3_SET_ITEMP_CTRL_200_mA 0x02

#define	LOADCELL3_SET_ITEMP_CTRL_1000_mA 0x03

#define	LOADCELL3_SET_ITEMP_CTRL_OFF 0x04

#define	LOADCELL3_SET_OFFSET_CANCEL_0_mV 0x00

#define	LOADCELL3_SET_OFFSET_CANCEL_3_65_mV 0x01

#define	LOADCELL3_SET_OFFSET_CANCEL_7_3_mV 0x02

#define	LOADCELL3_SET_OFFSET_CANCEL_10_95_mV 0x03

#define	LOADCELL3_SET_OFFSET_CANCEL_14_6_mV 0x04

#define	LOADCELL3_SET_OFFSET_CANCEL_18_28_mV 0x05

#define	LOADCELL3_SET_OFFSET_CANCEL_21_9_mV 0x06

#define	LOADCELL3_SET_OFFSET_CANCEL_25_55_mV 0x07

#define	LOADCELL3_SET_OFFSET_CANCEL_29_2_mV 0x08

#define	LOADCELL3_SET_OFFSET_CANCEL_32_85_mV 0x09

#define	LOADCELL3_SET_OFFSET_CANCEL_36_5_mV 0x0A

#define	LOADCELL3_SET_OFFSET_CANCEL_40_15_mV 0x0B

#define	LOADCELL3_SET_OFFSET_CANCEL_43_8_mV 0x0C

#define	LOADCELL3_SET_OFFSET_CANCEL_47_45_mV 0x0D

#define	LOADCELL3_SET_OFFSET_CANCEL_51_1_mV 0x0E

#define	LOADCELL3_SET_OFFSET_CANCEL_54_75_mV 0x0F

#define	LOADCELL3_SET_OFFSET_CURRENT_VINPN 0x00

#define	LOADCELL3_SET_OFFSET_CURRENT_VINPP 0x01

#define	LOADCELL3_SET_DEV_ADDR 0x42
	Load Cell 3 device address setting.

#define	LOADCELL3_SET_MEMORY_PAGE_TEST_REG 0x40

#define	LOADCELL3_SET_MEMORY_PAGE_CONTROL_AND_STATUS_REG 0x42

#define	LOADCELL3_SET_MEMORY_PAGE_EEPROM_CACHE_CELLS 0x45

#define	LOADCELL3_SET_MEMORY_PAGE_CTRL_AND_STATUS_REG 0x47

Detailed Description

Settings for registers of Load Cell 3 Click driver.

Macro Definition Documentation

◆ LOADCELL3_SET_DEV_ADDR

#define LOADCELL3_SET_DEV_ADDR 0x42

Load Cell 3 device address setting.

Specified setting for device slave address selection of Load Cell 3 Click driver.

◆ LOADCELL3_SET_GAIN_10

#define LOADCELL3_SET_GAIN_10 0x03

◆ LOADCELL3_SET_GAIN_100

#define LOADCELL3_SET_GAIN_100 0x06

◆ LOADCELL3_SET_GAIN_1_33

#define LOADCELL3_SET_GAIN_1_33 0x00

◆ LOADCELL3_SET_GAIN_2

#define LOADCELL3_SET_GAIN_2 0x01

◆ LOADCELL3_SET_GAIN_20

#define LOADCELL3_SET_GAIN_20 0x04

◆ LOADCELL3_SET_GAIN_200

#define LOADCELL3_SET_GAIN_200 0x07

◆ LOADCELL3_SET_GAIN_4

#define LOADCELL3_SET_GAIN_4 0x02

◆ LOADCELL3_SET_GAIN_40

#define LOADCELL3_SET_GAIN_40 0x05

◆ LOADCELL3_SET_IF_SEL_ACCESSES_CONTROLLER

#define LOADCELL3_SET_IF_SEL_ACCESSES_CONTROLLER 0x00

Load Cell 3 description setting.

Specified setting for description of Load Cell 3 Click driver.

◆ LOADCELL3_SET_IF_SEL_ACCESSES_DIGITAL_INTERFACE

#define LOADCELL3_SET_IF_SEL_ACCESSES_DIGITAL_INTERFACE 0x01

◆ LOADCELL3_SET_ITEMP_CTRL_1000_mA

#define LOADCELL3_SET_ITEMP_CTRL_1000_mA 0x03

◆ LOADCELL3_SET_ITEMP_CTRL_100_mA

#define LOADCELL3_SET_ITEMP_CTRL_100_mA 0x01

◆ LOADCELL3_SET_ITEMP_CTRL_200_mA

#define LOADCELL3_SET_ITEMP_CTRL_200_mA 0x02

◆ LOADCELL3_SET_ITEMP_CTRL_50_mA

#define LOADCELL3_SET_ITEMP_CTRL_50_mA 0x00

◆ LOADCELL3_SET_ITEMP_CTRL_OFF

#define LOADCELL3_SET_ITEMP_CTRL_OFF 0x04

◆ LOADCELL3_SET_MEMORY_PAGE_CONTROL_AND_STATUS_REG

#define LOADCELL3_SET_MEMORY_PAGE_CONTROL_AND_STATUS_REG 0x42

◆ LOADCELL3_SET_MEMORY_PAGE_CTRL_AND_STATUS_REG

#define LOADCELL3_SET_MEMORY_PAGE_CTRL_AND_STATUS_REG 0x47

◆ LOADCELL3_SET_MEMORY_PAGE_EEPROM_CACHE_CELLS

#define LOADCELL3_SET_MEMORY_PAGE_EEPROM_CACHE_CELLS 0x45

◆ LOADCELL3_SET_MEMORY_PAGE_TEST_REG

#define LOADCELL3_SET_MEMORY_PAGE_TEST_REG 0x40

◆ LOADCELL3_SET_OFFSET_CANCEL_0_mV

#define LOADCELL3_SET_OFFSET_CANCEL_0_mV 0x00

◆ LOADCELL3_SET_OFFSET_CANCEL_10_95_mV

#define LOADCELL3_SET_OFFSET_CANCEL_10_95_mV 0x03

◆ LOADCELL3_SET_OFFSET_CANCEL_14_6_mV

#define LOADCELL3_SET_OFFSET_CANCEL_14_6_mV 0x04

◆ LOADCELL3_SET_OFFSET_CANCEL_18_28_mV

#define LOADCELL3_SET_OFFSET_CANCEL_18_28_mV 0x05

◆ LOADCELL3_SET_OFFSET_CANCEL_21_9_mV

#define LOADCELL3_SET_OFFSET_CANCEL_21_9_mV 0x06

◆ LOADCELL3_SET_OFFSET_CANCEL_25_55_mV

#define LOADCELL3_SET_OFFSET_CANCEL_25_55_mV 0x07

◆ LOADCELL3_SET_OFFSET_CANCEL_29_2_mV

#define LOADCELL3_SET_OFFSET_CANCEL_29_2_mV 0x08

◆ LOADCELL3_SET_OFFSET_CANCEL_32_85_mV

#define LOADCELL3_SET_OFFSET_CANCEL_32_85_mV 0x09

◆ LOADCELL3_SET_OFFSET_CANCEL_36_5_mV

#define LOADCELL3_SET_OFFSET_CANCEL_36_5_mV 0x0A

◆ LOADCELL3_SET_OFFSET_CANCEL_3_65_mV

#define LOADCELL3_SET_OFFSET_CANCEL_3_65_mV 0x01

◆ LOADCELL3_SET_OFFSET_CANCEL_40_15_mV

#define LOADCELL3_SET_OFFSET_CANCEL_40_15_mV 0x0B

◆ LOADCELL3_SET_OFFSET_CANCEL_43_8_mV

#define LOADCELL3_SET_OFFSET_CANCEL_43_8_mV 0x0C

◆ LOADCELL3_SET_OFFSET_CANCEL_47_45_mV

#define LOADCELL3_SET_OFFSET_CANCEL_47_45_mV 0x0D

◆ LOADCELL3_SET_OFFSET_CANCEL_51_1_mV

#define LOADCELL3_SET_OFFSET_CANCEL_51_1_mV 0x0E

◆ LOADCELL3_SET_OFFSET_CANCEL_54_75_mV

#define LOADCELL3_SET_OFFSET_CANCEL_54_75_mV 0x0F

◆ LOADCELL3_SET_OFFSET_CANCEL_7_3_mV

#define LOADCELL3_SET_OFFSET_CANCEL_7_3_mV 0x02

◆ LOADCELL3_SET_OFFSET_CURRENT_VINPN

#define LOADCELL3_SET_OFFSET_CURRENT_VINPN 0x00

◆ LOADCELL3_SET_OFFSET_CURRENT_VINPP

#define LOADCELL3_SET_OFFSET_CURRENT_VINPP 0x01

◆ LOADCELL3_SET_T_MUX_CTRL_BRIDGE_CURRENT

#define LOADCELL3_SET_T_MUX_CTRL_BRIDGE_CURRENT 0x03

◆ LOADCELL3_SET_T_MUX_CTRL_EXT_TEMPE

#define LOADCELL3_SET_T_MUX_CTRL_EXT_TEMPE 0x00

◆ LOADCELL3_SET_T_MUX_CTRL_INT_TEMPE

#define LOADCELL3_SET_T_MUX_CTRL_INT_TEMPE 0x02

◆ LOADCELL3_SET_T_MUX_CTRL_ITEMP

#define LOADCELL3_SET_T_MUX_CTRL_ITEMP 0x04

◆ LOADCELL3_SET_T_MUX_CTRL_TEST

#define LOADCELL3_SET_T_MUX_CTRL_TEST 0x01

◆ LOADCELL3_SET_TSEM_MODE_DIFFERENTIAL

#define LOADCELL3_SET_TSEM_MODE_DIFFERENTIAL 0x01

◆ LOADCELL3_SET_TSEM_MODE_SINGLE_ENDED

#define LOADCELL3_SET_TSEM_MODE_SINGLE_ENDED 0x00

Macros