|
#define | LOADCELL6_CMD_RATE0 0x01 |
| Load Cell 6 description setting.
|
|
#define | LOADCELL6_CMD_RATE1 0x02 |
|
#define | LOADCELL6_CMD_RATE2 0x04 |
|
#define | LOADCELL6_CMD_RATE3 0x08 |
|
#define | LOADCELL6_CMD_IMPD 0x10 |
|
#define | LOADCELL6_CMD_CAL 0x20 |
|
#define | LOADCELL6_CMD_START 0x80 |
|
#define | LOADCELL6_CMD_REG_ACCESS_MODE 0x40 |
|
#define | LOADCELL6_STAT_RDY 0x0001 |
| Load Cell 6 STAT register bits description.
|
|
#define | LOADCELL6_STAT_MSTAT 0x0002 |
|
#define | LOADCELL6_STAT_DOR 0x0004 |
|
#define | LOADCELL6_STAT_SYSGOR 0x0008 |
|
#define | LOADCELL6_STAT_RATE0 0x0010 |
|
#define | LOADCELL6_STAT_RATE1 0x0020 |
|
#define | LOADCELL6_STAT_RATE2 0x0040 |
|
#define | LOADCELL6_STAT_RATE3 0x0080 |
|
#define | LOADCELL6_STAT_AOR 0x0100 |
|
#define | LOADCELL6_STAT_RDERR 0x0200 |
|
#define | LOADCELL6_STAT_PDSTAT0 0x0400 |
|
#define | LOADCELL6_STAT_PDSTAT1 0x0800 |
|
#define | LOADCELL6_STAT_ERROR 0x4000 |
|
#define | LOADCELL6_STAT_INRESET 0x8000 |
|
#define | LOADCELL6_CTRL1_CONTSC 0x01 |
| Load Cell 6 CTRL1 register bits description.
|
|
#define | LOADCELL6_CTRL1_SCYCLE 0x02 |
|
#define | LOADCELL6_CTRL1_FORMAT 0x04 |
|
#define | LOADCELL6_CTRL1_U_B 0x08 |
|
#define | LOADCELL6_CTRL1_PD0 0x10 |
|
#define | LOADCELL6_CTRL1_PD1 0x20 |
|
#define | LOADCELL6_CTRL1_SYNC 0x40 |
|
#define | LOADCELL6_CTRL1_EXTCK 0x80 |
|
#define | LOADCELL6_CTRL2_PGAIN_x1 0x00 |
| Load Cell 6 CTRL2 register bits description.
|
|
#define | LOADCELL6_CTRL2_PGAIN_x2 0x01 |
|
#define | LOADCELL6_CTRL2_PGAIN_x4 0x02 |
|
#define | LOADCELL6_CTRL2_PGAIN_x8 0x03 |
|
#define | LOADCELL6_CTRL2_PGAIN_x16 0x04 |
|
#define | LOADCELL6_CTRL2_PGAIN_x32 0x05 |
|
#define | LOADCELL6_CTRL2_PGAIN_x64 0x06 |
|
#define | LOADCELL6_CTRL2_PGAIN_x128 0x07 |
|
#define | LOADCELL6_CTRL2_PGAGEN 0x08 |
|
#define | LOADCELL6_CTRL2_LPMODE 0x10 |
|
#define | LOADCELL6_CTRL2_BUFEN 0x20 |
|
#define | LOADCELL6_CTRL2_DGAIN_x1 0x00 |
|
#define | LOADCELL6_CTRL2_DGAIN_x2 0x40 |
|
#define | LOADCELL6_CTRL2_DGAIN_x4 0x80 |
|
#define | LOADCELL6_CTRL2_DGAIN_x8 0xC0 |
|
#define | LOADCELL6_CTRL2_DGAIN0 0x40 |
|
#define | LOADCELL6_CTRL2_DGAIN1 0x80 |
|
#define | LOADCELL6_CTRL3_DATA32 0x08 |
| Load Cell 6 CTRL3 register bits description.
|
|
#define | LOADCELL6_CTRL3_MODBITS 0x10 |
|
#define | LOADCELL6_CTRL3_ENMSYNC 0x20 |
|
#define | LOADCELL6_CTRL3_RESERVED 0x41 |
|
#define | LOADCELL6_CTRL4_DIO1 0x01 |
| Load Cell 6 CTRL4 register bits description.
|
|
#define | LOADCELL6_CTRL4_DIO2 0x02 |
|
#define | LOADCELL6_CTRL4_DIO3 0x04 |
|
#define | LOADCELL6_CTRL4_DIO4 0x08 |
|
#define | LOADCELL6_CTRL4_DIR1 0x10 |
|
#define | LOADCELL6_CTRL4_DIR2 0x20 |
|
#define | LOADCELL6_CTRL4_DIR3 0x40 |
|
#define | LOADCELL6_CTRL4_DIR4 0x80 |
|
#define | LOADCELL6_CTRL5_NOSCO 0x01 |
| Load Cell 6 CTRL5 register bits description.
|
|
#define | LOADCELL6_CTRL5_NOSCG 0x02 |
|
#define | LOADCELL6_CTRL5_NOSYSO 0x04 |
|
#define | LOADCELL6_CTRL5_NOSYSG 0x08 |
|
#define | LOADCELL6_CTRL5_CAL0 0x40 |
|
#define | LOADCELL6_CTRL5_CAL1 0x80 |
|
#define | LOADCELL6_DATA_NO_DATA 0 |
| Load Cell 6 weight data description.
|
|
#define | LOADCELL6_DATA_OK 1 |
|
#define | LOADCELL6_WEIGHT_ZERO 0 |
|
#define | LOADCELL6_WEIGHT_100G 100 |
|
#define | LOADCELL6_WEIGHT_200G 200 |
|
#define | LOADCELL6_WEIGHT_500G 500 |
|
#define | LOADCELL6_WEIGHT_1000G 1000 |
|
#define | LOADCELL6_WEIGHT_5000G 5000 |
|
#define | LOADCELL6_WEIGHT_10000G 10000 |
|
#define | LOADCELL6_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE |
| Data sample selection.
|
|
#define | LOADCELL6_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE |
|