MCP251863 description register. More...

Macros
#define	MCP251863_FIFO_CH0 0
	MCP251863 description setting.

#define	MCP251863_FIFO_CH1 1

#define	MCP251863_FIFO_CH2 2

#define	MCP251863_FIFO_CH3 3

#define	MCP251863_FIFO_CH4 4

#define	MCP251863_FIFO_CH5 5

#define	MCP251863_FIFO_CH6 6

#define	MCP251863_FIFO_CH7 7

#define	MCP251863_FIFO_CH8 8

#define	MCP251863_FIFO_CH9 9

#define	MCP251863_FIFO_CH10 10

#define	MCP251863_FIFO_CH11 11

#define	MCP251863_FIFO_CH12 12

#define	MCP251863_FIFO_CH13 13

#define	MCP251863_FIFO_CH14 14

#define	MCP251863_FIFO_CH15 15

#define	MCP251863_FIFO_CH16 16

#define	MCP251863_FIFO_CH17 17

#define	MCP251863_FIFO_CH18 18

#define	MCP251863_FIFO_CH19 19

#define	MCP251863_FIFO_CH20 20

#define	MCP251863_FIFO_CH21 21

#define	MCP251863_FIFO_CH22 22

#define	MCP251863_FIFO_CH23 23

#define	MCP251863_FIFO_CH24 24

#define	MCP251863_FIFO_CH25 25

#define	MCP251863_FIFO_CH26 26

#define	MCP251863_FIFO_CH27 27

#define	MCP251863_FIFO_CH28 28

#define	MCP251863_FIFO_CH29 29

#define	MCP251863_FIFO_CH30 30

#define	MCP251863_FIFO_CH31 31

#define	MCP251863_FIFO_TOTAL_CHANNELS 32

#define	MCP251863_FIFO_FIRST_CHANNEL MCP251863_FIFO_CH1

#define	CAN_TXQUEUE_CH0 MCP251863_FIFO_CH0

#define	MCP251863_FILT0 0
	MCP251863 CAN Filter Channels.

#define	MCP251863_FILT1 1

#define	MCP251863_FILT2 2

#define	MCP251863_FILT3 3

#define	MCP251863_FILT4 4

#define	MCP251863_FILT5 5

#define	MCP251863_FILT6 6

#define	MCP251863_FILT7 7

#define	MCP251863_FILT8 8

#define	MCP251863_FILT9 9

#define	MCP251863_FILT10 10

#define	MCP251863_FILT11 11

#define	MCP251863_FILT12 12

#define	MCP251863_FILT13 13

#define	MCP251863_FILT14 14

#define	MCP251863_FILT15 15

#define	MCP251863_FILT16 16

#define	MCP251863_FILT17 17

#define	MCP251863_FILT18 18

#define	MCP251863_FILT19 19

#define	MCP251863_FILT20 20

#define	MCP251863_FILT21 21

#define	MCP251863_FILT22 22

#define	MCP251863_FILT23 23

#define	MCP251863_FILT24 24

#define	MCP251863_FILT25 25

#define	MCP251863_FILT26 26

#define	MCP251863_FILT27 27

#define	MCP251863_FILT28 28

#define	MCP251863_FILT29 29

#define	MCP251863_FILT30 30

#define	MCP251863_FILT31 31

#define	MCP251863_FILT_TOTAL 32

#define	MCP251863_NORMAL_MODE 0x00
	MCP251863 CAN Operation Modes.

#define	MCP251863_SLEEP_MODE 0x01

#define	MCP251863_INT_LOOP_MODE 0x02

#define	MCP251863_LISTEN_ONLY_MODE 0x03

#define	MCP251863_CONFIG_MODE 0x04

#define	MCP251863_EXT_LOOP_MODE 0x05

#define	MCP251863_CLASSIC_MODE 0x06

#define	MCP251863_RESTRICT_MODE 0x07

#define	MCP251863_INVALID_MODE 0xFF

#define	MCP251863_TXBWS_NO_DELAY 0
	MCP251863 Transmit Bandwidth Sharing.

#define	MCP251863_TXBWS_2 1

#define	MCP251863_TXBWS_4 2

#define	MCP251863_TXBWS_8 3

#define	MCP251863_TXBWS_16 4

#define	MCP251863_TXBWS_32 5

#define	MCP251863_TXBWS_64 6

#define	MCP251863_TXBWS_128 7

#define	MCP251863_TXBWS_256 8

#define	MCP251863_TXBWS_512 9

#define	MCP251863_TXBWS_1024 10

#define	MCP251863_TXBWS_2048 11

#define	MCP251863_TXBWS_4096 12

#define	MCP251863_WFT00 0
	MCP251863 Wake-up Filter Time.

#define	MCP251863_WFT01 1

#define	MCP251863_WFT10 2

#define	MCP251863_WFT11 3

#define	MCP251863_DNET_FILT_DISABLE 0
	MCP251863 Data Byte Filter Number.

#define	MCP251863_DNET_FILT_SIZE_1_BIT 1

#define	MCP251863_DNET_FILT_SIZE_2_BIT 2

#define	MCP251863_DNET_FILT_SIZE_3_BIT 3

#define	MCP251863_DNET_FILT_SIZE_4_BIT 4

#define	MCP251863_DNET_FILT_SIZE_5_BIT 5

#define	MCP251863_DNET_FILT_SIZE_6_BIT 6

#define	MCP251863_DNET_FILT_SIZE_7_BIT 7

#define	MCP251863_DNET_FILT_SIZE_8_BIT 8

#define	MCP251863_DNET_FILT_SIZE_9_BIT 9

#define	MCP251863_DNET_FILT_SIZE_10_BIT 10

#define	MCP251863_DNET_FILT_SIZE_11_BIT 11

#define	MCP251863_DNET_FILT_SIZE_12_BIT 12

#define	MCP251863_DNET_FILT_SIZE_13_BIT 13

#define	MCP251863_DNET_FILT_SIZE_14_BIT 14

#define	MCP251863_DNET_FILT_SIZE_15_BIT 15

#define	MCP251863_DNET_FILT_SIZE_16_BIT 16

#define	MCP251863_DNET_FILT_SIZE_17_BIT 17

#define	MCP251863_DNET_FILT_SIZE_18_BIT 18

#define	MCP251863_PLSIZE_8 0
	MCP251863 FIFO Payload Size.

#define	MCP251863_PLSIZE_12 1

#define	MCP251863_PLSIZE_16 2

#define	MCP251863_PLSIZE_20 3

#define	MCP251863_PLSIZE_24 4

#define	MCP251863_PLSIZE_32 5

#define	MCP251863_PLSIZE_48 6

#define	MCP251863_PLSIZE_64 7

#define	MCP251863_DLC_0 0
	MCP251863 CAN Data Length Code.

#define	MCP251863_DLC_1 1

#define	MCP251863_DLC_2 2

#define	MCP251863_DLC_3 3

#define	MCP251863_DLC_4 4

#define	MCP251863_DLC_5 5

#define	MCP251863_DLC_6 6

#define	MCP251863_DLC_7 7

#define	MCP251863_DLC_8 8

#define	MCP251863_DLC_12 9

#define	MCP251863_DLC_16 10

#define	MCP251863_DLC_20 11

#define	MCP251863_DLC_24 12

#define	MCP251863_DLC_32 13

#define	MCP251863_DLC_48 14

#define	MCP251863_DLC_64 15

#define	MCP251863_RX_FIFO_EMPTY 0
	MCP251863 CAN RX FIFO Status.

#define	MCP251863_RX_FIFO_STATUS_MASK 0x0F

#define	MCP251863_RX_FIFO_NOT_EMPTY 0x01

#define	MCP251863_RX_FIFO_HALF_FULL 0x02

#define	MCP251863_RX_FIFO_FULL 0x04

#define	MCP251863_RX_FIFO_OVERFLOW 0x08

#define	MCP251863_TX_FIFO_FULL 0
	MCP251863 CAN TX FIFO Status.

#define	MCP251863_TX_FIFO_STATUS_MASK 0x1F7

#define	MCP251863_TX_FIFO_NOT_FULL 0x01

#define	MCP251863_TX_FIFO_HALF_FULL 0x02

#define	MCP251863_TX_FIFO_EMPTY 0x04

#define	MCP251863_TX_FIFO_ATTEMPTS_EXHAUSTED 0x10

#define	MCP251863_TX_FIFO_ERROR 0x20

#define	MCP251863_TX_FIFO_ARBITRATION_LOST 0x40

#define	MCP251863_TX_FIFO_ABORTED 0x80

#define	MCP251863_TX_FIFO_TRANSMITTING 0x100

#define	MCP251863_TEF_FIFO_EMPTY 0
	MCP251863 CAN TEF FIFO Status.

#define	MCP251863_TEF_FIFO_STATUS_MASK 0x0F

#define	MCP251863_TEF_FIFO_NOT_EMPTY 0x01

#define	MCP251863_TEF_FIFO_HALF_FULL 0x02

#define	MCP251863_TEF_FIFO_FULL 0x04

#define	MCP251863_TEF_FIFO_OVERFLOW 0x08

#define	MCP251863_TX_FIFO_NO_EVENT 0
	MCP251863 CAN Module Events.

#define	MCP251863_TX_FIFO_ALL_EVENTS 0x17

#define	MCP251863_TX_FIFO_NOT_FULL_EVENT 0x01

#define	MCP251863_TX_FIFO_HALF_FULL_EVENT 0x02

#define	MCP251863_TX_FIFO_EMPTY_EVENT 0x04

#define	MCP251863_TX_FIFO_ATTEMPTS_EXHAUSTED_EVENT 0x10

#define	MCP251863_RX_FIFO_NO_EVENT 0

#define	MCP251863_RX_FIFO_ALL_EVENTS 0x0F

#define	MCP251863_RX_FIFO_NOT_EMPTY_EVENT 0x01

#define	MCP251863_RX_FIFO_HALF_FULL_EVENT 0x02

#define	MCP251863_RX_FIFO_FULL_EVENT 0x04

#define	MCP251863_RX_FIFO_OVERFLOW_EVENT 0x08

#define	MCP251863_TEF_FIFO_NO_EVENT 0

#define	MCP251863_TEF_FIFO_ALL_EVENTS 0x0F

#define	MCP251863_TEF_FIFO_NOT_EMPTY_EVENT 0x01

#define	MCP251863_TEF_FIFO_HALF_FULL_EVENT 0x02

#define	MCP251863_TEF_FIFO_FULL_EVENT 0x04

#define	MCP251863_TEF_FIFO_OVERFLOW_EVENT 0x08

#define	MCP251863_NO_EVENT 0

#define	MCP251863_ALL_EVENTS 0xFF1F

#define	MCP251863_TX_EVENT 0x0001

#define	MCP251863_RX_EVENT 0x0002

#define	MCP251863_TIME_BASE_COUNTER_EVENT 0x0004

#define	MCP251863_OPERATION_MODE_CHANGE_EVENT 0x0008

#define	MCP251863_TEF_EVENT 0x0010

#define	MCP251863_RAM_ECC_EVENT 0x0100

#define	MCP251863_SPI_CRC_EVENT 0x0200

#define	MCP251863_TX_ATTEMPTS_EVENT 0x0400

#define	MCP251863_RX_OVERFLOW_EVENT 0x0800

#define	MCP251863_SYSTEM_ERROR_EVENT 0x1000

#define	MCP251863_BUS_ERROR_EVENT 0x2000

#define	MCP251863_BUS_WAKEUP_EVENT 0x4000

#define	MCP251863_RX_INVALID_MESSAGE_EVENT 0x8000

#define	MCP251863_500K_1M 0

#define	MCP251863_500K_2M 1

#define	MCP251863_500K_3M 2

#define	MCP251863_500K_4M 3

#define	MCP251863_500K_5M 4

#define	MCP251863_500K_6M7 5

#define	MCP251863_500K_8M 6

#define	MCP251863_500K_10M 7

#define	MCP251863_250K_500K 8

#define	MCP251863_250K_833K 9

#define	MCP251863_250K_1M 10

#define	MCP251863_250K_1M5 11

#define	MCP251863_250K_2M 12

#define	MCP251863_250K_3M 13

#define	MCP251863_250K_4M 14

#define	MCP251863_1000K_4M 15

#define	MCP251863_1000K_8M 16

#define	MCP251863_125K_500K 17

#define	MCP251863_NBT_125K 0

#define	MCP251863_NBT_250K 1

#define	MCP251863_NBT_500K 2

#define	MCP251863_NBT_1M 3

#define	MCP251863_DBT_500K 0

#define	MCP251863_DBT_833K 1

#define	MCP251863_DBT_1M 2

#define	MCP251863_DBT_1M5 3

#define	MCP251863_DBT_2M 4

#define	MCP251863_DBT_3M 5

#define	MCP251863_DBT_4M 6

#define	MCP251863_DBT_5M 7

#define	MCP251863_DBT_6M7 8

#define	MCP251863_DBT_8M 9

#define	MCP251863_DBT_10M 10

#define	MCP251863_SSP_MODE_OFF 0

#define	MCP251863_SSP_MODE_MANUAL 1

#define	MCP251863_SSP_MODE_AUTO 2

#define	MCP251863_ERROR_FREE_STATE 0

#define	MCP251863_ERROR_ALL 0x3F

#define	MCP251863_TX_RX_WARNING_STATE 0x01

#define	MCP251863_RX_WARNING_STATE 0x02

#define	MCP251863_TX_WARNING_STATE 0x04

#define	MCP251863_RX_BUS_PASSIVE_STATE 0x08

#define	MCP251863_TX_BUS_PASSIVE_STATE 0x10

#define	MCP251863_TX_BUS_OFF_STATE 0x20

#define	MCP251863_TS_SOF 0x00

#define	MCP251863_TS_EOF 0x01

#define	MCP251863_TS_RES 0x02

#define	MCP2518_ECC_NO_EVENT 0x00

#define	MCP2518_ECC_ALL_EVENTS 0x06

#define	MCP2518_ECC_SEC_EVENT 0x02

#define	MCP2518_ECC_DED_EVENT 0x04

#define	MCP251863_CRC_NO_EVENT 0x00

#define	MCP251863_CRC_ALL_EVENTS 0x03

#define	MCP251863_CRC_CRCERR_EVENT 0x01

#define	MCP251863_CRC_FORMERR_EVENT 0x02

#define	MCP251863_PIN_0 0
	MCP251863 Pin mode.

#define	MCP251863_PIN_1 1

#define	MCP251863_PINMODE_INT 0

#define	MCP251863_PINMODE_GPIO 1

#define	MCP251863_PINOUT 0

#define	MCP251863_PININ 1

#define	MCP251863_PINLOW 0

#define	MCP251863_PINHIGH 1

#define	MCP251863_PUSHPULL 0

#define	MCP251863_OPENDRAIN 1

#define	MCP251863_CLKO_CLOCK 0

#define	MCP251863_CLKO_SOF 1

#define	MCP251863_TXREQ_CH0 0x00000001
	MCP251863 TX req channel.

#define	MCP251863_TXREQ_CH1 0x00000002

#define	MCP251863_TXREQ_CH2 0x00000004

#define	MCP251863_TXREQ_CH3 0x00000008

#define	MCP251863_TXREQ_CH4 0x00000010

#define	MCP251863_TXREQ_CH5 0x00000020

#define	MCP251863_TXREQ_CH6 0x00000040

#define	MCP251863_TXREQ_CH7 0x00000080

#define	MCP251863_TXREQ_CH8 0x00000100

#define	MCP251863_TXREQ_CH9 0x00000200

#define	MCP251863_TXREQ_CH10 0x00000400

#define	MCP251863_TXREQ_CH11 0x00000800

#define	MCP251863_TXREQ_CH12 0x00001000

#define	MCP251863_TXREQ_CH13 0x00002000

#define	MCP251863_TXREQ_CH14 0x00004000

#define	MCP251863_TXREQ_CH15 0x00008000

#define	MCP251863_TXREQ_CH16 0x00010000

#define	MCP251863_TXREQ_CH17 0x00020000

#define	MCP251863_TXREQ_CH18 0x00040000

#define	MCP251863_TXREQ_CH19 0x00080000

#define	MCP251863_TXREQ_CH20 0x00100000

#define	MCP251863_TXREQ_CH21 0x00200000

#define	MCP251863_TXREQ_CH22 0x00400000

#define	MCP251863_TXREQ_CH23 0x00800000

#define	MCP251863_TXREQ_CH24 0x01000000

#define	MCP251863_TXREQ_CH25 0x02000000

#define	MCP251863_TXREQ_CH26 0x04000000

#define	MCP251863_TXREQ_CH27 0x08000000

#define	MCP251863_TXREQ_CH28 0x10000000

#define	MCP251863_TXREQ_CH29 0x20000000

#define	MCP251863_TXREQ_CH30 0x40000000

#define	MCP251863_TXREQ_CH31 0x80000000

#define	MCP251863_ICODE_FIFO_CH0 0
	MCP251863 FIFO channel.

#define	MCP251863_ICODE_FIFO_CH1 1

#define	MCP251863_ICODE_FIFO_CH2 2

#define	MCP251863_ICODE_FIFO_CH3 3

#define	MCP251863_ICODE_FIFO_CH4 4

#define	MCP251863_ICODE_FIFO_CH5 5

#define	MCP251863_ICODE_FIFO_CH6 6

#define	MCP251863_ICODE_FIFO_CH7 7

#define	MCP251863_ICODE_FIFO_CH8 8

#define	MCP251863_ICODE_FIFO_CH9 9

#define	MCP251863_ICODE_FIFO_CH10 10

#define	MCP251863_ICODE_FIFO_CH11 11

#define	MCP251863_ICODE_FIFO_CH12 12

#define	MCP251863_ICODE_FIFO_CH13 13

#define	MCP251863_ICODE_FIFO_CH14 14

#define	MCP251863_ICODE_FIFO_CH15 15

#define	MCP251863_ICODE_FIFO_CH16 16

#define	MCP251863_ICODE_FIFO_CH17 17

#define	MCP251863_ICODE_FIFO_CH18 18

#define	MCP251863_ICODE_FIFO_CH19 19

#define	MCP251863_ICODE_FIFO_CH20 20

#define	MCP251863_ICODE_FIFO_CH21 21

#define	MCP251863_ICODE_FIFO_CH22 22

#define	MCP251863_ICODE_FIFO_CH23 23

#define	MCP251863_ICODE_FIFO_CH24 24

#define	MCP251863_ICODE_FIFO_CH25 25

#define	MCP251863_ICODE_FIFO_CH26 26

#define	MCP251863_ICODE_FIFO_CH27 27

#define	MCP251863_ICODE_FIFO_CH28 28

#define	MCP251863_ICODE_FIFO_CH29 29

#define	MCP251863_ICODE_FIFO_CH30 30

#define	MCP251863_ICODE_FIFO_CH31 31

#define	MCP251863_ICODE_TOTAL_CHANNELS 32

#define	MCP251863_ICODE_NO_INT 64

#define	MCP251863_ICODE_CERRIF 65

#define	MCP251863_ICODE_WAKIF 66

#define	MCP251863_ICODE_RXOVIF 67

#define	MCP251863_ICODE_ADDRERR_SERRIF 68

#define	MCP251863_ICODE_MABOV_SERRIF 69

#define	MCP251863_ICODE_TBCIF 70

#define	MCP251863_ICODE_MODIF 71

#define	MCP251863_ICODE_IVMIF 72

#define	MCP251863_ICODE_TEFIF 73

#define	MCP251863_ICODE_TXATIF 74

#define	MCP251863_ICODE_RESERVED 75

#define	MCP251863_RXCODE_FIFO_CH0 0
	MCP251863 RX FIFO channel.

#define	MCP251863_RXCODE_FIFO_CH1 1

#define	MCP251863_RXCODE_FIFO_CH2 2

#define	MCP251863_RXCODE_FIFO_CH3 3

#define	MCP251863_RXCODE_FIFO_CH4 4

#define	MCP251863_RXCODE_FIFO_CH5 5

#define	MCP251863_RXCODE_FIFO_CH6 6

#define	MCP251863_RXCODE_FIFO_CH7 7

#define	MCP251863_RXCODE_FIFO_CH8 8

#define	MCP251863_RXCODE_FIFO_CH9 9

#define	MCP251863_RXCODE_FIFO_CH10 10

#define	MCP251863_RXCODE_FIFO_CH11 11

#define	MCP251863_RXCODE_FIFO_CH12 12

#define	MCP251863_RXCODE_FIFO_CH13 13

#define	MCP251863_RXCODE_FIFO_CH14 14

#define	MCP251863_RXCODE_FIFO_CH15 15

#define	MCP251863_RXCODE_FIFO_CH16 16

#define	MCP251863_RXCODE_FIFO_CH17 17

#define	MCP251863_RXCODE_FIFO_CH18 18

#define	MCP251863_RXCODE_FIFO_CH19 19

#define	MCP251863_RXCODE_FIFO_CH20 20

#define	MCP251863_RXCODE_FIFO_CH21 21

#define	MCP251863_RXCODE_FIFO_CH22 22

#define	MCP251863_RXCODE_FIFO_CH23 23

#define	MCP251863_RXCODE_FIFO_CH24 24

#define	MCP251863_RXCODE_FIFO_CH25 25

#define	MCP251863_RXCODE_FIFO_CH26 26

#define	MCP251863_RXCODE_FIFO_CH27 27

#define	MCP251863_RXCODE_FIFO_CH28 28

#define	MCP251863_RXCODE_FIFO_CH29 29

#define	MCP251863_RXCODE_FIFO_CH30 30

#define	MCP251863_RXCODE_FIFO_CH31 31

#define	MCP251863_RXCODE_TOTAL_CHANNELS 32

#define	MCP251863_RXCODE_NO_INT 64

#define	MCP251863_RXCODE_RESERVED 65

#define	MCP251863_TXCODE_FIFO_CH0 0
	MCP251863 TX FIFO channel.

#define	MCP251863_TXCODE_FIFO_CH1 1

#define	MCP251863_TXCODE_FIFO_CH2 2

#define	MCP251863_TXCODE_FIFO_CH3 3

#define	MCP251863_TXCODE_FIFO_CH4 4

#define	MCP251863_TXCODE_FIFO_CH5 5

#define	MCP251863_TXCODE_FIFO_CH6 6

#define	MCP251863_TXCODE_FIFO_CH7 7

#define	MCP251863_TXCODE_FIFO_CH8 8

#define	MCP251863_TXCODE_FIFO_CH9 9

#define	MCP251863_TXCODE_FIFO_CH10 10

#define	MCP251863_TXCODE_FIFO_CH11 11

#define	MCP251863_TXCODE_FIFO_CH12 12

#define	MCP251863_TXCODE_FIFO_CH13 13

#define	MCP251863_TXCODE_FIFO_CH14 14

#define	MCP251863_TXCODE_FIFO_CH15 15

#define	MCP251863_TXCODE_FIFO_CH16 16

#define	MCP251863_TXCODE_FIFO_CH17 17

#define	MCP251863_TXCODE_FIFO_CH18 18

#define	MCP251863_TXCODE_FIFO_CH19 19

#define	MCP251863_TXCODE_FIFO_CH20 20

#define	MCP251863_TXCODE_FIFO_CH21 21

#define	MCP251863_TXCODE_FIFO_CH22 22

#define	MCP251863_TXCODE_FIFO_CH23 23

#define	MCP251863_TXCODE_FIFO_CH24 24

#define	MCP251863_TXCODE_FIFO_CH25 25

#define	MCP251863_TXCODE_FIFO_CH26 26

#define	MCP251863_TXCODE_FIFO_CH27 27

#define	MCP251863_TXCODE_FIFO_CH28 28

#define	MCP251863_TXCODE_FIFO_CH29 29

#define	MCP251863_TXCODE_FIFO_CH30 30

#define	MCP251863_TXCODE_FIFO_CH31 31

#define	MCP251863_TXCODE_TOTAL_CHANNELS 32

#define	MCP251863_TXCODE_NO_INT 64

#define	MCP251863_TXCODE_RESERVED 65

#define	MCP251863_SYSCLK_40M 0
	MCP251863 system clock.

#define	MCP251863_SYSCLK_20M 1

#define	MCP251863_SYSCLK_10M 2

#define	MCP251863_CLKO_DIV1 0
	MCP251863 clock devider.

#define	MCP251863_CLKO_DIV2 1

#define	MCP251863_CLKO_DIV4 2

#define	MCP251863_CLKO_DIV10 3

#define	N_MCP251863_FIFO_REGS ( MCP251863_FIFO_TOTAL_CHANNELS * MCP251863_FIFO_OFFSET )

#define	N_MCP251863_FILT_CTRL_REGS ( MCP251863_FILT_TOTAL / 4 )

#define	N_MCP251863_FILT_OBJ_REGS ( MCP251863_FILT_TOTAL * MCP251863_FILTER_OFFSET )

#define	MCP251863_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE
	Data sample selection.

#define	MCP251863_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE

Detailed Description

MCP251863 description register.

Specified register for description of MCP251863 Click driver.

Settings for registers of MCP251863 Click driver.

Macro Definition Documentation

◆ CAN_TXQUEUE_CH0

#define CAN_TXQUEUE_CH0 MCP251863_FIFO_CH0

◆ MCP251863_1000K_4M

#define MCP251863_1000K_4M 15

◆ MCP251863_1000K_8M

#define MCP251863_1000K_8M 16

◆ MCP251863_125K_500K

#define MCP251863_125K_500K 17

◆ MCP251863_250K_1M

#define MCP251863_250K_1M 10

◆ MCP251863_250K_1M5

#define MCP251863_250K_1M5 11

◆ MCP251863_250K_2M

#define MCP251863_250K_2M 12

◆ MCP251863_250K_3M

#define MCP251863_250K_3M 13

◆ MCP251863_250K_4M

#define MCP251863_250K_4M 14

◆ MCP251863_250K_500K

#define MCP251863_250K_500K 8

◆ MCP251863_250K_833K

#define MCP251863_250K_833K 9

◆ MCP251863_500K_10M

#define MCP251863_500K_10M 7

◆ MCP251863_500K_1M

#define MCP251863_500K_1M 0

◆ MCP251863_500K_2M

#define MCP251863_500K_2M 1

◆ MCP251863_500K_3M

#define MCP251863_500K_3M 2

◆ MCP251863_500K_4M

#define MCP251863_500K_4M 3

◆ MCP251863_500K_5M

#define MCP251863_500K_5M 4

◆ MCP251863_500K_6M7

#define MCP251863_500K_6M7 5

◆ MCP251863_500K_8M

#define MCP251863_500K_8M 6

◆ MCP251863_ALL_EVENTS

#define MCP251863_ALL_EVENTS 0xFF1F

◆ MCP251863_BUS_ERROR_EVENT

#define MCP251863_BUS_ERROR_EVENT 0x2000

◆ MCP251863_BUS_WAKEUP_EVENT

#define MCP251863_BUS_WAKEUP_EVENT 0x4000

◆ MCP251863_CLASSIC_MODE

#define MCP251863_CLASSIC_MODE 0x06

◆ MCP251863_CLKO_CLOCK

#define MCP251863_CLKO_CLOCK 0

◆ MCP251863_CLKO_DIV1

#define MCP251863_CLKO_DIV1 0

MCP251863 clock devider.

Specified setting for clock devider of MCP251863 Click driver.

◆ MCP251863_CLKO_DIV10

#define MCP251863_CLKO_DIV10 3

◆ MCP251863_CLKO_DIV2

#define MCP251863_CLKO_DIV2 1

◆ MCP251863_CLKO_DIV4

#define MCP251863_CLKO_DIV4 2

◆ MCP251863_CLKO_SOF

#define MCP251863_CLKO_SOF 1

◆ MCP251863_CONFIG_MODE

#define MCP251863_CONFIG_MODE 0x04

◆ MCP251863_CRC_ALL_EVENTS

#define MCP251863_CRC_ALL_EVENTS 0x03

◆ MCP251863_CRC_CRCERR_EVENT

#define MCP251863_CRC_CRCERR_EVENT 0x01

◆ MCP251863_CRC_FORMERR_EVENT

#define MCP251863_CRC_FORMERR_EVENT 0x02

◆ MCP251863_CRC_NO_EVENT

#define MCP251863_CRC_NO_EVENT 0x00

◆ MCP251863_DBT_10M

#define MCP251863_DBT_10M 10

◆ MCP251863_DBT_1M

#define MCP251863_DBT_1M 2

◆ MCP251863_DBT_1M5

#define MCP251863_DBT_1M5 3

◆ MCP251863_DBT_2M

#define MCP251863_DBT_2M 4

◆ MCP251863_DBT_3M

#define MCP251863_DBT_3M 5

◆ MCP251863_DBT_4M

#define MCP251863_DBT_4M 6

◆ MCP251863_DBT_500K

#define MCP251863_DBT_500K 0

◆ MCP251863_DBT_5M

#define MCP251863_DBT_5M 7

◆ MCP251863_DBT_6M7

#define MCP251863_DBT_6M7 8

◆ MCP251863_DBT_833K

#define MCP251863_DBT_833K 1

◆ MCP251863_DBT_8M

#define MCP251863_DBT_8M 9

◆ MCP251863_DLC_0

#define MCP251863_DLC_0 0

MCP251863 CAN Data Length Code.

Specified setting for CAN data length code of MCP251863 Click driver.

◆ MCP251863_DLC_1

#define MCP251863_DLC_1 1

◆ MCP251863_DLC_12

#define MCP251863_DLC_12 9

◆ MCP251863_DLC_16

#define MCP251863_DLC_16 10

◆ MCP251863_DLC_2

#define MCP251863_DLC_2 2

◆ MCP251863_DLC_20

#define MCP251863_DLC_20 11

◆ MCP251863_DLC_24

#define MCP251863_DLC_24 12

◆ MCP251863_DLC_3

#define MCP251863_DLC_3 3

◆ MCP251863_DLC_32

#define MCP251863_DLC_32 13

◆ MCP251863_DLC_4

#define MCP251863_DLC_4 4

◆ MCP251863_DLC_48

#define MCP251863_DLC_48 14

◆ MCP251863_DLC_5

#define MCP251863_DLC_5 5

◆ MCP251863_DLC_6

#define MCP251863_DLC_6 6

◆ MCP251863_DLC_64

#define MCP251863_DLC_64 15

◆ MCP251863_DLC_7

#define MCP251863_DLC_7 7

◆ MCP251863_DLC_8

#define MCP251863_DLC_8 8

◆ MCP251863_DNET_FILT_DISABLE

#define MCP251863_DNET_FILT_DISABLE 0

MCP251863 Data Byte Filter Number.

Specified setting for data byte filter number of MCP251863 Click driver.

◆ MCP251863_DNET_FILT_SIZE_10_BIT

#define MCP251863_DNET_FILT_SIZE_10_BIT 10

◆ MCP251863_DNET_FILT_SIZE_11_BIT

#define MCP251863_DNET_FILT_SIZE_11_BIT 11

◆ MCP251863_DNET_FILT_SIZE_12_BIT

#define MCP251863_DNET_FILT_SIZE_12_BIT 12

◆ MCP251863_DNET_FILT_SIZE_13_BIT

#define MCP251863_DNET_FILT_SIZE_13_BIT 13

◆ MCP251863_DNET_FILT_SIZE_14_BIT

#define MCP251863_DNET_FILT_SIZE_14_BIT 14

◆ MCP251863_DNET_FILT_SIZE_15_BIT

#define MCP251863_DNET_FILT_SIZE_15_BIT 15

◆ MCP251863_DNET_FILT_SIZE_16_BIT

#define MCP251863_DNET_FILT_SIZE_16_BIT 16

◆ MCP251863_DNET_FILT_SIZE_17_BIT

#define MCP251863_DNET_FILT_SIZE_17_BIT 17

◆ MCP251863_DNET_FILT_SIZE_18_BIT

#define MCP251863_DNET_FILT_SIZE_18_BIT 18

◆ MCP251863_DNET_FILT_SIZE_1_BIT

#define MCP251863_DNET_FILT_SIZE_1_BIT 1

◆ MCP251863_DNET_FILT_SIZE_2_BIT

#define MCP251863_DNET_FILT_SIZE_2_BIT 2

◆ MCP251863_DNET_FILT_SIZE_3_BIT

#define MCP251863_DNET_FILT_SIZE_3_BIT 3

◆ MCP251863_DNET_FILT_SIZE_4_BIT

#define MCP251863_DNET_FILT_SIZE_4_BIT 4

◆ MCP251863_DNET_FILT_SIZE_5_BIT

#define MCP251863_DNET_FILT_SIZE_5_BIT 5

◆ MCP251863_DNET_FILT_SIZE_6_BIT

#define MCP251863_DNET_FILT_SIZE_6_BIT 6

◆ MCP251863_DNET_FILT_SIZE_7_BIT

#define MCP251863_DNET_FILT_SIZE_7_BIT 7

◆ MCP251863_DNET_FILT_SIZE_8_BIT

#define MCP251863_DNET_FILT_SIZE_8_BIT 8

◆ MCP251863_DNET_FILT_SIZE_9_BIT

#define MCP251863_DNET_FILT_SIZE_9_BIT 9

◆ MCP251863_ERROR_ALL

#define MCP251863_ERROR_ALL 0x3F

◆ MCP251863_ERROR_FREE_STATE

#define MCP251863_ERROR_FREE_STATE 0

◆ MCP251863_EXT_LOOP_MODE

#define MCP251863_EXT_LOOP_MODE 0x05

◆ MCP251863_FIFO_CH0

#define MCP251863_FIFO_CH0 0

MCP251863 description setting.

Specified setting for description of MCP251863 Click driver.

MCP251863 CAN FIFO Channels.

Specified setting for CAN FIFO channels of MCP251863 Click driver.

◆ MCP251863_FIFO_CH1

#define MCP251863_FIFO_CH1 1

◆ MCP251863_FIFO_CH10

#define MCP251863_FIFO_CH10 10

◆ MCP251863_FIFO_CH11

#define MCP251863_FIFO_CH11 11

◆ MCP251863_FIFO_CH12

#define MCP251863_FIFO_CH12 12

◆ MCP251863_FIFO_CH13

#define MCP251863_FIFO_CH13 13

◆ MCP251863_FIFO_CH14

#define MCP251863_FIFO_CH14 14

◆ MCP251863_FIFO_CH15

#define MCP251863_FIFO_CH15 15

◆ MCP251863_FIFO_CH16

#define MCP251863_FIFO_CH16 16

◆ MCP251863_FIFO_CH17

#define MCP251863_FIFO_CH17 17

◆ MCP251863_FIFO_CH18

#define MCP251863_FIFO_CH18 18

◆ MCP251863_FIFO_CH19

#define MCP251863_FIFO_CH19 19

◆ MCP251863_FIFO_CH2

#define MCP251863_FIFO_CH2 2

◆ MCP251863_FIFO_CH20

#define MCP251863_FIFO_CH20 20

◆ MCP251863_FIFO_CH21

#define MCP251863_FIFO_CH21 21

◆ MCP251863_FIFO_CH22

#define MCP251863_FIFO_CH22 22

◆ MCP251863_FIFO_CH23

#define MCP251863_FIFO_CH23 23

◆ MCP251863_FIFO_CH24

#define MCP251863_FIFO_CH24 24

◆ MCP251863_FIFO_CH25

#define MCP251863_FIFO_CH25 25

◆ MCP251863_FIFO_CH26

#define MCP251863_FIFO_CH26 26

◆ MCP251863_FIFO_CH27

#define MCP251863_FIFO_CH27 27

◆ MCP251863_FIFO_CH28

#define MCP251863_FIFO_CH28 28

◆ MCP251863_FIFO_CH29

#define MCP251863_FIFO_CH29 29

◆ MCP251863_FIFO_CH3

#define MCP251863_FIFO_CH3 3

◆ MCP251863_FIFO_CH30

#define MCP251863_FIFO_CH30 30

◆ MCP251863_FIFO_CH31

#define MCP251863_FIFO_CH31 31

◆ MCP251863_FIFO_CH4

#define MCP251863_FIFO_CH4 4

◆ MCP251863_FIFO_CH5

#define MCP251863_FIFO_CH5 5

◆ MCP251863_FIFO_CH6

#define MCP251863_FIFO_CH6 6

◆ MCP251863_FIFO_CH7

#define MCP251863_FIFO_CH7 7

◆ MCP251863_FIFO_CH8

#define MCP251863_FIFO_CH8 8

◆ MCP251863_FIFO_CH9

#define MCP251863_FIFO_CH9 9

◆ MCP251863_FIFO_FIRST_CHANNEL

#define MCP251863_FIFO_FIRST_CHANNEL MCP251863_FIFO_CH1

◆ MCP251863_FIFO_TOTAL_CHANNELS

#define MCP251863_FIFO_TOTAL_CHANNELS 32

◆ MCP251863_FILT0

#define MCP251863_FILT0 0

MCP251863 CAN Filter Channels.

Specified setting for CAN filter channels of MCP251863 Click driver.

◆ MCP251863_FILT1

#define MCP251863_FILT1 1

◆ MCP251863_FILT10

#define MCP251863_FILT10 10

◆ MCP251863_FILT11

#define MCP251863_FILT11 11

◆ MCP251863_FILT12

#define MCP251863_FILT12 12

◆ MCP251863_FILT13

#define MCP251863_FILT13 13

◆ MCP251863_FILT14

#define MCP251863_FILT14 14

◆ MCP251863_FILT15

#define MCP251863_FILT15 15

◆ MCP251863_FILT16

#define MCP251863_FILT16 16

◆ MCP251863_FILT17

#define MCP251863_FILT17 17

◆ MCP251863_FILT18

#define MCP251863_FILT18 18

◆ MCP251863_FILT19

#define MCP251863_FILT19 19

◆ MCP251863_FILT2

#define MCP251863_FILT2 2

◆ MCP251863_FILT20

#define MCP251863_FILT20 20

◆ MCP251863_FILT21

#define MCP251863_FILT21 21

◆ MCP251863_FILT22

#define MCP251863_FILT22 22

◆ MCP251863_FILT23

#define MCP251863_FILT23 23

◆ MCP251863_FILT24

#define MCP251863_FILT24 24

◆ MCP251863_FILT25

#define MCP251863_FILT25 25

◆ MCP251863_FILT26

#define MCP251863_FILT26 26

◆ MCP251863_FILT27

#define MCP251863_FILT27 27

◆ MCP251863_FILT28

#define MCP251863_FILT28 28

◆ MCP251863_FILT29

#define MCP251863_FILT29 29

◆ MCP251863_FILT3

#define MCP251863_FILT3 3

◆ MCP251863_FILT30

#define MCP251863_FILT30 30

◆ MCP251863_FILT31

#define MCP251863_FILT31 31

◆ MCP251863_FILT4

#define MCP251863_FILT4 4

◆ MCP251863_FILT5

#define MCP251863_FILT5 5

◆ MCP251863_FILT6

#define MCP251863_FILT6 6

◆ MCP251863_FILT7

#define MCP251863_FILT7 7

◆ MCP251863_FILT8

#define MCP251863_FILT8 8

◆ MCP251863_FILT9

#define MCP251863_FILT9 9

◆ MCP251863_FILT_TOTAL

#define MCP251863_FILT_TOTAL 32

◆ MCP251863_ICODE_ADDRERR_SERRIF

#define MCP251863_ICODE_ADDRERR_SERRIF 68

◆ MCP251863_ICODE_CERRIF

#define MCP251863_ICODE_CERRIF 65

◆ MCP251863_ICODE_FIFO_CH0

#define MCP251863_ICODE_FIFO_CH0 0

MCP251863 FIFO channel.

Specified setting for FIFO channel of MCP251863 Click driver.

◆ MCP251863_ICODE_FIFO_CH1

#define MCP251863_ICODE_FIFO_CH1 1

◆ MCP251863_ICODE_FIFO_CH10

#define MCP251863_ICODE_FIFO_CH10 10

◆ MCP251863_ICODE_FIFO_CH11

#define MCP251863_ICODE_FIFO_CH11 11

◆ MCP251863_ICODE_FIFO_CH12

#define MCP251863_ICODE_FIFO_CH12 12

◆ MCP251863_ICODE_FIFO_CH13

#define MCP251863_ICODE_FIFO_CH13 13

◆ MCP251863_ICODE_FIFO_CH14

#define MCP251863_ICODE_FIFO_CH14 14

◆ MCP251863_ICODE_FIFO_CH15

#define MCP251863_ICODE_FIFO_CH15 15

◆ MCP251863_ICODE_FIFO_CH16

#define MCP251863_ICODE_FIFO_CH16 16

◆ MCP251863_ICODE_FIFO_CH17

#define MCP251863_ICODE_FIFO_CH17 17

◆ MCP251863_ICODE_FIFO_CH18

#define MCP251863_ICODE_FIFO_CH18 18

◆ MCP251863_ICODE_FIFO_CH19

#define MCP251863_ICODE_FIFO_CH19 19

◆ MCP251863_ICODE_FIFO_CH2

#define MCP251863_ICODE_FIFO_CH2 2

◆ MCP251863_ICODE_FIFO_CH20

#define MCP251863_ICODE_FIFO_CH20 20

◆ MCP251863_ICODE_FIFO_CH21

#define MCP251863_ICODE_FIFO_CH21 21

◆ MCP251863_ICODE_FIFO_CH22

#define MCP251863_ICODE_FIFO_CH22 22

◆ MCP251863_ICODE_FIFO_CH23

#define MCP251863_ICODE_FIFO_CH23 23

◆ MCP251863_ICODE_FIFO_CH24

#define MCP251863_ICODE_FIFO_CH24 24

◆ MCP251863_ICODE_FIFO_CH25

#define MCP251863_ICODE_FIFO_CH25 25

◆ MCP251863_ICODE_FIFO_CH26

#define MCP251863_ICODE_FIFO_CH26 26

◆ MCP251863_ICODE_FIFO_CH27

#define MCP251863_ICODE_FIFO_CH27 27

◆ MCP251863_ICODE_FIFO_CH28

#define MCP251863_ICODE_FIFO_CH28 28

◆ MCP251863_ICODE_FIFO_CH29

#define MCP251863_ICODE_FIFO_CH29 29

◆ MCP251863_ICODE_FIFO_CH3

#define MCP251863_ICODE_FIFO_CH3 3

◆ MCP251863_ICODE_FIFO_CH30

#define MCP251863_ICODE_FIFO_CH30 30

◆ MCP251863_ICODE_FIFO_CH31

#define MCP251863_ICODE_FIFO_CH31 31

◆ MCP251863_ICODE_FIFO_CH4

#define MCP251863_ICODE_FIFO_CH4 4

◆ MCP251863_ICODE_FIFO_CH5

#define MCP251863_ICODE_FIFO_CH5 5

◆ MCP251863_ICODE_FIFO_CH6

#define MCP251863_ICODE_FIFO_CH6 6

◆ MCP251863_ICODE_FIFO_CH7

#define MCP251863_ICODE_FIFO_CH7 7

◆ MCP251863_ICODE_FIFO_CH8

#define MCP251863_ICODE_FIFO_CH8 8

◆ MCP251863_ICODE_FIFO_CH9

#define MCP251863_ICODE_FIFO_CH9 9

◆ MCP251863_ICODE_IVMIF

#define MCP251863_ICODE_IVMIF 72

◆ MCP251863_ICODE_MABOV_SERRIF

#define MCP251863_ICODE_MABOV_SERRIF 69

◆ MCP251863_ICODE_MODIF

#define MCP251863_ICODE_MODIF 71

◆ MCP251863_ICODE_NO_INT

#define MCP251863_ICODE_NO_INT 64

◆ MCP251863_ICODE_RESERVED

#define MCP251863_ICODE_RESERVED 75

◆ MCP251863_ICODE_RXOVIF

#define MCP251863_ICODE_RXOVIF 67

◆ MCP251863_ICODE_TBCIF

#define MCP251863_ICODE_TBCIF 70

◆ MCP251863_ICODE_TEFIF

#define MCP251863_ICODE_TEFIF 73

◆ MCP251863_ICODE_TOTAL_CHANNELS

#define MCP251863_ICODE_TOTAL_CHANNELS 32

◆ MCP251863_ICODE_TXATIF

#define MCP251863_ICODE_TXATIF 74

◆ MCP251863_ICODE_WAKIF

#define MCP251863_ICODE_WAKIF 66

◆ MCP251863_INT_LOOP_MODE

#define MCP251863_INT_LOOP_MODE 0x02

◆ MCP251863_INVALID_MODE

#define MCP251863_INVALID_MODE 0xFF

◆ MCP251863_LISTEN_ONLY_MODE

#define MCP251863_LISTEN_ONLY_MODE 0x03

◆ MCP251863_NBT_125K

#define MCP251863_NBT_125K 0

◆ MCP251863_NBT_1M

#define MCP251863_NBT_1M 3

◆ MCP251863_NBT_250K

#define MCP251863_NBT_250K 1

◆ MCP251863_NBT_500K

#define MCP251863_NBT_500K 2

◆ MCP251863_NO_EVENT

#define MCP251863_NO_EVENT 0

◆ MCP251863_NORMAL_MODE

#define MCP251863_NORMAL_MODE 0x00

MCP251863 CAN Operation Modes.

Specified setting for CAN operation modes of MCP251863 Click driver.

◆ MCP251863_OPENDRAIN

#define MCP251863_OPENDRAIN 1

◆ MCP251863_OPERATION_MODE_CHANGE_EVENT

#define MCP251863_OPERATION_MODE_CHANGE_EVENT 0x0008

◆ MCP251863_PIN_0

#define MCP251863_PIN_0 0

MCP251863 Pin mode.

Specified setting for pin mode of MCP251863 Click driver.

◆ MCP251863_PIN_1

#define MCP251863_PIN_1 1

◆ MCP251863_PINHIGH

#define MCP251863_PINHIGH 1

◆ MCP251863_PININ

#define MCP251863_PININ 1

◆ MCP251863_PINLOW

#define MCP251863_PINLOW 0

◆ MCP251863_PINMODE_GPIO

#define MCP251863_PINMODE_GPIO 1

◆ MCP251863_PINMODE_INT

#define MCP251863_PINMODE_INT 0

◆ MCP251863_PINOUT

#define MCP251863_PINOUT 0

◆ MCP251863_PLSIZE_12

#define MCP251863_PLSIZE_12 1

◆ MCP251863_PLSIZE_16

#define MCP251863_PLSIZE_16 2

◆ MCP251863_PLSIZE_20

#define MCP251863_PLSIZE_20 3

◆ MCP251863_PLSIZE_24

#define MCP251863_PLSIZE_24 4

◆ MCP251863_PLSIZE_32

#define MCP251863_PLSIZE_32 5

◆ MCP251863_PLSIZE_48

#define MCP251863_PLSIZE_48 6

◆ MCP251863_PLSIZE_64

#define MCP251863_PLSIZE_64 7

◆ MCP251863_PLSIZE_8

#define MCP251863_PLSIZE_8 0

MCP251863 FIFO Payload Size.

Specified setting for FIFO payload size of MCP251863 Click driver.

◆ MCP251863_PUSHPULL

#define MCP251863_PUSHPULL 0

◆ MCP251863_RAM_ECC_EVENT

#define MCP251863_RAM_ECC_EVENT 0x0100

◆ MCP251863_RESTRICT_MODE

#define MCP251863_RESTRICT_MODE 0x07

◆ MCP251863_RX_BUS_PASSIVE_STATE

#define MCP251863_RX_BUS_PASSIVE_STATE 0x08

◆ MCP251863_RX_EVENT

#define MCP251863_RX_EVENT 0x0002

◆ MCP251863_RX_FIFO_ALL_EVENTS

#define MCP251863_RX_FIFO_ALL_EVENTS 0x0F

◆ MCP251863_RX_FIFO_EMPTY

#define MCP251863_RX_FIFO_EMPTY 0

MCP251863 CAN RX FIFO Status.

Specified setting for CAN RX FIFO status of MCP251863 Click driver.

◆ MCP251863_RX_FIFO_FULL

#define MCP251863_RX_FIFO_FULL 0x04

◆ MCP251863_RX_FIFO_FULL_EVENT

#define MCP251863_RX_FIFO_FULL_EVENT 0x04

◆ MCP251863_RX_FIFO_HALF_FULL

#define MCP251863_RX_FIFO_HALF_FULL 0x02

◆ MCP251863_RX_FIFO_HALF_FULL_EVENT

#define MCP251863_RX_FIFO_HALF_FULL_EVENT 0x02

◆ MCP251863_RX_FIFO_NO_EVENT

#define MCP251863_RX_FIFO_NO_EVENT 0

◆ MCP251863_RX_FIFO_NOT_EMPTY

#define MCP251863_RX_FIFO_NOT_EMPTY 0x01

◆ MCP251863_RX_FIFO_NOT_EMPTY_EVENT

#define MCP251863_RX_FIFO_NOT_EMPTY_EVENT 0x01

◆ MCP251863_RX_FIFO_OVERFLOW

#define MCP251863_RX_FIFO_OVERFLOW 0x08

◆ MCP251863_RX_FIFO_OVERFLOW_EVENT

#define MCP251863_RX_FIFO_OVERFLOW_EVENT 0x08

◆ MCP251863_RX_FIFO_STATUS_MASK

#define MCP251863_RX_FIFO_STATUS_MASK 0x0F

◆ MCP251863_RX_INVALID_MESSAGE_EVENT

#define MCP251863_RX_INVALID_MESSAGE_EVENT 0x8000

◆ MCP251863_RX_OVERFLOW_EVENT

#define MCP251863_RX_OVERFLOW_EVENT 0x0800

◆ MCP251863_RX_WARNING_STATE

#define MCP251863_RX_WARNING_STATE 0x02

◆ MCP251863_RXCODE_FIFO_CH0

#define MCP251863_RXCODE_FIFO_CH0 0

MCP251863 RX FIFO channel.

Specified setting for RX FIFO channel of MCP251863 Click driver.

◆ MCP251863_RXCODE_FIFO_CH1

#define MCP251863_RXCODE_FIFO_CH1 1

◆ MCP251863_RXCODE_FIFO_CH10

#define MCP251863_RXCODE_FIFO_CH10 10

◆ MCP251863_RXCODE_FIFO_CH11

#define MCP251863_RXCODE_FIFO_CH11 11

◆ MCP251863_RXCODE_FIFO_CH12

#define MCP251863_RXCODE_FIFO_CH12 12

◆ MCP251863_RXCODE_FIFO_CH13

#define MCP251863_RXCODE_FIFO_CH13 13

◆ MCP251863_RXCODE_FIFO_CH14

#define MCP251863_RXCODE_FIFO_CH14 14

◆ MCP251863_RXCODE_FIFO_CH15

#define MCP251863_RXCODE_FIFO_CH15 15

◆ MCP251863_RXCODE_FIFO_CH16

#define MCP251863_RXCODE_FIFO_CH16 16

◆ MCP251863_RXCODE_FIFO_CH17

#define MCP251863_RXCODE_FIFO_CH17 17

◆ MCP251863_RXCODE_FIFO_CH18

#define MCP251863_RXCODE_FIFO_CH18 18

◆ MCP251863_RXCODE_FIFO_CH19

#define MCP251863_RXCODE_FIFO_CH19 19

◆ MCP251863_RXCODE_FIFO_CH2

#define MCP251863_RXCODE_FIFO_CH2 2

◆ MCP251863_RXCODE_FIFO_CH20

#define MCP251863_RXCODE_FIFO_CH20 20

◆ MCP251863_RXCODE_FIFO_CH21

#define MCP251863_RXCODE_FIFO_CH21 21

◆ MCP251863_RXCODE_FIFO_CH22

#define MCP251863_RXCODE_FIFO_CH22 22

◆ MCP251863_RXCODE_FIFO_CH23

#define MCP251863_RXCODE_FIFO_CH23 23

◆ MCP251863_RXCODE_FIFO_CH24

#define MCP251863_RXCODE_FIFO_CH24 24

◆ MCP251863_RXCODE_FIFO_CH25

#define MCP251863_RXCODE_FIFO_CH25 25

◆ MCP251863_RXCODE_FIFO_CH26

#define MCP251863_RXCODE_FIFO_CH26 26

◆ MCP251863_RXCODE_FIFO_CH27

#define MCP251863_RXCODE_FIFO_CH27 27

◆ MCP251863_RXCODE_FIFO_CH28

#define MCP251863_RXCODE_FIFO_CH28 28

◆ MCP251863_RXCODE_FIFO_CH29

#define MCP251863_RXCODE_FIFO_CH29 29

◆ MCP251863_RXCODE_FIFO_CH3

#define MCP251863_RXCODE_FIFO_CH3 3

◆ MCP251863_RXCODE_FIFO_CH30

#define MCP251863_RXCODE_FIFO_CH30 30

◆ MCP251863_RXCODE_FIFO_CH31

#define MCP251863_RXCODE_FIFO_CH31 31

◆ MCP251863_RXCODE_FIFO_CH4

#define MCP251863_RXCODE_FIFO_CH4 4

◆ MCP251863_RXCODE_FIFO_CH5

#define MCP251863_RXCODE_FIFO_CH5 5

◆ MCP251863_RXCODE_FIFO_CH6

#define MCP251863_RXCODE_FIFO_CH6 6

◆ MCP251863_RXCODE_FIFO_CH7

#define MCP251863_RXCODE_FIFO_CH7 7

◆ MCP251863_RXCODE_FIFO_CH8

#define MCP251863_RXCODE_FIFO_CH8 8

◆ MCP251863_RXCODE_FIFO_CH9

#define MCP251863_RXCODE_FIFO_CH9 9

◆ MCP251863_RXCODE_NO_INT

#define MCP251863_RXCODE_NO_INT 64

◆ MCP251863_RXCODE_RESERVED

#define MCP251863_RXCODE_RESERVED 65

◆ MCP251863_RXCODE_TOTAL_CHANNELS

#define MCP251863_RXCODE_TOTAL_CHANNELS 32

◆ MCP251863_SET_DATA_SAMPLE_EDGE

#define MCP251863_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE

Data sample selection.

This macro sets data samples for SPI modules.

Note: Available only on Microchip PIC family devices. This macro will set data sampling for all SPI modules on MCU. Can be overwritten with mcp251863_init which will set SET_SPI_DATA_SAMPLE_MIDDLE by default on the mapped mikrobus.

◆ MCP251863_SET_DATA_SAMPLE_MIDDLE

#define MCP251863_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE

◆ MCP251863_SLEEP_MODE

#define MCP251863_SLEEP_MODE 0x01

◆ MCP251863_SPI_CRC_EVENT

#define MCP251863_SPI_CRC_EVENT 0x0200

◆ MCP251863_SSP_MODE_AUTO

#define MCP251863_SSP_MODE_AUTO 2

◆ MCP251863_SSP_MODE_MANUAL

#define MCP251863_SSP_MODE_MANUAL 1

◆ MCP251863_SSP_MODE_OFF

#define MCP251863_SSP_MODE_OFF 0

◆ MCP251863_SYSCLK_10M

#define MCP251863_SYSCLK_10M 2

◆ MCP251863_SYSCLK_20M

#define MCP251863_SYSCLK_20M 1

◆ MCP251863_SYSCLK_40M

#define MCP251863_SYSCLK_40M 0

MCP251863 system clock.

Specified setting for system clock of MCP251863 Click driver.

◆ MCP251863_SYSTEM_ERROR_EVENT

#define MCP251863_SYSTEM_ERROR_EVENT 0x1000

◆ MCP251863_TEF_EVENT

#define MCP251863_TEF_EVENT 0x0010

◆ MCP251863_TEF_FIFO_ALL_EVENTS

#define MCP251863_TEF_FIFO_ALL_EVENTS 0x0F

◆ MCP251863_TEF_FIFO_EMPTY

#define MCP251863_TEF_FIFO_EMPTY 0

MCP251863 CAN TEF FIFO Status.

Specified setting for CAN TEF FIFO status of MCP251863 Click driver.

◆ MCP251863_TEF_FIFO_FULL

#define MCP251863_TEF_FIFO_FULL 0x04

◆ MCP251863_TEF_FIFO_FULL_EVENT

#define MCP251863_TEF_FIFO_FULL_EVENT 0x04

◆ MCP251863_TEF_FIFO_HALF_FULL

#define MCP251863_TEF_FIFO_HALF_FULL 0x02

◆ MCP251863_TEF_FIFO_HALF_FULL_EVENT

#define MCP251863_TEF_FIFO_HALF_FULL_EVENT 0x02

◆ MCP251863_TEF_FIFO_NO_EVENT

#define MCP251863_TEF_FIFO_NO_EVENT 0

◆ MCP251863_TEF_FIFO_NOT_EMPTY

#define MCP251863_TEF_FIFO_NOT_EMPTY 0x01

◆ MCP251863_TEF_FIFO_NOT_EMPTY_EVENT

#define MCP251863_TEF_FIFO_NOT_EMPTY_EVENT 0x01

◆ MCP251863_TEF_FIFO_OVERFLOW

#define MCP251863_TEF_FIFO_OVERFLOW 0x08

◆ MCP251863_TEF_FIFO_OVERFLOW_EVENT

#define MCP251863_TEF_FIFO_OVERFLOW_EVENT 0x08

◆ MCP251863_TEF_FIFO_STATUS_MASK

#define MCP251863_TEF_FIFO_STATUS_MASK 0x0F

◆ MCP251863_TIME_BASE_COUNTER_EVENT

#define MCP251863_TIME_BASE_COUNTER_EVENT 0x0004

◆ MCP251863_TS_EOF

#define MCP251863_TS_EOF 0x01

◆ MCP251863_TS_RES

#define MCP251863_TS_RES 0x02

◆ MCP251863_TS_SOF

#define MCP251863_TS_SOF 0x00

◆ MCP251863_TX_ATTEMPTS_EVENT

#define MCP251863_TX_ATTEMPTS_EVENT 0x0400

◆ MCP251863_TX_BUS_OFF_STATE

#define MCP251863_TX_BUS_OFF_STATE 0x20

◆ MCP251863_TX_BUS_PASSIVE_STATE

#define MCP251863_TX_BUS_PASSIVE_STATE 0x10

◆ MCP251863_TX_EVENT

#define MCP251863_TX_EVENT 0x0001

◆ MCP251863_TX_FIFO_ABORTED

#define MCP251863_TX_FIFO_ABORTED 0x80

◆ MCP251863_TX_FIFO_ALL_EVENTS

#define MCP251863_TX_FIFO_ALL_EVENTS 0x17

◆ MCP251863_TX_FIFO_ARBITRATION_LOST

#define MCP251863_TX_FIFO_ARBITRATION_LOST 0x40

◆ MCP251863_TX_FIFO_ATTEMPTS_EXHAUSTED

#define MCP251863_TX_FIFO_ATTEMPTS_EXHAUSTED 0x10

◆ MCP251863_TX_FIFO_ATTEMPTS_EXHAUSTED_EVENT

#define MCP251863_TX_FIFO_ATTEMPTS_EXHAUSTED_EVENT 0x10

◆ MCP251863_TX_FIFO_EMPTY

#define MCP251863_TX_FIFO_EMPTY 0x04

◆ MCP251863_TX_FIFO_EMPTY_EVENT

#define MCP251863_TX_FIFO_EMPTY_EVENT 0x04

◆ MCP251863_TX_FIFO_ERROR

#define MCP251863_TX_FIFO_ERROR 0x20

◆ MCP251863_TX_FIFO_FULL

#define MCP251863_TX_FIFO_FULL 0

MCP251863 CAN TX FIFO Status.

Specified setting for CAN TX FIFO status of MCP251863 Click driver.

◆ MCP251863_TX_FIFO_HALF_FULL

#define MCP251863_TX_FIFO_HALF_FULL 0x02

◆ MCP251863_TX_FIFO_HALF_FULL_EVENT

#define MCP251863_TX_FIFO_HALF_FULL_EVENT 0x02

◆ MCP251863_TX_FIFO_NO_EVENT

#define MCP251863_TX_FIFO_NO_EVENT 0

MCP251863 CAN Module Events.

Specified setting for CAN module events of MCP251863 Click driver.

◆ MCP251863_TX_FIFO_NOT_FULL

#define MCP251863_TX_FIFO_NOT_FULL 0x01

◆ MCP251863_TX_FIFO_NOT_FULL_EVENT

#define MCP251863_TX_FIFO_NOT_FULL_EVENT 0x01

◆ MCP251863_TX_FIFO_STATUS_MASK

#define MCP251863_TX_FIFO_STATUS_MASK 0x1F7

◆ MCP251863_TX_FIFO_TRANSMITTING

#define MCP251863_TX_FIFO_TRANSMITTING 0x100

◆ MCP251863_TX_RX_WARNING_STATE

#define MCP251863_TX_RX_WARNING_STATE 0x01

◆ MCP251863_TX_WARNING_STATE

#define MCP251863_TX_WARNING_STATE 0x04

◆ MCP251863_TXBWS_1024

#define MCP251863_TXBWS_1024 10

◆ MCP251863_TXBWS_128

#define MCP251863_TXBWS_128 7

◆ MCP251863_TXBWS_16

#define MCP251863_TXBWS_16 4

◆ MCP251863_TXBWS_2

#define MCP251863_TXBWS_2 1

◆ MCP251863_TXBWS_2048

#define MCP251863_TXBWS_2048 11

◆ MCP251863_TXBWS_256

#define MCP251863_TXBWS_256 8

◆ MCP251863_TXBWS_32

#define MCP251863_TXBWS_32 5

◆ MCP251863_TXBWS_4

#define MCP251863_TXBWS_4 2

◆ MCP251863_TXBWS_4096

#define MCP251863_TXBWS_4096 12

◆ MCP251863_TXBWS_512

#define MCP251863_TXBWS_512 9

◆ MCP251863_TXBWS_64

#define MCP251863_TXBWS_64 6

◆ MCP251863_TXBWS_8

#define MCP251863_TXBWS_8 3

◆ MCP251863_TXBWS_NO_DELAY

#define MCP251863_TXBWS_NO_DELAY 0

MCP251863 Transmit Bandwidth Sharing.

Specified setting for transmit bandwidth sharing of MCP251863 Click driver.

◆ MCP251863_TXCODE_FIFO_CH0

#define MCP251863_TXCODE_FIFO_CH0 0

MCP251863 TX FIFO channel.

Specified setting for TX FIFO channel of MCP251863 Click driver.

◆ MCP251863_TXCODE_FIFO_CH1

#define MCP251863_TXCODE_FIFO_CH1 1

◆ MCP251863_TXCODE_FIFO_CH10

#define MCP251863_TXCODE_FIFO_CH10 10

◆ MCP251863_TXCODE_FIFO_CH11

#define MCP251863_TXCODE_FIFO_CH11 11

◆ MCP251863_TXCODE_FIFO_CH12

#define MCP251863_TXCODE_FIFO_CH12 12

◆ MCP251863_TXCODE_FIFO_CH13

#define MCP251863_TXCODE_FIFO_CH13 13

◆ MCP251863_TXCODE_FIFO_CH14

#define MCP251863_TXCODE_FIFO_CH14 14

◆ MCP251863_TXCODE_FIFO_CH15

#define MCP251863_TXCODE_FIFO_CH15 15

◆ MCP251863_TXCODE_FIFO_CH16

#define MCP251863_TXCODE_FIFO_CH16 16

◆ MCP251863_TXCODE_FIFO_CH17

#define MCP251863_TXCODE_FIFO_CH17 17

◆ MCP251863_TXCODE_FIFO_CH18

#define MCP251863_TXCODE_FIFO_CH18 18

◆ MCP251863_TXCODE_FIFO_CH19

#define MCP251863_TXCODE_FIFO_CH19 19

◆ MCP251863_TXCODE_FIFO_CH2

#define MCP251863_TXCODE_FIFO_CH2 2

◆ MCP251863_TXCODE_FIFO_CH20

#define MCP251863_TXCODE_FIFO_CH20 20

◆ MCP251863_TXCODE_FIFO_CH21

#define MCP251863_TXCODE_FIFO_CH21 21

◆ MCP251863_TXCODE_FIFO_CH22

#define MCP251863_TXCODE_FIFO_CH22 22

◆ MCP251863_TXCODE_FIFO_CH23

#define MCP251863_TXCODE_FIFO_CH23 23

◆ MCP251863_TXCODE_FIFO_CH24

#define MCP251863_TXCODE_FIFO_CH24 24

◆ MCP251863_TXCODE_FIFO_CH25

#define MCP251863_TXCODE_FIFO_CH25 25

◆ MCP251863_TXCODE_FIFO_CH26

#define MCP251863_TXCODE_FIFO_CH26 26

◆ MCP251863_TXCODE_FIFO_CH27

#define MCP251863_TXCODE_FIFO_CH27 27

◆ MCP251863_TXCODE_FIFO_CH28

#define MCP251863_TXCODE_FIFO_CH28 28

◆ MCP251863_TXCODE_FIFO_CH29

#define MCP251863_TXCODE_FIFO_CH29 29

◆ MCP251863_TXCODE_FIFO_CH3

#define MCP251863_TXCODE_FIFO_CH3 3

◆ MCP251863_TXCODE_FIFO_CH30

#define MCP251863_TXCODE_FIFO_CH30 30

◆ MCP251863_TXCODE_FIFO_CH31

#define MCP251863_TXCODE_FIFO_CH31 31

◆ MCP251863_TXCODE_FIFO_CH4

#define MCP251863_TXCODE_FIFO_CH4 4

◆ MCP251863_TXCODE_FIFO_CH5

#define MCP251863_TXCODE_FIFO_CH5 5

◆ MCP251863_TXCODE_FIFO_CH6

#define MCP251863_TXCODE_FIFO_CH6 6

◆ MCP251863_TXCODE_FIFO_CH7

#define MCP251863_TXCODE_FIFO_CH7 7

◆ MCP251863_TXCODE_FIFO_CH8

#define MCP251863_TXCODE_FIFO_CH8 8

◆ MCP251863_TXCODE_FIFO_CH9

#define MCP251863_TXCODE_FIFO_CH9 9

◆ MCP251863_TXCODE_NO_INT

#define MCP251863_TXCODE_NO_INT 64

◆ MCP251863_TXCODE_RESERVED

#define MCP251863_TXCODE_RESERVED 65

◆ MCP251863_TXCODE_TOTAL_CHANNELS

#define MCP251863_TXCODE_TOTAL_CHANNELS 32

◆ MCP251863_TXREQ_CH0

#define MCP251863_TXREQ_CH0 0x00000001

MCP251863 TX req channel.

Specified setting for TX req channel of MCP251863 Click driver.

◆ MCP251863_TXREQ_CH1

#define MCP251863_TXREQ_CH1 0x00000002

◆ MCP251863_TXREQ_CH10

#define MCP251863_TXREQ_CH10 0x00000400

◆ MCP251863_TXREQ_CH11

#define MCP251863_TXREQ_CH11 0x00000800

◆ MCP251863_TXREQ_CH12

#define MCP251863_TXREQ_CH12 0x00001000

◆ MCP251863_TXREQ_CH13

#define MCP251863_TXREQ_CH13 0x00002000

◆ MCP251863_TXREQ_CH14

#define MCP251863_TXREQ_CH14 0x00004000

◆ MCP251863_TXREQ_CH15

#define MCP251863_TXREQ_CH15 0x00008000

◆ MCP251863_TXREQ_CH16

#define MCP251863_TXREQ_CH16 0x00010000

◆ MCP251863_TXREQ_CH17

#define MCP251863_TXREQ_CH17 0x00020000

◆ MCP251863_TXREQ_CH18

#define MCP251863_TXREQ_CH18 0x00040000

◆ MCP251863_TXREQ_CH19

#define MCP251863_TXREQ_CH19 0x00080000

◆ MCP251863_TXREQ_CH2

#define MCP251863_TXREQ_CH2 0x00000004

◆ MCP251863_TXREQ_CH20

#define MCP251863_TXREQ_CH20 0x00100000

◆ MCP251863_TXREQ_CH21

#define MCP251863_TXREQ_CH21 0x00200000

◆ MCP251863_TXREQ_CH22

#define MCP251863_TXREQ_CH22 0x00400000

◆ MCP251863_TXREQ_CH23

#define MCP251863_TXREQ_CH23 0x00800000

◆ MCP251863_TXREQ_CH24

#define MCP251863_TXREQ_CH24 0x01000000

◆ MCP251863_TXREQ_CH25

#define MCP251863_TXREQ_CH25 0x02000000

◆ MCP251863_TXREQ_CH26

#define MCP251863_TXREQ_CH26 0x04000000

◆ MCP251863_TXREQ_CH27

#define MCP251863_TXREQ_CH27 0x08000000

◆ MCP251863_TXREQ_CH28

#define MCP251863_TXREQ_CH28 0x10000000

◆ MCP251863_TXREQ_CH29

#define MCP251863_TXREQ_CH29 0x20000000

◆ MCP251863_TXREQ_CH3

#define MCP251863_TXREQ_CH3 0x00000008

◆ MCP251863_TXREQ_CH30

#define MCP251863_TXREQ_CH30 0x40000000

◆ MCP251863_TXREQ_CH31

#define MCP251863_TXREQ_CH31 0x80000000

◆ MCP251863_TXREQ_CH4

#define MCP251863_TXREQ_CH4 0x00000010

◆ MCP251863_TXREQ_CH5

#define MCP251863_TXREQ_CH5 0x00000020

◆ MCP251863_TXREQ_CH6

#define MCP251863_TXREQ_CH6 0x00000040

◆ MCP251863_TXREQ_CH7

#define MCP251863_TXREQ_CH7 0x00000080

◆ MCP251863_TXREQ_CH8

#define MCP251863_TXREQ_CH8 0x00000100

◆ MCP251863_TXREQ_CH9

#define MCP251863_TXREQ_CH9 0x00000200

◆ MCP251863_WFT00

#define MCP251863_WFT00 0

MCP251863 Wake-up Filter Time.

Specified setting for wake-up filter time of MCP251863 Click driver.

◆ MCP251863_WFT01

#define MCP251863_WFT01 1

◆ MCP251863_WFT10

#define MCP251863_WFT10 2

◆ MCP251863_WFT11

#define MCP251863_WFT11 3

◆ MCP2518_ECC_ALL_EVENTS

#define MCP2518_ECC_ALL_EVENTS 0x06

◆ MCP2518_ECC_DED_EVENT

#define MCP2518_ECC_DED_EVENT 0x04

◆ MCP2518_ECC_NO_EVENT

#define MCP2518_ECC_NO_EVENT 0x00

◆ MCP2518_ECC_SEC_EVENT

#define MCP2518_ECC_SEC_EVENT 0x02

◆ N_MCP251863_FIFO_REGS

#define N_MCP251863_FIFO_REGS ( MCP251863_FIFO_TOTAL_CHANNELS * MCP251863_FIFO_OFFSET )

◆ N_MCP251863_FILT_CTRL_REGS

#define N_MCP251863_FILT_CTRL_REGS ( MCP251863_FILT_TOTAL / 4 )

◆ N_MCP251863_FILT_OBJ_REGS

#define N_MCP251863_FILT_OBJ_REGS ( MCP251863_FILT_TOTAL * MCP251863_FILTER_OFFSET )

Macros