Macros
#define	MPU9DOF_BIT_SLEEP 0x40

#define	MPU9DOF_BIT_H_RESET 0x80

#define	MPU9DOF_BITS_CLKSEL 0x07

#define	MPU9DOF_MPU_CLK_SEL_PLLGYROX 0x01

#define	MPU9DOF_MPU_CLK_SEL_PLLGYROZ 0x03

#define	MPU9DOF_MPU_EXT_SYNC_GYROX 0x02

#define	MPU9DOF_BITS_AFSL_SEL_2G 0x00

#define	MPU9DOF_BITS_AFSL_SEL_4G 0x08

#define	MPU9DOF_BITS_AFSL_SEL_8G 0x10

#define	MPU9DOF_BITS_AFSL_SEL_16G 0x18

#define	MPU9DOF_BITS_FS_250DPS 0x00

#define	MPU9DOF_BITS_FS_500DPS 0x08

#define	MPU9DOF_BITS_FS_1000DPS 0x10

#define	MPU9DOF_BITS_FS_2000DPS 0x18

#define	MPU9DOF_BITS_FS_MASK 0x18

#define	MPU9DOF_BITS_DLPF_CFG_256HZ_NOLPF2 0x00

#define	MPU9DOF_BITS_DLPF_CFG_188HZ 0x01

#define	MPU9DOF_BITS_DLPF_CFG_98HZ 0x02

#define	MPU9DOF_BITS_DLPF_CFG_42HZ 0x03

#define	MPU9DOF_BITS_DLPF_CFG_20HZ 0x04

#define	MPU9DOF_BITS_DLPF_CFG_10HZ 0x05

#define	MPU9DOF_BITS_DLPF_CFG_5HZ 0x06

#define	MPU9DOF_BITS_DLPF_CFG_2100HZ_NOLPF 0x07

#define	MPU9DOF_BITS_DLPF_CFG_MASK 0x07

#define	MPU9DOF_BIT_INT_ANYRD_2CLEAR 0x10

#define	MPU9DOF_BIT_RAW_RDY_EN 0x01

#define	MPU9DOF_BIT_I2C_IF_DIS 0x10

#define	MPU9DOF_BIT_INT_PIN_CFG 0x02

#define	MPU9DOF_BIT_FIFO_EN 0x78

#define	MPU9DOF_BIT_FIFO_DIS 0x00

#define	MPU9DOF_DEFAULT 0x00

Detailed Description

Macro Definition Documentation

◆ MPU9DOF_BIT_FIFO_DIS

#define MPU9DOF_BIT_FIFO_DIS 0x00

◆ MPU9DOF_BIT_FIFO_EN

#define MPU9DOF_BIT_FIFO_EN 0x78

◆ MPU9DOF_BIT_H_RESET

#define MPU9DOF_BIT_H_RESET 0x80

◆ MPU9DOF_BIT_I2C_IF_DIS

#define MPU9DOF_BIT_I2C_IF_DIS 0x10

◆ MPU9DOF_BIT_INT_ANYRD_2CLEAR

#define MPU9DOF_BIT_INT_ANYRD_2CLEAR 0x10

◆ MPU9DOF_BIT_INT_PIN_CFG

#define MPU9DOF_BIT_INT_PIN_CFG 0x02

◆ MPU9DOF_BIT_RAW_RDY_EN

#define MPU9DOF_BIT_RAW_RDY_EN 0x01

◆ MPU9DOF_BIT_SLEEP

#define MPU9DOF_BIT_SLEEP 0x40

◆ MPU9DOF_BITS_AFSL_SEL_16G

#define MPU9DOF_BITS_AFSL_SEL_16G 0x18

◆ MPU9DOF_BITS_AFSL_SEL_2G

#define MPU9DOF_BITS_AFSL_SEL_2G 0x00

◆ MPU9DOF_BITS_AFSL_SEL_4G

#define MPU9DOF_BITS_AFSL_SEL_4G 0x08

◆ MPU9DOF_BITS_AFSL_SEL_8G

#define MPU9DOF_BITS_AFSL_SEL_8G 0x10

◆ MPU9DOF_BITS_CLKSEL

#define MPU9DOF_BITS_CLKSEL 0x07

◆ MPU9DOF_BITS_DLPF_CFG_10HZ

#define MPU9DOF_BITS_DLPF_CFG_10HZ 0x05

◆ MPU9DOF_BITS_DLPF_CFG_188HZ

#define MPU9DOF_BITS_DLPF_CFG_188HZ 0x01

◆ MPU9DOF_BITS_DLPF_CFG_20HZ

#define MPU9DOF_BITS_DLPF_CFG_20HZ 0x04

◆ MPU9DOF_BITS_DLPF_CFG_2100HZ_NOLPF

#define MPU9DOF_BITS_DLPF_CFG_2100HZ_NOLPF 0x07

◆ MPU9DOF_BITS_DLPF_CFG_256HZ_NOLPF2

#define MPU9DOF_BITS_DLPF_CFG_256HZ_NOLPF2 0x00

◆ MPU9DOF_BITS_DLPF_CFG_42HZ

#define MPU9DOF_BITS_DLPF_CFG_42HZ 0x03

◆ MPU9DOF_BITS_DLPF_CFG_5HZ

#define MPU9DOF_BITS_DLPF_CFG_5HZ 0x06

◆ MPU9DOF_BITS_DLPF_CFG_98HZ

#define MPU9DOF_BITS_DLPF_CFG_98HZ 0x02

◆ MPU9DOF_BITS_DLPF_CFG_MASK

#define MPU9DOF_BITS_DLPF_CFG_MASK 0x07

◆ MPU9DOF_BITS_FS_1000DPS

#define MPU9DOF_BITS_FS_1000DPS 0x10

◆ MPU9DOF_BITS_FS_2000DPS

#define MPU9DOF_BITS_FS_2000DPS 0x18

◆ MPU9DOF_BITS_FS_250DPS

#define MPU9DOF_BITS_FS_250DPS 0x00

◆ MPU9DOF_BITS_FS_500DPS

#define MPU9DOF_BITS_FS_500DPS 0x08

◆ MPU9DOF_BITS_FS_MASK

#define MPU9DOF_BITS_FS_MASK 0x18

◆ MPU9DOF_DEFAULT

#define MPU9DOF_DEFAULT 0x00

◆ MPU9DOF_MPU_CLK_SEL_PLLGYROX

#define MPU9DOF_MPU_CLK_SEL_PLLGYROX 0x01

◆ MPU9DOF_MPU_CLK_SEL_PLLGYROZ

#define MPU9DOF_MPU_CLK_SEL_PLLGYROZ 0x03

◆ MPU9DOF_MPU_EXT_SYNC_GYROX

#define MPU9DOF_MPU_EXT_SYNC_GYROX 0x02

Macros