Settings for registers of MRAM 3 Click driver. More...

Macros
#define	MRAM3_STATUS_WPEN 0x80
	MRAM 3 status register settings.

#define	MRAM3_STATUS_SNPEN 0x40

#define	MRAM3_STATUS_TBSEL_BOTTOM 0x20

#define	MRAM3_STATUS_TBSEL_TOP 0x00

#define	MRAM3_STATUS_BPSEL_NONE 0x00

#define	MRAM3_STATUS_BPSEL_UPPER_1_64 0x04

#define	MRAM3_STATUS_BPSEL_UPPER_1_32 0x08

#define	MRAM3_STATUS_BPSEL_UPPER_1_16 0x0C

#define	MRAM3_STATUS_BPSEL_UPPER_1_8 0x10

#define	MRAM3_STATUS_BPSEL_UPPER_QUARTER 0x14

#define	MRAM3_STATUS_BPSEL_UPPER_HALF 0x18

#define	MRAM3_STATUS_BPSEL_ALL 0x1C

#define	MRAM3_STATUS_WREN 0x02

#define	MRAM3_CONFIG1_MAPLK_LOCK 0x04
	MRAM 3 config registers settings.

#define	MRAM3_CONFIG1_MAPLK_UNLOCK 0x00

#define	MRAM3_CONFIG1_ASPLK_LOCK 0x01

#define	MRAM3_CONFIG1_ASPLK_UNLOCK 0x00

#define	MRAM3_CONFIG2_QUAD_SPI 0x40

#define	MRAM3_CONFIG2_DUAL_SPI 0x10

#define	MRAM3_CONFIG2_MLATS_0_CYCLES 0x00

#define	MRAM3_CONFIG2_MLATS_1_CYCLE 0x01

#define	MRAM3_CONFIG2_MLATS_2_CYCLES 0x02

#define	MRAM3_CONFIG2_MLATS_3_CYCLES 0x03

#define	MRAM3_CONFIG2_MLATS_4_CYCLES 0x04

#define	MRAM3_CONFIG2_MLATS_5_CYCLES 0x05

#define	MRAM3_CONFIG2_MLATS_6_CYCLES 0x06

#define	MRAM3_CONFIG2_MLATS_7_CYCLES 0x07

#define	MRAM3_CONFIG2_MLATS_8_CYCLES 0x08

#define	MRAM3_CONFIG2_MLATS_9_CYCLES 0x09

#define	MRAM3_CONFIG2_MLATS_10_CYCLES 0x0A

#define	MRAM3_CONFIG2_MLATS_11_CYCLES 0x0B

#define	MRAM3_CONFIG2_MLATS_12_CYCLES 0x0C

#define	MRAM3_CONFIG2_MLATS_13_CYCLES 0x0D

#define	MRAM3_CONFIG2_MLATS_14_CYCLES 0x0E

#define	MRAM3_CONFIG2_MLATS_15_CYCLES 0x0F

#define	MRAM3_CONFIG3_ODSEL_35OHM 0x00

#define	MRAM3_CONFIG3_ODSEL_75OHM 0x20

#define	MRAM3_CONFIG3_ODSEL_60OHM 0x40

#define	MRAM3_CONFIG3_ODSEL_45OHM 0x60

#define	MRAM3_CONFIG3_ODSEL_40OHM 0xA0

#define	MRAM3_CONFIG3_ODSEL_20OHM 0xC0

#define	MRAM3_CONFIG3_ODSEL_15OHM 0xE0

#define	MRAM3_CONFIG3_WRAPS_ENABLE 0x10

#define	MRAM3_CONFIG3_WRPLS_16BYTE 0x00

#define	MRAM3_CONFIG3_WRPLS_32BYTE 0x01

#define	MRAM3_CONFIG3_WRPLS_64BYTE 0x02

#define	MRAM3_CONFIG3_WRPLS_128BYTE 0x03

#define	MRAM3_CONFIG3_WRPLS_256BYTE 0x04

#define	MRAM3_CONFIG4_WRENS_NORMAL 0x04

#define	MRAM3_CONFIG4_WRENS_SRAM 0x05

#define	MRAM3_CONFIG4_WRENS_BACK_TO_BACK 0x06

#define	MRAM3_MIN_ADDRESS 0x000000
	MRAM 3 memory address range.

#define	MRAM3_MAX_ADDRESS 0x01FFFFul

#define	MRAM3_DEVICE_ID 0xE6010102ul
	MRAM 3 device ID.

#define	MRAM3_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE
	Data sample selection.

#define	MRAM3_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE

Detailed Description

Settings for registers of MRAM 3 Click driver.

Macro Definition Documentation

◆ MRAM3_CONFIG1_ASPLK_LOCK

#define MRAM3_CONFIG1_ASPLK_LOCK 0x01

◆ MRAM3_CONFIG1_ASPLK_UNLOCK

#define MRAM3_CONFIG1_ASPLK_UNLOCK 0x00

◆ MRAM3_CONFIG1_MAPLK_LOCK

#define MRAM3_CONFIG1_MAPLK_LOCK 0x04

MRAM 3 config registers settings.

Specified config registers settings of MRAM 3 Click driver.

◆ MRAM3_CONFIG1_MAPLK_UNLOCK

#define MRAM3_CONFIG1_MAPLK_UNLOCK 0x00

◆ MRAM3_CONFIG2_DUAL_SPI

#define MRAM3_CONFIG2_DUAL_SPI 0x10

◆ MRAM3_CONFIG2_MLATS_0_CYCLES

#define MRAM3_CONFIG2_MLATS_0_CYCLES 0x00

◆ MRAM3_CONFIG2_MLATS_10_CYCLES

#define MRAM3_CONFIG2_MLATS_10_CYCLES 0x0A

◆ MRAM3_CONFIG2_MLATS_11_CYCLES

#define MRAM3_CONFIG2_MLATS_11_CYCLES 0x0B

◆ MRAM3_CONFIG2_MLATS_12_CYCLES

#define MRAM3_CONFIG2_MLATS_12_CYCLES 0x0C

◆ MRAM3_CONFIG2_MLATS_13_CYCLES

#define MRAM3_CONFIG2_MLATS_13_CYCLES 0x0D

◆ MRAM3_CONFIG2_MLATS_14_CYCLES

#define MRAM3_CONFIG2_MLATS_14_CYCLES 0x0E

◆ MRAM3_CONFIG2_MLATS_15_CYCLES

#define MRAM3_CONFIG2_MLATS_15_CYCLES 0x0F

◆ MRAM3_CONFIG2_MLATS_1_CYCLE

#define MRAM3_CONFIG2_MLATS_1_CYCLE 0x01

◆ MRAM3_CONFIG2_MLATS_2_CYCLES

#define MRAM3_CONFIG2_MLATS_2_CYCLES 0x02

◆ MRAM3_CONFIG2_MLATS_3_CYCLES

#define MRAM3_CONFIG2_MLATS_3_CYCLES 0x03

◆ MRAM3_CONFIG2_MLATS_4_CYCLES

#define MRAM3_CONFIG2_MLATS_4_CYCLES 0x04

◆ MRAM3_CONFIG2_MLATS_5_CYCLES

#define MRAM3_CONFIG2_MLATS_5_CYCLES 0x05

◆ MRAM3_CONFIG2_MLATS_6_CYCLES

#define MRAM3_CONFIG2_MLATS_6_CYCLES 0x06

◆ MRAM3_CONFIG2_MLATS_7_CYCLES

#define MRAM3_CONFIG2_MLATS_7_CYCLES 0x07

◆ MRAM3_CONFIG2_MLATS_8_CYCLES

#define MRAM3_CONFIG2_MLATS_8_CYCLES 0x08

◆ MRAM3_CONFIG2_MLATS_9_CYCLES

#define MRAM3_CONFIG2_MLATS_9_CYCLES 0x09

◆ MRAM3_CONFIG2_QUAD_SPI

#define MRAM3_CONFIG2_QUAD_SPI 0x40

◆ MRAM3_CONFIG3_ODSEL_15OHM

#define MRAM3_CONFIG3_ODSEL_15OHM 0xE0

◆ MRAM3_CONFIG3_ODSEL_20OHM

#define MRAM3_CONFIG3_ODSEL_20OHM 0xC0

◆ MRAM3_CONFIG3_ODSEL_35OHM

#define MRAM3_CONFIG3_ODSEL_35OHM 0x00

◆ MRAM3_CONFIG3_ODSEL_40OHM

#define MRAM3_CONFIG3_ODSEL_40OHM 0xA0

◆ MRAM3_CONFIG3_ODSEL_45OHM

#define MRAM3_CONFIG3_ODSEL_45OHM 0x60

◆ MRAM3_CONFIG3_ODSEL_60OHM

#define MRAM3_CONFIG3_ODSEL_60OHM 0x40

◆ MRAM3_CONFIG3_ODSEL_75OHM

#define MRAM3_CONFIG3_ODSEL_75OHM 0x20

◆ MRAM3_CONFIG3_WRAPS_ENABLE

#define MRAM3_CONFIG3_WRAPS_ENABLE 0x10

◆ MRAM3_CONFIG3_WRPLS_128BYTE

#define MRAM3_CONFIG3_WRPLS_128BYTE 0x03

◆ MRAM3_CONFIG3_WRPLS_16BYTE

#define MRAM3_CONFIG3_WRPLS_16BYTE 0x00

◆ MRAM3_CONFIG3_WRPLS_256BYTE

#define MRAM3_CONFIG3_WRPLS_256BYTE 0x04

◆ MRAM3_CONFIG3_WRPLS_32BYTE

#define MRAM3_CONFIG3_WRPLS_32BYTE 0x01

◆ MRAM3_CONFIG3_WRPLS_64BYTE

#define MRAM3_CONFIG3_WRPLS_64BYTE 0x02

◆ MRAM3_CONFIG4_WRENS_BACK_TO_BACK

#define MRAM3_CONFIG4_WRENS_BACK_TO_BACK 0x06

◆ MRAM3_CONFIG4_WRENS_NORMAL

#define MRAM3_CONFIG4_WRENS_NORMAL 0x04

◆ MRAM3_CONFIG4_WRENS_SRAM

#define MRAM3_CONFIG4_WRENS_SRAM 0x05

◆ MRAM3_DEVICE_ID

#define MRAM3_DEVICE_ID 0xE6010102ul

MRAM 3 device ID.

Specified device ID of MRAM 3 Click driver.

◆ MRAM3_MAX_ADDRESS

#define MRAM3_MAX_ADDRESS 0x01FFFFul

◆ MRAM3_MIN_ADDRESS

#define MRAM3_MIN_ADDRESS 0x000000

MRAM 3 memory address range.

Specified memory address range of MRAM 3 Click driver.

◆ MRAM3_SET_DATA_SAMPLE_EDGE

#define MRAM3_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE

Data sample selection.

This macro sets data samples for SPI modules.

Note: Available only on Microchip PIC family devices. This macro will set data sampling for all SPI modules on MCU. Can be overwritten with mram3_init which will set SET_SPI_DATA_SAMPLE_MIDDLE by default on the mapped mikrobus.

◆ MRAM3_SET_DATA_SAMPLE_MIDDLE

#define MRAM3_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE

◆ MRAM3_STATUS_BPSEL_ALL

#define MRAM3_STATUS_BPSEL_ALL 0x1C

◆ MRAM3_STATUS_BPSEL_NONE

#define MRAM3_STATUS_BPSEL_NONE 0x00

◆ MRAM3_STATUS_BPSEL_UPPER_1_16

#define MRAM3_STATUS_BPSEL_UPPER_1_16 0x0C

◆ MRAM3_STATUS_BPSEL_UPPER_1_32

#define MRAM3_STATUS_BPSEL_UPPER_1_32 0x08

◆ MRAM3_STATUS_BPSEL_UPPER_1_64

#define MRAM3_STATUS_BPSEL_UPPER_1_64 0x04

◆ MRAM3_STATUS_BPSEL_UPPER_1_8

#define MRAM3_STATUS_BPSEL_UPPER_1_8 0x10

◆ MRAM3_STATUS_BPSEL_UPPER_HALF

#define MRAM3_STATUS_BPSEL_UPPER_HALF 0x18

◆ MRAM3_STATUS_BPSEL_UPPER_QUARTER

#define MRAM3_STATUS_BPSEL_UPPER_QUARTER 0x14

◆ MRAM3_STATUS_SNPEN

#define MRAM3_STATUS_SNPEN 0x40

◆ MRAM3_STATUS_TBSEL_BOTTOM

#define MRAM3_STATUS_TBSEL_BOTTOM 0x20

◆ MRAM3_STATUS_TBSEL_TOP

#define MRAM3_STATUS_TBSEL_TOP 0x00

◆ MRAM3_STATUS_WPEN

#define MRAM3_STATUS_WPEN 0x80

MRAM 3 status register settings.

Specified status register settings of MRAM 3 Click driver.

◆ MRAM3_STATUS_WREN

#define MRAM3_STATUS_WREN 0x02

Macros